Thomas Gleixner | c942fdd | 2019-05-27 08:55:06 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Peter De Schrijver | 22b8b85 | 2012-01-26 18:22:03 +0200 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/mach-tegra/cpuidle.c |
| 4 | * |
| 5 | * CPU idle driver for Tegra CPUs |
| 6 | * |
| 7 | * Copyright (c) 2010-2012, NVIDIA Corporation. |
| 8 | * Copyright (c) 2011 Google, Inc. |
| 9 | * Author: Colin Cross <ccross@android.com> |
| 10 | * Gary King <gking@nvidia.com> |
| 11 | * |
| 12 | * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com> |
Peter De Schrijver | 22b8b85 | 2012-01-26 18:22:03 +0200 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
Peter De Schrijver | 22b8b85 | 2012-01-26 18:22:03 +0200 | [diff] [blame] | 17 | |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 18 | #include <soc/tegra/fuse.h> |
| 19 | |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 20 | #include "cpuidle.h" |
Peter De Schrijver | 22b8b85 | 2012-01-26 18:22:03 +0200 | [diff] [blame] | 21 | |
Joseph Lo | e22dc2b | 2013-06-04 18:47:32 +0800 | [diff] [blame] | 22 | void __init tegra_cpuidle_init(void) |
Peter De Schrijver | 22b8b85 | 2012-01-26 18:22:03 +0200 | [diff] [blame] | 23 | { |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 24 | switch (tegra_get_chip_id()) { |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 25 | case TEGRA20: |
Joseph Lo | b046a65 | 2013-06-04 18:47:34 +0800 | [diff] [blame] | 26 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
| 27 | tegra20_cpuidle_init(); |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 28 | break; |
| 29 | case TEGRA30: |
Joseph Lo | b046a65 | 2013-06-04 18:47:34 +0800 | [diff] [blame] | 30 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) |
| 31 | tegra30_cpuidle_init(); |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 32 | break; |
Joseph Lo | 51dc525 | 2013-01-21 17:49:06 +0800 | [diff] [blame] | 33 | case TEGRA114: |
Joseph Lo | 24036fd | 2013-10-11 17:57:32 +0800 | [diff] [blame] | 34 | case TEGRA124: |
| 35 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || |
| 36 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) |
Joseph Lo | b046a65 | 2013-06-04 18:47:34 +0800 | [diff] [blame] | 37 | tegra114_cpuidle_init(); |
Joseph Lo | 0b25e25 | 2012-10-31 17:41:15 +0800 | [diff] [blame] | 38 | break; |
Peter De Schrijver | 22b8b85 | 2012-01-26 18:22:03 +0200 | [diff] [blame] | 39 | } |
Peter De Schrijver | 22b8b85 | 2012-01-26 18:22:03 +0200 | [diff] [blame] | 40 | } |
Stephen Warren | b4f1737 | 2013-05-06 14:19:19 -0600 | [diff] [blame] | 41 | |
| 42 | void tegra_cpuidle_pcie_irqs_in_use(void) |
| 43 | { |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 44 | switch (tegra_get_chip_id()) { |
Stephen Warren | b4f1737 | 2013-05-06 14:19:19 -0600 | [diff] [blame] | 45 | case TEGRA20: |
| 46 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
| 47 | tegra20_cpuidle_pcie_irqs_in_use(); |
| 48 | break; |
| 49 | } |
| 50 | } |