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Florian Fainelli5e95329b2013-03-22 10:50:50 +00001Marvell Distributed Switch Architecture Device Tree Bindings
2------------------------------------------------------------
3
4Required properties:
5- compatible : Should be "marvell,dsa"
6- #address-cells : Must be 2, first cell is the address on the MDIO bus
7 and second cell is the address in the switch tree.
8 Second cell is used only when cascading/chaining.
9- #size-cells : Must be 0
10- dsa,ethernet : Should be a phandle to a valid Ethernet device node
11- dsa,mii-bus : Should be a phandle to a valid MDIO bus device node
12
Guenter Roeck06745722014-10-29 10:45:02 -070013Optional properties:
Florian Fainelli5e95329b2013-03-22 10:50:50 +000014- interrupts : property with a value describing the switch
15 interrupt number (not supported by the driver)
16
17A DSA node can contain multiple switch chips which are therefore child nodes of
18the parent DSA node. The maximum number of allowed child nodes is 4
19(DSA_MAX_SWITCHES).
20Each of these switch child nodes should have the following required properties:
21
Pavel Nakonechny30303812015-04-05 00:46:21 +030022- reg : Contains two fields. The first one describes the
23 address on the MII bus. The second is the switch
24 number that must be unique in cascaded configurations
Florian Fainelli5e95329b2013-03-22 10:50:50 +000025- #address-cells : Must be 1
26- #size-cells : Must be 0
27
Guenter Roeck06745722014-10-29 10:45:02 -070028A switch child node has the following optional property:
29
30- eeprom-length : Set to the length of an EEPROM connected to the
31 switch. Must be set if the switch can not detect
32 the presence and/or size of a connected EEPROM,
33 otherwise optional.
34
Florian Fainelli5e95329b2013-03-22 10:50:50 +000035A switch may have multiple "port" children nodes
36
37Each port children node must have the following mandatory properties:
38- reg : Describes the port address in the switch
39- label : Describes the label associated with this port, special
40 labels are "cpu" to indicate a CPU port and "dsa" to
41 indicate an uplink/downlink port.
42
43Note that a port labelled "dsa" will imply checking for the uplink phandle
44described below.
45
46Optionnal property:
Andrew Lunn1e72e6f2015-08-17 23:52:50 +020047- link : Should be a list of phandles to another switch's DSA port.
Florian Fainelli5e95329b2013-03-22 10:50:50 +000048 This property is only used when switches are being
Andrew Lunn1e72e6f2015-08-17 23:52:50 +020049 chained/cascaded together. This port is used as outgoing port
50 towards the phandle port, which can be more than one hop away.
Florian Fainelli5e95329b2013-03-22 10:50:50 +000051
Florian Fainelli51f26592014-08-27 17:04:57 -070052- phy-handle : Phandle to a PHY on an external MDIO bus, not the
53 switch internal one. See
54 Documentation/devicetree/bindings/net/ethernet.txt
55 for details.
56
57- phy-mode : String representing the connection to the designated
58 PHY node specified by the 'phy-handle' property. See
59 Documentation/devicetree/bindings/net/ethernet.txt
60 for details.
61
Andrew Lunn6bc6d0a2015-08-08 17:09:14 +020062- mii-bus : Should be a phandle to a valid MDIO bus device node.
63 This mii-bus will be used in preference to the
64 global dsa,mii-bus defined above, for this switch.
65
Florian Fainelli51f26592014-08-27 17:04:57 -070066Optional subnodes:
67- fixed-link : Fixed-link subnode describing a link to a non-MDIO
68 managed entity. See
69 Documentation/devicetree/bindings/net/fixed-link.txt
70 for details.
71
Florian Fainelli5e95329b2013-03-22 10:50:50 +000072Example:
73
74 dsa@0 {
75 compatible = "marvell,dsa";
Florian Fainelli4c64f1f2013-03-25 05:03:38 +000076 #address-cells = <2>;
Florian Fainelli5e95329b2013-03-22 10:50:50 +000077 #size-cells = <0>;
78
79 interrupts = <10>;
80 dsa,ethernet = <&ethernet0>;
81 dsa,mii-bus = <&mii_bus0>;
82
83 switch@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 reg = <16 0>; /* MDIO address 16, switch 0 in tree */
87
88 port@0 {
89 reg = <0>;
90 label = "lan1";
Florian Fainelli51f26592014-08-27 17:04:57 -070091 phy-handle = <&phy0>;
Florian Fainelli5e95329b2013-03-22 10:50:50 +000092 };
93
94 port@1 {
95 reg = <1>;
96 label = "lan2";
97 };
98
99 port@5 {
100 reg = <5>;
101 label = "cpu";
102 };
103
Andrew Lunn1e72e6f2015-08-17 23:52:50 +0200104 switch0port6: port@6 {
Florian Fainelli5e95329b2013-03-22 10:50:50 +0000105 reg = <6>;
106 label = "dsa";
Andrew Lunn1e72e6f2015-08-17 23:52:50 +0200107 link = <&switch1port0
108 &switch2port0>;
Florian Fainelli5e95329b2013-03-22 10:50:50 +0000109 };
110 };
111
112 switch@1 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 reg = <17 1>; /* MDIO address 17, switch 1 in tree */
Andrew Lunn6bc6d0a2015-08-08 17:09:14 +0200116 mii-bus = <&mii_bus1>;
Florian Fainelli5e95329b2013-03-22 10:50:50 +0000117
Andrew Lunn1e72e6f2015-08-17 23:52:50 +0200118 switch1port0: port@0 {
Florian Fainelli5e95329b2013-03-22 10:50:50 +0000119 reg = <0>;
120 label = "dsa";
Andrew Lunn1e72e6f2015-08-17 23:52:50 +0200121 link = <&switch0port6>;
122 };
123 switch1port1: port@1 {
124 reg = <1>;
125 label = "dsa";
126 link = <&switch2port1>;
127 };
128 };
129
130 switch@2 {
131 #address-cells = <1>;
132 #size-cells = <0>;
133 reg = <18 2>; /* MDIO address 18, switch 2 in tree */
134 mii-bus = <&mii_bus1>;
135
136 switch2port0: port@0 {
137 reg = <0>;
138 label = "dsa";
139 link = <&switch1port1
140 &switch0port6>;
Florian Fainelli5e95329b2013-03-22 10:50:50 +0000141 };
142 };
143 };