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Flora Fu6df8dd52015-02-22 13:15:29 +01001/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/interrupt.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/of_irq.h>
19#include <linux/regmap.h>
20#include <linux/mfd/core.h>
21#include <linux/mfd/mt6397/core.h>
22#include <linux/mfd/mt6397/registers.h>
23
Eddie Huanga5d7ea02015-05-06 15:23:40 +080024#define MT6397_RTC_BASE 0xe000
25#define MT6397_RTC_SIZE 0x3e
26
John Crispin1d2c25e2016-01-27 12:47:37 +010027#define MT6391_CID_CODE 0x91
28#define MT6397_CID_CODE 0x97
29
Eddie Huanga5d7ea02015-05-06 15:23:40 +080030static const struct resource mt6397_rtc_resources[] = {
31 {
32 .start = MT6397_RTC_BASE,
33 .end = MT6397_RTC_BASE + MT6397_RTC_SIZE,
34 .flags = IORESOURCE_MEM,
35 },
36 {
37 .start = MT6397_IRQ_RTC,
38 .end = MT6397_IRQ_RTC,
39 .flags = IORESOURCE_IRQ,
40 },
41};
42
Flora Fu6df8dd52015-02-22 13:15:29 +010043static const struct mfd_cell mt6397_devs[] = {
44 {
45 .name = "mt6397-rtc",
Eddie Huanga5d7ea02015-05-06 15:23:40 +080046 .num_resources = ARRAY_SIZE(mt6397_rtc_resources),
47 .resources = mt6397_rtc_resources,
Flora Fu6df8dd52015-02-22 13:15:29 +010048 .of_compatible = "mediatek,mt6397-rtc",
49 }, {
50 .name = "mt6397-regulator",
51 .of_compatible = "mediatek,mt6397-regulator",
52 }, {
53 .name = "mt6397-codec",
54 .of_compatible = "mediatek,mt6397-codec",
55 }, {
56 .name = "mt6397-clk",
57 .of_compatible = "mediatek,mt6397-clk",
Hongzhou Yangcf550782015-05-27 02:10:35 -070058 }, {
59 .name = "mt6397-pinctrl",
60 .of_compatible = "mediatek,mt6397-pinctrl",
Flora Fu6df8dd52015-02-22 13:15:29 +010061 },
62};
63
64static void mt6397_irq_lock(struct irq_data *data)
65{
Jiang Liu1e84aa42015-07-13 20:44:56 +000066 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +010067
68 mutex_lock(&mt6397->irqlock);
69}
70
71static void mt6397_irq_sync_unlock(struct irq_data *data)
72{
Jiang Liu1e84aa42015-07-13 20:44:56 +000073 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +010074
John Crispinfeec4792016-01-27 12:47:36 +010075 regmap_write(mt6397->regmap, mt6397->int_con[0],
76 mt6397->irq_masks_cur[0]);
77 regmap_write(mt6397->regmap, mt6397->int_con[1],
78 mt6397->irq_masks_cur[1]);
Flora Fu6df8dd52015-02-22 13:15:29 +010079
80 mutex_unlock(&mt6397->irqlock);
81}
82
83static void mt6397_irq_disable(struct irq_data *data)
84{
Jiang Liu1e84aa42015-07-13 20:44:56 +000085 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +010086 int shift = data->hwirq & 0xf;
87 int reg = data->hwirq >> 4;
88
89 mt6397->irq_masks_cur[reg] &= ~BIT(shift);
90}
91
92static void mt6397_irq_enable(struct irq_data *data)
93{
Jiang Liu1e84aa42015-07-13 20:44:56 +000094 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
Flora Fu6df8dd52015-02-22 13:15:29 +010095 int shift = data->hwirq & 0xf;
96 int reg = data->hwirq >> 4;
97
98 mt6397->irq_masks_cur[reg] |= BIT(shift);
99}
100
Henry Chenf3151ab2015-08-10 21:10:45 +0800101#ifdef CONFIG_PM_SLEEP
102static int mt6397_irq_set_wake(struct irq_data *irq_data, unsigned int on)
103{
104 struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(irq_data);
105 int shift = irq_data->hwirq & 0xf;
106 int reg = irq_data->hwirq >> 4;
107
108 if (on)
109 mt6397->wake_mask[reg] |= BIT(shift);
110 else
111 mt6397->wake_mask[reg] &= ~BIT(shift);
112
113 return 0;
114}
115#else
116#define mt6397_irq_set_wake NULL
117#endif
118
Flora Fu6df8dd52015-02-22 13:15:29 +0100119static struct irq_chip mt6397_irq_chip = {
120 .name = "mt6397-irq",
121 .irq_bus_lock = mt6397_irq_lock,
122 .irq_bus_sync_unlock = mt6397_irq_sync_unlock,
123 .irq_enable = mt6397_irq_enable,
124 .irq_disable = mt6397_irq_disable,
Henry Chenf3151ab2015-08-10 21:10:45 +0800125 .irq_set_wake = mt6397_irq_set_wake,
Flora Fu6df8dd52015-02-22 13:15:29 +0100126};
127
128static void mt6397_irq_handle_reg(struct mt6397_chip *mt6397, int reg,
129 int irqbase)
130{
131 unsigned int status;
132 int i, irq, ret;
133
134 ret = regmap_read(mt6397->regmap, reg, &status);
135 if (ret) {
136 dev_err(mt6397->dev, "Failed to read irq status: %d\n", ret);
137 return;
138 }
139
140 for (i = 0; i < 16; i++) {
141 if (status & BIT(i)) {
142 irq = irq_find_mapping(mt6397->irq_domain, irqbase + i);
143 if (irq)
144 handle_nested_irq(irq);
145 }
146 }
147
148 regmap_write(mt6397->regmap, reg, status);
149}
150
151static irqreturn_t mt6397_irq_thread(int irq, void *data)
152{
153 struct mt6397_chip *mt6397 = data;
154
John Crispinfeec4792016-01-27 12:47:36 +0100155 mt6397_irq_handle_reg(mt6397, mt6397->int_status[0], 0);
156 mt6397_irq_handle_reg(mt6397, mt6397->int_status[1], 16);
Flora Fu6df8dd52015-02-22 13:15:29 +0100157
158 return IRQ_HANDLED;
159}
160
161static int mt6397_irq_domain_map(struct irq_domain *d, unsigned int irq,
162 irq_hw_number_t hw)
163{
164 struct mt6397_chip *mt6397 = d->host_data;
165
166 irq_set_chip_data(irq, mt6397);
167 irq_set_chip_and_handler(irq, &mt6397_irq_chip, handle_level_irq);
168 irq_set_nested_thread(irq, 1);
Flora Fu6df8dd52015-02-22 13:15:29 +0100169 irq_set_noprobe(irq);
Flora Fu6df8dd52015-02-22 13:15:29 +0100170
171 return 0;
172}
173
Krzysztof Kozlowski7ce7b262015-04-27 21:54:13 +0900174static const struct irq_domain_ops mt6397_irq_domain_ops = {
Flora Fu6df8dd52015-02-22 13:15:29 +0100175 .map = mt6397_irq_domain_map,
176};
177
178static int mt6397_irq_init(struct mt6397_chip *mt6397)
179{
180 int ret;
181
182 mutex_init(&mt6397->irqlock);
183
184 /* Mask all interrupt sources */
John Crispinfeec4792016-01-27 12:47:36 +0100185 regmap_write(mt6397->regmap, mt6397->int_con[0], 0x0);
186 regmap_write(mt6397->regmap, mt6397->int_con[1], 0x0);
Flora Fu6df8dd52015-02-22 13:15:29 +0100187
188 mt6397->irq_domain = irq_domain_add_linear(mt6397->dev->of_node,
189 MT6397_IRQ_NR, &mt6397_irq_domain_ops, mt6397);
190 if (!mt6397->irq_domain) {
191 dev_err(mt6397->dev, "could not create irq domain\n");
192 return -ENOMEM;
193 }
194
195 ret = devm_request_threaded_irq(mt6397->dev, mt6397->irq, NULL,
196 mt6397_irq_thread, IRQF_ONESHOT, "mt6397-pmic", mt6397);
197 if (ret) {
198 dev_err(mt6397->dev, "failed to register irq=%d; err: %d\n",
199 mt6397->irq, ret);
200 return ret;
201 }
202
203 return 0;
204}
205
Henry Chenf3151ab2015-08-10 21:10:45 +0800206#ifdef CONFIG_PM_SLEEP
207static int mt6397_irq_suspend(struct device *dev)
208{
209 struct mt6397_chip *chip = dev_get_drvdata(dev);
210
John Crispinfeec4792016-01-27 12:47:36 +0100211 regmap_write(chip->regmap, chip->int_con[0], chip->wake_mask[0]);
212 regmap_write(chip->regmap, chip->int_con[1], chip->wake_mask[1]);
Henry Chenf3151ab2015-08-10 21:10:45 +0800213
214 enable_irq_wake(chip->irq);
215
216 return 0;
217}
218
219static int mt6397_irq_resume(struct device *dev)
220{
221 struct mt6397_chip *chip = dev_get_drvdata(dev);
222
John Crispinfeec4792016-01-27 12:47:36 +0100223 regmap_write(chip->regmap, chip->int_con[0], chip->irq_masks_cur[0]);
224 regmap_write(chip->regmap, chip->int_con[1], chip->irq_masks_cur[1]);
Henry Chenf3151ab2015-08-10 21:10:45 +0800225
226 disable_irq_wake(chip->irq);
227
228 return 0;
229}
230#endif
231
232static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_irq_suspend,
233 mt6397_irq_resume);
234
Flora Fu6df8dd52015-02-22 13:15:29 +0100235static int mt6397_probe(struct platform_device *pdev)
236{
237 int ret;
John Crispin1d2c25e2016-01-27 12:47:37 +0100238 unsigned int id;
239 struct mt6397_chip *pmic;
Flora Fu6df8dd52015-02-22 13:15:29 +0100240
John Crispin1d2c25e2016-01-27 12:47:37 +0100241 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
242 if (!pmic)
Flora Fu6df8dd52015-02-22 13:15:29 +0100243 return -ENOMEM;
244
John Crispin1d2c25e2016-01-27 12:47:37 +0100245 pmic->dev = &pdev->dev;
John Crispinfeec4792016-01-27 12:47:36 +0100246
Flora Fu6df8dd52015-02-22 13:15:29 +0100247 /*
248 * mt6397 MFD is child device of soc pmic wrapper.
249 * Regmap is set from its parent.
250 */
John Crispin1d2c25e2016-01-27 12:47:37 +0100251 pmic->regmap = dev_get_regmap(pdev->dev.parent, NULL);
252 if (!pmic->regmap)
Flora Fu6df8dd52015-02-22 13:15:29 +0100253 return -ENODEV;
254
John Crispin1d2c25e2016-01-27 12:47:37 +0100255 platform_set_drvdata(pdev, pmic);
Flora Fu6df8dd52015-02-22 13:15:29 +0100256
John Crispin1d2c25e2016-01-27 12:47:37 +0100257 ret = regmap_read(pmic->regmap, MT6397_CID, &id);
258 if (ret) {
259 dev_err(pmic->dev, "Failed to read chip id: %d\n", ret);
260 goto fail_irq;
261 }
262
263 switch (id & 0xff) {
264 case MT6397_CID_CODE:
265 case MT6391_CID_CODE:
266 pmic->int_con[0] = MT6397_INT_CON0;
267 pmic->int_con[1] = MT6397_INT_CON1;
268 pmic->int_status[0] = MT6397_INT_STATUS0;
269 pmic->int_status[1] = MT6397_INT_STATUS1;
270 ret = mfd_add_devices(&pdev->dev, -1, mt6397_devs,
271 ARRAY_SIZE(mt6397_devs), NULL, 0, NULL);
272 break;
273
274 default:
275 dev_err(&pdev->dev, "unsupported chip: %d\n", id);
276 ret = -ENODEV;
277 break;
278 }
279
280 pmic->irq = platform_get_irq(pdev, 0);
281 if (pmic->irq > 0) {
282 ret = mt6397_irq_init(pmic);
Flora Fu6df8dd52015-02-22 13:15:29 +0100283 if (ret)
284 return ret;
285 }
286
John Crispin1d2c25e2016-01-27 12:47:37 +0100287fail_irq:
288 if (ret) {
289 irq_domain_remove(pmic->irq_domain);
Flora Fu6df8dd52015-02-22 13:15:29 +0100290 dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
John Crispin1d2c25e2016-01-27 12:47:37 +0100291 }
Flora Fu6df8dd52015-02-22 13:15:29 +0100292
293 return ret;
294}
295
296static int mt6397_remove(struct platform_device *pdev)
297{
298 mfd_remove_devices(&pdev->dev);
299
300 return 0;
301}
302
303static const struct of_device_id mt6397_of_match[] = {
304 { .compatible = "mediatek,mt6397" },
305 { }
306};
307MODULE_DEVICE_TABLE(of, mt6397_of_match);
308
309static struct platform_driver mt6397_driver = {
310 .probe = mt6397_probe,
311 .remove = mt6397_remove,
312 .driver = {
313 .name = "mt6397",
314 .of_match_table = of_match_ptr(mt6397_of_match),
Henry Chenf3151ab2015-08-10 21:10:45 +0800315 .pm = &mt6397_pm_ops,
Flora Fu6df8dd52015-02-22 13:15:29 +0100316 },
317};
318
319module_platform_driver(mt6397_driver);
320
321MODULE_AUTHOR("Flora Fu, MediaTek");
322MODULE_DESCRIPTION("Driver for MediaTek MT6397 PMIC");
323MODULE_LICENSE("GPL");
324MODULE_ALIAS("platform:mt6397");