blob: 74a14b24794ce827359765d178989b5252235866 [file] [log] [blame]
Fred Oh0cde3e92020-11-27 18:40:22 +02001// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2020 Intel Corporation. All rights reserved.
4//
5// Author: Fred Oh <fred.oh@linux.intel.com>
6//
7
8/*
9 * Hardware interface for audio DSP on IceLake.
10 */
11
12#include <linux/kernel.h>
13#include <linux/kconfig.h>
14#include <linux/export.h>
15#include <linux/bits.h>
16#include "../ops.h"
17#include "hda.h"
18#include "hda-ipc.h"
19#include "../sof-audio.h"
20
21static const struct snd_sof_debugfs_map icl_dsp_debugfs[] = {
22 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
23 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
24 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
25};
26
27/* Icelake ops */
28const struct snd_sof_dsp_ops sof_icl_ops = {
Libin Yang4939e492021-03-22 11:37:25 -050029 /* probe/remove/shutdown */
Fred Oh0cde3e92020-11-27 18:40:22 +020030 .probe = hda_dsp_probe,
31 .remove = hda_dsp_remove,
Libin Yang4939e492021-03-22 11:37:25 -050032 .shutdown = hda_dsp_shutdown,
Fred Oh0cde3e92020-11-27 18:40:22 +020033
34 /* Register IO */
35 .write = sof_io_write,
36 .read = sof_io_read,
37 .write64 = sof_io_write64,
38 .read64 = sof_io_read64,
39
40 /* Block IO */
41 .block_read = sof_block_read,
42 .block_write = sof_block_write,
43
44 /* doorbell */
45 .irq_thread = cnl_ipc_irq_thread,
46
47 /* ipc */
48 .send_msg = cnl_ipc_send_msg,
49 .fw_ready = sof_fw_ready,
50 .get_mailbox_offset = hda_dsp_ipc_get_mailbox_offset,
51 .get_window_offset = hda_dsp_ipc_get_window_offset,
52
53 .ipc_msg_data = hda_ipc_msg_data,
54 .ipc_pcm_params = hda_ipc_pcm_params,
55
56 /* machine driver */
57 .machine_select = hda_machine_select,
58 .machine_register = sof_machine_register,
59 .machine_unregister = sof_machine_unregister,
60 .set_mach_params = hda_set_mach_params,
61
62 /* debug */
63 .debug_map = icl_dsp_debugfs,
64 .debug_map_count = ARRAY_SIZE(icl_dsp_debugfs),
65 .dbg_dump = hda_dsp_dump,
66 .ipc_dump = cnl_ipc_dump,
67
68 /* stream callbacks */
69 .pcm_open = hda_dsp_pcm_open,
70 .pcm_close = hda_dsp_pcm_close,
71 .pcm_hw_params = hda_dsp_pcm_hw_params,
72 .pcm_hw_free = hda_dsp_stream_hw_free,
73 .pcm_trigger = hda_dsp_pcm_trigger,
74 .pcm_pointer = hda_dsp_pcm_pointer,
75
76#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_PROBES)
77 /* probe callbacks */
78 .probe_assign = hda_probe_compr_assign,
79 .probe_free = hda_probe_compr_free,
80 .probe_set_params = hda_probe_compr_set_params,
81 .probe_trigger = hda_probe_compr_trigger,
82 .probe_pointer = hda_probe_compr_pointer,
83#endif
84
85 /* firmware loading */
86 .load_firmware = snd_sof_load_firmware_raw,
87
88 /* pre/post fw run */
89 .pre_fw_run = hda_dsp_pre_fw_run,
90 .post_fw_run = hda_dsp_post_fw_run_icl,
91
92 /* parse platform specific extended manifest */
93 .parse_platform_ext_manifest = hda_dsp_ext_man_get_cavs_config_data,
94
95 /* dsp core power up/down */
96 .core_power_up = hda_dsp_enable_core,
97 .core_power_down = hda_dsp_core_reset_power_down,
98
99 /* firmware run */
100 .run = hda_dsp_cl_boot_firmware_iccmax,
101 .stall = hda_dsp_core_stall_icl,
102
103 /* trace callback */
104 .trace_init = hda_dsp_trace_init,
105 .trace_release = hda_dsp_trace_release,
106 .trace_trigger = hda_dsp_trace_trigger,
107
108 /* DAI drivers */
109 .drv = skl_dai,
110 .num_drv = SOF_SKL_NUM_DAIS,
111
112 /* PM */
113 .suspend = hda_dsp_suspend,
114 .resume = hda_dsp_resume,
115 .runtime_suspend = hda_dsp_runtime_suspend,
116 .runtime_resume = hda_dsp_runtime_resume,
117 .runtime_idle = hda_dsp_runtime_idle,
118 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
119 .set_power_state = hda_dsp_set_power_state,
120
121 /* ALSA HW info flags */
122 .hw_info = SNDRV_PCM_INFO_MMAP |
123 SNDRV_PCM_INFO_MMAP_VALID |
124 SNDRV_PCM_INFO_INTERLEAVED |
125 SNDRV_PCM_INFO_PAUSE |
126 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
127
128 .arch_ops = &sof_xtensa_arch_ops,
129};
130EXPORT_SYMBOL_NS(sof_icl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
131
132const struct sof_intel_dsp_desc icl_chip_info = {
133 /* Icelake */
134 .cores_num = 4,
135 .init_core_mask = 1,
136 .host_managed_cores_mask = GENMASK(3, 0),
137 .ipc_req = CNL_DSP_REG_HIPCIDR,
138 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
139 .ipc_ack = CNL_DSP_REG_HIPCIDA,
140 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
141 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
142 .rom_init_timeout = 300,
143 .ssp_count = ICL_SSP_COUNT,
144 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
Bard Liao1cbf6442021-07-23 19:54:47 +0800145 .sdw_shim_base = SDW_SHIM_BASE,
146 .sdw_alh_base = SDW_ALH_BASE,
Fred Oh0cde3e92020-11-27 18:40:22 +0200147};
148EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);