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Wolfram Sang95f25ef2010-10-15 12:21:04 +02001/*
2 * Freescale eSDHC i.MX controller driver for the platform bus.
3 *
4 * derived from the OF-version.
5 *
6 * Copyright (c) 2010 Pengutronix e.K.
Wolfram Sang035ff832015-04-20 15:51:42 +02007 * Author: Wolfram Sang <kernel@pengutronix.de>
Wolfram Sang95f25ef2010-10-15 12:21:04 +02008 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 */
13
14#include <linux/io.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/clk.h>
Wolfram Sang0c6d49c2011-02-26 14:44:39 +010018#include <linux/gpio.h>
Shawn Guo66506f72011-08-15 10:28:18 +080019#include <linux/module.h>
Richard Zhue1498602011-03-25 09:18:27 -040020#include <linux/slab.h>
Wolfram Sang95f25ef2010-10-15 12:21:04 +020021#include <linux/mmc/host.h>
Richard Zhu58ac8172011-03-21 13:22:16 +080022#include <linux/mmc/mmc.h>
23#include <linux/mmc/sdio.h>
Shawn Guofbe5fdd2012-12-11 22:32:20 +080024#include <linux/mmc/slot-gpio.h>
Shawn Guoabfafc22011-06-30 15:44:44 +080025#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/of_gpio.h>
Dong Aishenge62d8b82012-05-11 14:56:01 +080028#include <linux/pinctrl/consumer.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020029#include <linux/platform_data/mmc-esdhc-imx.h>
Dong Aisheng89d7e5c2013-11-04 16:38:29 +080030#include <linux/pm_runtime.h>
Wolfram Sang95f25ef2010-10-15 12:21:04 +020031#include "sdhci-pltfm.h"
32#include "sdhci-esdhc.h"
33
Haibo Chena2151862016-08-15 16:19:38 +080034#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f
Shawn Guo60bf6392013-01-15 23:36:53 +080035#define ESDHC_CTRL_D3CD 0x08
Haibo Chenfd449542015-08-11 19:38:30 +080036#define ESDHC_BURST_LEN_EN_INCR (1 << 27)
Richard Zhu58ac8172011-03-21 13:22:16 +080037/* VENDOR SPEC register */
Shawn Guo60bf6392013-01-15 23:36:53 +080038#define ESDHC_VENDOR_SPEC 0xc0
39#define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
Dong Aisheng03221912013-09-13 19:11:34 +080040#define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
Dong Aishengfed2f6e2013-09-13 19:11:33 +080041#define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
Shawn Guo60bf6392013-01-15 23:36:53 +080042#define ESDHC_WTMK_LVL 0x44
Dong Aishengcc17e122016-07-12 15:46:13 +080043#define ESDHC_WTMK_DEFAULT_VAL 0x10401040
Shawn Guo60bf6392013-01-15 23:36:53 +080044#define ESDHC_MIX_CTRL 0x48
Dong Aishengde5bdbf2013-10-18 19:48:46 +080045#define ESDHC_MIX_CTRL_DDREN (1 << 3)
Shawn Guo2a15f982013-01-21 19:02:26 +080046#define ESDHC_MIX_CTRL_AC23EN (1 << 7)
Dong Aisheng03221912013-09-13 19:11:34 +080047#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
48#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
Dong Aisheng0b330e32016-07-12 15:46:18 +080049#define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24)
Dong Aisheng03221912013-09-13 19:11:34 +080050#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
Haibo Chen28b07672015-08-11 19:38:26 +080051#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
Shawn Guo2a15f982013-01-21 19:02:26 +080052/* Bits 3 and 6 are not SDHCI standard definitions */
53#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
Dong Aishengd131a712013-11-04 16:38:26 +080054/* Tuning bits */
55#define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
Richard Zhu58ac8172011-03-21 13:22:16 +080056
Dong Aisheng602519b2013-10-18 19:48:47 +080057/* dll control register */
58#define ESDHC_DLL_CTRL 0x60
59#define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
60#define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
61
Dong Aisheng03221912013-09-13 19:11:34 +080062/* tune control register */
63#define ESDHC_TUNE_CTRL_STATUS 0x68
64#define ESDHC_TUNE_CTRL_STEP 1
65#define ESDHC_TUNE_CTRL_MIN 0
66#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
67
Haibo Chen28b07672015-08-11 19:38:26 +080068/* strobe dll register */
69#define ESDHC_STROBE_DLL_CTRL 0x70
70#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
71#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
72#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
73
74#define ESDHC_STROBE_DLL_STATUS 0x74
75#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
76#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
77
Dong Aisheng6e9fd282013-10-18 19:48:43 +080078#define ESDHC_TUNING_CTRL 0xcc
79#define ESDHC_STD_TUNING_EN (1 << 24)
80/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
Dong Aishengd87fc962016-07-12 15:46:15 +080081#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
82#define ESDHC_TUNING_START_TAP_MASK 0xff
Haibo Chen260ecb32015-11-10 17:43:30 +080083#define ESDHC_TUNING_STEP_MASK 0x00070000
Haibo Chend407e30ba2015-08-11 19:38:27 +080084#define ESDHC_TUNING_STEP_SHIFT 16
Dong Aisheng6e9fd282013-10-18 19:48:43 +080085
Dong Aishengad932202013-09-13 19:11:35 +080086/* pinctrl state */
87#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
88#define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
89
Richard Zhu58ac8172011-03-21 13:22:16 +080090/*
Sascha Haueraf510792013-01-21 19:02:28 +080091 * Our interpretation of the SDHCI_HOST_CONTROL register
92 */
93#define ESDHC_CTRL_4BITBUS (0x1 << 1)
94#define ESDHC_CTRL_8BITBUS (0x2 << 1)
95#define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
96
97/*
Richard Zhu97e4ba62011-08-11 16:51:46 -040098 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
99 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
100 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
101 * Define this macro DMA error INT for fsl eSDHC
102 */
Shawn Guo60bf6392013-01-15 23:36:53 +0800103#define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
Richard Zhu97e4ba62011-08-11 16:51:46 -0400104
105/*
Richard Zhu58ac8172011-03-21 13:22:16 +0800106 * The CMDTYPE of the CMD register (offset 0xE) should be set to
107 * "11" when the STOP CMD12 is issued on imx53 to abort one
108 * open ended multi-blk IO. Otherwise the TC INT wouldn't
109 * be generated.
110 * In exact block transfer, the controller doesn't complete the
111 * operations automatically as required at the end of the
112 * transfer and remains on hold if the abort command is not sent.
113 * As a result, the TC flag is not asserted and SW received timeout
114 * exeception. Bit1 of Vendor Spec registor is used to fix it.
115 */
Shawn Guo31fbb302013-10-17 15:19:44 +0800116#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
117/*
118 * The flag enables the workaround for ESDHC errata ENGcm07207 which
119 * affects i.MX25 and i.MX35.
120 */
121#define ESDHC_FLAG_ENGCM07207 BIT(2)
Shawn Guo9d61c002013-10-17 15:19:45 +0800122/*
123 * The flag tells that the ESDHC controller is an USDHC block that is
124 * integrated on the i.MX6 series.
125 */
126#define ESDHC_FLAG_USDHC BIT(3)
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800127/* The IP supports manual tuning process */
128#define ESDHC_FLAG_MAN_TUNING BIT(4)
129/* The IP supports standard tuning process */
130#define ESDHC_FLAG_STD_TUNING BIT(5)
131/* The IP has SDHCI_CAPABILITIES_1 register */
132#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
Dong Aisheng18094432015-05-27 18:13:28 +0800133/*
134 * The IP has errata ERR004536
135 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
136 * when reading data from the card
137 */
138#define ESDHC_FLAG_ERR004536 BIT(7)
Dong Aisheng4245aff2015-05-27 18:13:31 +0800139/* The IP supports HS200 mode */
140#define ESDHC_FLAG_HS200 BIT(8)
Haibo Chen28b07672015-08-11 19:38:26 +0800141/* The IP supports HS400 mode */
142#define ESDHC_FLAG_HS400 BIT(9)
143
144/* A higher clock ferquency than this rate requires strobell dll control */
145#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
Richard Zhue1498602011-03-25 09:18:27 -0400146
Shawn Guof47c4bb2013-10-17 15:19:47 +0800147struct esdhc_soc_data {
148 u32 flags;
149};
150
151static struct esdhc_soc_data esdhc_imx25_data = {
152 .flags = ESDHC_FLAG_ENGCM07207,
153};
154
155static struct esdhc_soc_data esdhc_imx35_data = {
156 .flags = ESDHC_FLAG_ENGCM07207,
157};
158
159static struct esdhc_soc_data esdhc_imx51_data = {
160 .flags = 0,
161};
162
163static struct esdhc_soc_data esdhc_imx53_data = {
164 .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
165};
166
167static struct esdhc_soc_data usdhc_imx6q_data = {
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800168 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
169};
170
171static struct esdhc_soc_data usdhc_imx6sl_data = {
172 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
Dong Aisheng4245aff2015-05-27 18:13:31 +0800173 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536
174 | ESDHC_FLAG_HS200,
Shawn Guo57ed3312011-06-30 09:24:26 +0800175};
176
Dong Aisheng913d4952015-05-27 18:13:30 +0800177static struct esdhc_soc_data usdhc_imx6sx_data = {
178 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
Dong Aisheng4245aff2015-05-27 18:13:31 +0800179 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
Dong Aisheng913d4952015-05-27 18:13:30 +0800180};
181
Haibo Chen28b07672015-08-11 19:38:26 +0800182static struct esdhc_soc_data usdhc_imx7d_data = {
183 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
184 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
185 | ESDHC_FLAG_HS400,
186};
187
Richard Zhue1498602011-03-25 09:18:27 -0400188struct pltfm_imx_data {
Richard Zhue1498602011-03-25 09:18:27 -0400189 u32 scratchpad;
Dong Aishenge62d8b82012-05-11 14:56:01 +0800190 struct pinctrl *pinctrl;
Dong Aishengad932202013-09-13 19:11:35 +0800191 struct pinctrl_state *pins_default;
192 struct pinctrl_state *pins_100mhz;
193 struct pinctrl_state *pins_200mhz;
Shawn Guof47c4bb2013-10-17 15:19:47 +0800194 const struct esdhc_soc_data *socdata;
Shawn Guo842afc02011-07-06 22:57:48 +0800195 struct esdhc_platform_data boarddata;
Sascha Hauer52dac612012-03-07 09:31:34 +0100196 struct clk *clk_ipg;
197 struct clk *clk_ahb;
198 struct clk *clk_per;
Lucas Stach361b8482013-03-15 09:49:26 +0100199 enum {
200 NO_CMD_PENDING, /* no multiblock command pending*/
201 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
202 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
203 } multiblock_status;
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800204 u32 is_ddr;
Richard Zhue1498602011-03-25 09:18:27 -0400205};
206
Krzysztof Kozlowskif8cbf462015-05-02 00:49:21 +0900207static const struct platform_device_id imx_esdhc_devtype[] = {
Shawn Guo57ed3312011-06-30 09:24:26 +0800208 {
209 .name = "sdhci-esdhc-imx25",
Shawn Guof47c4bb2013-10-17 15:19:47 +0800210 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
Shawn Guo57ed3312011-06-30 09:24:26 +0800211 }, {
212 .name = "sdhci-esdhc-imx35",
Shawn Guof47c4bb2013-10-17 15:19:47 +0800213 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
Shawn Guo57ed3312011-06-30 09:24:26 +0800214 }, {
215 .name = "sdhci-esdhc-imx51",
Shawn Guof47c4bb2013-10-17 15:19:47 +0800216 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
Shawn Guo57ed3312011-06-30 09:24:26 +0800217 }, {
Shawn Guo57ed3312011-06-30 09:24:26 +0800218 /* sentinel */
219 }
220};
221MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
222
Shawn Guoabfafc22011-06-30 15:44:44 +0800223static const struct of_device_id imx_esdhc_dt_ids[] = {
Shawn Guof47c4bb2013-10-17 15:19:47 +0800224 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
225 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
226 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
227 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
Dong Aisheng913d4952015-05-27 18:13:30 +0800228 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800229 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
Shawn Guof47c4bb2013-10-17 15:19:47 +0800230 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
Haibo Chen28b07672015-08-11 19:38:26 +0800231 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
Shawn Guoabfafc22011-06-30 15:44:44 +0800232 { /* sentinel */ }
233};
234MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
235
Shawn Guo57ed3312011-06-30 09:24:26 +0800236static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
237{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800238 return data->socdata == &esdhc_imx25_data;
Shawn Guo57ed3312011-06-30 09:24:26 +0800239}
240
241static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
242{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800243 return data->socdata == &esdhc_imx53_data;
Shawn Guo57ed3312011-06-30 09:24:26 +0800244}
245
Shawn Guo95a24822011-09-19 17:32:21 +0800246static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
247{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800248 return data->socdata == &usdhc_imx6q_data;
Shawn Guo95a24822011-09-19 17:32:21 +0800249}
250
Shawn Guo9d61c002013-10-17 15:19:45 +0800251static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
252{
Shawn Guof47c4bb2013-10-17 15:19:47 +0800253 return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
Shawn Guo9d61c002013-10-17 15:19:45 +0800254}
255
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200256static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
257{
258 void __iomem *base = host->ioaddr + (reg & ~0x3);
259 u32 shift = (reg & 0x3) * 8;
260
261 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
262}
263
Wolfram Sang7e29c302011-02-26 14:44:41 +0100264static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
265{
Lucas Stach361b8482013-03-15 09:49:26 +0100266 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800267 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Wolfram Sang7e29c302011-02-26 14:44:41 +0100268 u32 val = readl(host->ioaddr + reg);
269
Dong Aisheng03221912013-09-13 19:11:34 +0800270 if (unlikely(reg == SDHCI_PRESENT_STATE)) {
271 u32 fsl_prss = val;
272 /* save the least 20 bits */
273 val = fsl_prss & 0x000FFFFF;
274 /* move dat[0-3] bits */
275 val |= (fsl_prss & 0x0F000000) >> 4;
276 /* move cmd line bit */
277 val |= (fsl_prss & 0x00800000) << 1;
278 }
279
Richard Zhu97e4ba62011-08-11 16:51:46 -0400280 if (unlikely(reg == SDHCI_CAPABILITIES)) {
Dong Aisheng6b4fb6712a2013-10-18 19:48:44 +0800281 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
282 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
283 val &= 0xffff0000;
284
Richard Zhu97e4ba62011-08-11 16:51:46 -0400285 /* In FSL esdhc IC module, only bit20 is used to indicate the
286 * ADMA2 capability of esdhc, but this bit is messed up on
287 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
288 * don't actually support ADMA2). So set the BROKEN_ADMA
289 * uirk on MX25/35 platforms.
290 */
291
292 if (val & SDHCI_CAN_DO_ADMA1) {
293 val &= ~SDHCI_CAN_DO_ADMA1;
294 val |= SDHCI_CAN_DO_ADMA2;
295 }
296 }
297
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800298 if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
299 if (esdhc_is_usdhc(imx_data)) {
300 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
301 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
302 else
303 /* imx6q/dl does not have cap_1 register, fake one */
304 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
Dong Aisheng888824b2013-10-18 19:48:48 +0800305 | SDHCI_SUPPORT_SDR50
Dong Aishengda0295f2016-07-12 15:46:19 +0800306 | SDHCI_USE_SDR50_TUNING
307 | (SDHCI_TUNING_MODE_3 << SDHCI_RETUNING_MODE_SHIFT);
Haibo Chen28b07672015-08-11 19:38:26 +0800308
309 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
310 val |= SDHCI_SUPPORT_HS400;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800311 }
312 }
Dong Aisheng03221912013-09-13 19:11:34 +0800313
Shawn Guo9d61c002013-10-17 15:19:45 +0800314 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
Dong Aisheng03221912013-09-13 19:11:34 +0800315 val = 0;
316 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
317 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
318 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
319 }
320
Richard Zhu97e4ba62011-08-11 16:51:46 -0400321 if (unlikely(reg == SDHCI_INT_STATUS)) {
Shawn Guo60bf6392013-01-15 23:36:53 +0800322 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
323 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
Richard Zhu97e4ba62011-08-11 16:51:46 -0400324 val |= SDHCI_INT_ADMA_ERROR;
325 }
Lucas Stach361b8482013-03-15 09:49:26 +0100326
327 /*
328 * mask off the interrupt we get in response to the manually
329 * sent CMD12
330 */
331 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
332 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
333 val &= ~SDHCI_INT_RESPONSE;
334 writel(SDHCI_INT_RESPONSE, host->ioaddr +
335 SDHCI_INT_STATUS);
336 imx_data->multiblock_status = NO_CMD_PENDING;
337 }
Richard Zhu97e4ba62011-08-11 16:51:46 -0400338 }
339
Wolfram Sang7e29c302011-02-26 14:44:41 +0100340 return val;
341}
342
343static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
344{
Richard Zhue1498602011-03-25 09:18:27 -0400345 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800346 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Tony Lin0d588642011-08-11 16:45:59 -0400347 u32 data;
Richard Zhue1498602011-03-25 09:18:27 -0400348
Aaron Brice77da3da2016-10-10 11:39:52 -0700349 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
350 reg == SDHCI_INT_STATUS)) {
Dong Aishengb7321042015-05-27 18:13:27 +0800351 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) {
Tony Lin0d588642011-08-11 16:45:59 -0400352 /*
353 * Clear and then set D3CD bit to avoid missing the
354 * card interrupt. This is a eSDHC controller problem
355 * so we need to apply the following workaround: clear
356 * and set D3CD bit will make eSDHC re-sample the card
357 * interrupt. In case a card interrupt was lost,
358 * re-sample it by the following steps.
359 */
360 data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
Shawn Guo60bf6392013-01-15 23:36:53 +0800361 data &= ~ESDHC_CTRL_D3CD;
Tony Lin0d588642011-08-11 16:45:59 -0400362 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
Shawn Guo60bf6392013-01-15 23:36:53 +0800363 data |= ESDHC_CTRL_D3CD;
Tony Lin0d588642011-08-11 16:45:59 -0400364 writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
365 }
Dong Aisheng915be4852015-05-27 18:13:26 +0800366
367 if (val & SDHCI_INT_ADMA_ERROR) {
368 val &= ~SDHCI_INT_ADMA_ERROR;
369 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
370 }
Tony Lin0d588642011-08-11 16:45:59 -0400371 }
Wolfram Sang7e29c302011-02-26 14:44:41 +0100372
Shawn Guof47c4bb2013-10-17 15:19:47 +0800373 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
Richard Zhu58ac8172011-03-21 13:22:16 +0800374 && (reg == SDHCI_INT_STATUS)
375 && (val & SDHCI_INT_DATA_END))) {
376 u32 v;
Shawn Guo60bf6392013-01-15 23:36:53 +0800377 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
378 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
379 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
Lucas Stach361b8482013-03-15 09:49:26 +0100380
381 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
382 {
383 /* send a manual CMD12 with RESPTYP=none */
384 data = MMC_STOP_TRANSMISSION << 24 |
385 SDHCI_CMD_ABORTCMD << 16;
386 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
387 imx_data->multiblock_status = WAIT_FOR_INT;
388 }
Richard Zhu58ac8172011-03-21 13:22:16 +0800389 }
390
Wolfram Sang7e29c302011-02-26 14:44:41 +0100391 writel(val, host->ioaddr + reg);
392}
393
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200394static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
395{
Shawn Guoef4d0882013-01-15 23:30:27 +0800396 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800397 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aisheng03221912013-09-13 19:11:34 +0800398 u16 ret = 0;
399 u32 val;
Shawn Guoef4d0882013-01-15 23:30:27 +0800400
Shawn Guo95a24822011-09-19 17:32:21 +0800401 if (unlikely(reg == SDHCI_HOST_VERSION)) {
Shawn Guoef4d0882013-01-15 23:30:27 +0800402 reg ^= 2;
Shawn Guo9d61c002013-10-17 15:19:45 +0800403 if (esdhc_is_usdhc(imx_data)) {
Shawn Guoef4d0882013-01-15 23:30:27 +0800404 /*
405 * The usdhc register returns a wrong host version.
406 * Correct it here.
407 */
408 return SDHCI_SPEC_300;
409 }
Shawn Guo95a24822011-09-19 17:32:21 +0800410 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200411
Dong Aisheng03221912013-09-13 19:11:34 +0800412 if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
413 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
414 if (val & ESDHC_VENDOR_SPEC_VSELECT)
415 ret |= SDHCI_CTRL_VDD_180;
416
Shawn Guo9d61c002013-10-17 15:19:45 +0800417 if (esdhc_is_usdhc(imx_data)) {
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800418 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
419 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
420 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
421 /* the std tuning bits is in ACMD12_ERR for imx6sl */
422 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
Dong Aisheng03221912013-09-13 19:11:34 +0800423 }
424
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800425 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
426 ret |= SDHCI_CTRL_EXEC_TUNING;
427 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
428 ret |= SDHCI_CTRL_TUNED_CLK;
429
Dong Aisheng03221912013-09-13 19:11:34 +0800430 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
431
432 return ret;
433 }
434
Dong Aisheng7dd109e2013-10-30 22:09:49 +0800435 if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
436 if (esdhc_is_usdhc(imx_data)) {
437 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
438 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
439 /* Swap AC23 bit */
440 if (m & ESDHC_MIX_CTRL_AC23EN) {
441 ret &= ~ESDHC_MIX_CTRL_AC23EN;
442 ret |= SDHCI_TRNS_AUTO_CMD23;
443 }
444 } else {
445 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
446 }
447
448 return ret;
449 }
450
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200451 return readw(host->ioaddr + reg);
452}
453
454static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
455{
456 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800457 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aisheng03221912013-09-13 19:11:34 +0800458 u32 new_val = 0;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200459
460 switch (reg) {
Dong Aisheng03221912013-09-13 19:11:34 +0800461 case SDHCI_CLOCK_CONTROL:
462 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
463 if (val & SDHCI_CLOCK_CARD_EN)
464 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
465 else
466 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
Dan Carpentereeed7022015-02-26 23:37:55 +0300467 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
Dong Aisheng03221912013-09-13 19:11:34 +0800468 return;
469 case SDHCI_HOST_CONTROL2:
470 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
471 if (val & SDHCI_CTRL_VDD_180)
472 new_val |= ESDHC_VENDOR_SPEC_VSELECT;
473 else
474 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
475 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800476 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
477 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
Dong Aishengda0295f2016-07-12 15:46:19 +0800478 if (val & SDHCI_CTRL_TUNED_CLK) {
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800479 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
Dong Aishengda0295f2016-07-12 15:46:19 +0800480 new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
481 } else {
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800482 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
Dong Aishengda0295f2016-07-12 15:46:19 +0800483 new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
484 }
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800485 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
486 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
487 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
488 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +0800489 if (val & SDHCI_CTRL_TUNED_CLK) {
490 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800491 } else {
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +0800492 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800493 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
Dong Aisheng0b330e32016-07-12 15:46:18 +0800494 m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800495 }
496
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +0800497 if (val & SDHCI_CTRL_EXEC_TUNING) {
498 v |= ESDHC_MIX_CTRL_EXE_TUNE;
499 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
Dong Aisheng0b330e32016-07-12 15:46:18 +0800500 m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +0800501 } else {
502 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
503 }
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800504
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800505 writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
506 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
507 }
Dong Aisheng03221912013-09-13 19:11:34 +0800508 return;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200509 case SDHCI_TRANSFER_MODE:
Shawn Guof47c4bb2013-10-17 15:19:47 +0800510 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
Richard Zhu58ac8172011-03-21 13:22:16 +0800511 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
512 && (host->cmd->data->blocks > 1)
513 && (host->cmd->data->flags & MMC_DATA_READ)) {
514 u32 v;
Shawn Guo60bf6392013-01-15 23:36:53 +0800515 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
516 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
517 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
Richard Zhu58ac8172011-03-21 13:22:16 +0800518 }
Shawn Guo69f54692013-01-21 19:02:24 +0800519
Shawn Guo9d61c002013-10-17 15:19:45 +0800520 if (esdhc_is_usdhc(imx_data)) {
Shawn Guo69f54692013-01-21 19:02:24 +0800521 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
Shawn Guo2a15f982013-01-21 19:02:26 +0800522 /* Swap AC23 bit */
523 if (val & SDHCI_TRNS_AUTO_CMD23) {
524 val &= ~SDHCI_TRNS_AUTO_CMD23;
525 val |= ESDHC_MIX_CTRL_AC23EN;
526 }
527 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
Shawn Guo69f54692013-01-21 19:02:24 +0800528 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
529 } else {
530 /*
531 * Postpone this write, we must do it together with a
532 * command write that is down below.
533 */
534 imx_data->scratchpad = val;
535 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200536 return;
537 case SDHCI_COMMAND:
Lucas Stach361b8482013-03-15 09:49:26 +0100538 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
Richard Zhu58ac8172011-03-21 13:22:16 +0800539 val |= SDHCI_CMD_ABORTCMD;
Shawn Guo95a24822011-09-19 17:32:21 +0800540
Lucas Stach361b8482013-03-15 09:49:26 +0100541 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
Shawn Guof47c4bb2013-10-17 15:19:47 +0800542 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
Lucas Stach361b8482013-03-15 09:49:26 +0100543 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
544
Shawn Guo9d61c002013-10-17 15:19:45 +0800545 if (esdhc_is_usdhc(imx_data))
Shawn Guo95a24822011-09-19 17:32:21 +0800546 writel(val << 16,
547 host->ioaddr + SDHCI_TRANSFER_MODE);
Shawn Guo69f54692013-01-21 19:02:24 +0800548 else
Shawn Guo95a24822011-09-19 17:32:21 +0800549 writel(val << 16 | imx_data->scratchpad,
550 host->ioaddr + SDHCI_TRANSFER_MODE);
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200551 return;
552 case SDHCI_BLOCK_SIZE:
553 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
554 break;
555 }
556 esdhc_clrset_le(host, 0xffff, val, reg);
557}
558
Aaron Brice77da3da2016-10-10 11:39:52 -0700559static u8 esdhc_readb_le(struct sdhci_host *host, int reg)
560{
561 u8 ret;
562 u32 val;
563
564 switch (reg) {
565 case SDHCI_HOST_CONTROL:
566 val = readl(host->ioaddr + reg);
567
568 ret = val & SDHCI_CTRL_LED;
569 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK;
570 ret |= (val & ESDHC_CTRL_4BITBUS);
571 ret |= (val & ESDHC_CTRL_8BITBUS) << 3;
572 return ret;
573 }
574
575 return readb(host->ioaddr + reg);
576}
577
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200578static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
579{
Wilson Callan9a0985b2012-07-19 02:49:16 -0400580 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800581 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200582 u32 new_val;
Sascha Haueraf510792013-01-21 19:02:28 +0800583 u32 mask;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200584
585 switch (reg) {
586 case SDHCI_POWER_CONTROL:
587 /*
588 * FSL put some DMA bits here
589 * If your board has a regulator, code should be here
590 */
591 return;
592 case SDHCI_HOST_CONTROL:
Shawn Guo6b40d182013-01-15 23:36:52 +0800593 /* FSL messed up here, so we need to manually compose it. */
Sascha Haueraf510792013-01-21 19:02:28 +0800594 new_val = val & SDHCI_CTRL_LED;
Masanari Iida7122bbb2012-08-05 23:25:40 +0900595 /* ensure the endianness */
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200596 new_val |= ESDHC_HOST_CONTROL_LE;
Wilson Callan9a0985b2012-07-19 02:49:16 -0400597 /* bits 8&9 are reserved on mx25 */
598 if (!is_imx25_esdhc(imx_data)) {
599 /* DMA mode bits are shifted */
600 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
601 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200602
Sascha Haueraf510792013-01-21 19:02:28 +0800603 /*
604 * Do not touch buswidth bits here. This is done in
605 * esdhc_pltfm_bus_width.
Martin Fuzzeyf6825742013-04-15 17:08:35 +0200606 * Do not touch the D3CD bit either which is used for the
607 * SDIO interrupt errata workaround.
Sascha Haueraf510792013-01-21 19:02:28 +0800608 */
Martin Fuzzeyf6825742013-04-15 17:08:35 +0200609 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
Sascha Haueraf510792013-01-21 19:02:28 +0800610
611 esdhc_clrset_le(host, mask, new_val, reg);
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200612 return;
613 }
614 esdhc_clrset_le(host, 0xff, val, reg);
Shawn Guo913413c2011-06-21 22:41:51 +0800615
616 /*
617 * The esdhc has a design violation to SDHC spec which tells
618 * that software reset should not affect card detection circuit.
619 * But esdhc clears its SYSCTL register bits [0..2] during the
620 * software reset. This will stop those clocks that card detection
621 * circuit relies on. To work around it, we turn the clocks on back
622 * to keep card detection circuit functional.
623 */
Shawn Guo58c8c4f2013-01-21 19:02:25 +0800624 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
Shawn Guo913413c2011-06-21 22:41:51 +0800625 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
Shawn Guo58c8c4f2013-01-21 19:02:25 +0800626 /*
627 * The reset on usdhc fails to clear MIX_CTRL register.
628 * Do it manually here.
629 */
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800630 if (esdhc_is_usdhc(imx_data)) {
Dong Aishengd131a712013-11-04 16:38:26 +0800631 /* the tuning bits should be kept during reset */
632 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
633 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
634 host->ioaddr + ESDHC_MIX_CTRL);
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800635 imx_data->is_ddr = 0;
636 }
Shawn Guo58c8c4f2013-01-21 19:02:25 +0800637 }
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200638}
639
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200640static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
641{
642 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200643
Dong Aishenga3bd4f92015-07-22 20:53:09 +0800644 return pltfm_host->clock;
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200645}
646
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200647static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
648{
649 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
650
Dong Aishenga9748622013-12-26 15:23:53 +0800651 return pltfm_host->clock / 256 / 16;
Wolfram Sang95f25ef2010-10-15 12:21:04 +0200652}
653
Lucas Stach8ba95802013-06-05 15:13:25 +0200654static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
655 unsigned int clock)
656{
657 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800658 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aishenga9748622013-12-26 15:23:53 +0800659 unsigned int host_clock = pltfm_host->clock;
Dong Aishengd31fc002013-09-13 19:11:32 +0800660 int pre_div = 2;
661 int div = 1;
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800662 u32 temp, val;
Lucas Stach8ba95802013-06-05 15:13:25 +0200663
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800664 if (clock == 0) {
Russell King1650d0c2014-04-25 12:58:50 +0100665 host->mmc->actual_clock = 0;
666
Shawn Guo9d61c002013-10-17 15:19:45 +0800667 if (esdhc_is_usdhc(imx_data)) {
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800668 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
669 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
670 host->ioaddr + ESDHC_VENDOR_SPEC);
671 }
Russell King373073e2014-04-25 12:58:45 +0100672 return;
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800673 }
Dong Aishengd31fc002013-09-13 19:11:32 +0800674
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800675 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
Dong Aisheng5f7886c2013-09-13 19:11:36 +0800676 pre_div = 1;
677
Dong Aishengd31fc002013-09-13 19:11:32 +0800678 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
679 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
680 | ESDHC_CLOCK_MASK);
681 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
682
683 while (host_clock / pre_div / 16 > clock && pre_div < 256)
684 pre_div *= 2;
685
686 while (host_clock / pre_div / div > clock && div < 16)
687 div++;
688
Dong Aishenge76b8552013-09-13 19:11:37 +0800689 host->mmc->actual_clock = host_clock / pre_div / div;
Dong Aishengd31fc002013-09-13 19:11:32 +0800690 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
Dong Aishenge76b8552013-09-13 19:11:37 +0800691 clock, host->mmc->actual_clock);
Dong Aishengd31fc002013-09-13 19:11:32 +0800692
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800693 if (imx_data->is_ddr)
694 pre_div >>= 2;
695 else
696 pre_div >>= 1;
Dong Aishengd31fc002013-09-13 19:11:32 +0800697 div--;
698
699 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
700 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
701 | (div << ESDHC_DIVIDER_SHIFT)
702 | (pre_div << ESDHC_PREDIV_SHIFT));
703 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800704
Shawn Guo9d61c002013-10-17 15:19:45 +0800705 if (esdhc_is_usdhc(imx_data)) {
Dong Aishengfed2f6e2013-09-13 19:11:33 +0800706 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
707 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
708 host->ioaddr + ESDHC_VENDOR_SPEC);
709 }
710
Dong Aishengd31fc002013-09-13 19:11:32 +0800711 mdelay(1);
Lucas Stach8ba95802013-06-05 15:13:25 +0200712}
713
Shawn Guo913413c2011-06-21 22:41:51 +0800714static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
715{
Shawn Guo842afc02011-07-06 22:57:48 +0800716 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800717 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Shawn Guo842afc02011-07-06 22:57:48 +0800718 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
Shawn Guo913413c2011-06-21 22:41:51 +0800719
720 switch (boarddata->wp_type) {
721 case ESDHC_WP_GPIO:
Shawn Guofbe5fdd2012-12-11 22:32:20 +0800722 return mmc_gpio_get_ro(host->mmc);
Shawn Guo913413c2011-06-21 22:41:51 +0800723 case ESDHC_WP_CONTROLLER:
724 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
725 SDHCI_WRITE_PROTECT);
726 case ESDHC_WP_NONE:
727 break;
728 }
729
730 return -ENOSYS;
731}
732
Russell King2317f562014-04-25 12:57:07 +0100733static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width)
Sascha Haueraf510792013-01-21 19:02:28 +0800734{
735 u32 ctrl;
736
737 switch (width) {
738 case MMC_BUS_WIDTH_8:
739 ctrl = ESDHC_CTRL_8BITBUS;
740 break;
741 case MMC_BUS_WIDTH_4:
742 ctrl = ESDHC_CTRL_4BITBUS;
743 break;
744 default:
745 ctrl = 0;
746 break;
747 }
748
749 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
750 SDHCI_HOST_CONTROL);
Sascha Haueraf510792013-01-21 19:02:28 +0800751}
752
Dong Aisheng03221912013-09-13 19:11:34 +0800753static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
754{
755 u32 reg;
756
757 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
758 mdelay(1);
759
760 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
761 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
762 ESDHC_MIX_CTRL_FBCLK_SEL;
763 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
764 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
765 dev_dbg(mmc_dev(host->mmc),
766 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
767 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
768}
769
Dong Aisheng03221912013-09-13 19:11:34 +0800770static void esdhc_post_tuning(struct sdhci_host *host)
771{
772 u32 reg;
773
774 reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
775 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
Dong Aishengda0295f2016-07-12 15:46:19 +0800776 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
Dong Aisheng03221912013-09-13 19:11:34 +0800777 writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
778}
779
780static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
781{
782 int min, max, avg, ret;
783
784 /* find the mininum delay first which can pass tuning */
785 min = ESDHC_TUNE_CTRL_MIN;
786 while (min < ESDHC_TUNE_CTRL_MAX) {
787 esdhc_prepare_tuning(host, min);
Chaotian Jing9979dbe2015-10-27 14:24:28 +0800788 if (!mmc_send_tuning(host->mmc, opcode, NULL))
Dong Aisheng03221912013-09-13 19:11:34 +0800789 break;
790 min += ESDHC_TUNE_CTRL_STEP;
791 }
792
793 /* find the maxinum delay which can not pass tuning */
794 max = min + ESDHC_TUNE_CTRL_STEP;
795 while (max < ESDHC_TUNE_CTRL_MAX) {
796 esdhc_prepare_tuning(host, max);
Chaotian Jing9979dbe2015-10-27 14:24:28 +0800797 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
Dong Aisheng03221912013-09-13 19:11:34 +0800798 max -= ESDHC_TUNE_CTRL_STEP;
799 break;
800 }
801 max += ESDHC_TUNE_CTRL_STEP;
802 }
803
804 /* use average delay to get the best timing */
805 avg = (min + max) / 2;
806 esdhc_prepare_tuning(host, avg);
Chaotian Jing9979dbe2015-10-27 14:24:28 +0800807 ret = mmc_send_tuning(host->mmc, opcode, NULL);
Dong Aisheng03221912013-09-13 19:11:34 +0800808 esdhc_post_tuning(host);
809
810 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
811 ret ? "failed" : "passed", avg, ret);
812
813 return ret;
814}
815
Dong Aishengad932202013-09-13 19:11:35 +0800816static int esdhc_change_pinstate(struct sdhci_host *host,
817 unsigned int uhs)
818{
819 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800820 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aishengad932202013-09-13 19:11:35 +0800821 struct pinctrl_state *pinctrl;
822
823 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
824
825 if (IS_ERR(imx_data->pinctrl) ||
826 IS_ERR(imx_data->pins_default) ||
827 IS_ERR(imx_data->pins_100mhz) ||
828 IS_ERR(imx_data->pins_200mhz))
829 return -EINVAL;
830
831 switch (uhs) {
832 case MMC_TIMING_UHS_SDR50:
833 pinctrl = imx_data->pins_100mhz;
834 break;
835 case MMC_TIMING_UHS_SDR104:
Dong Aisheng429a5b42013-10-30 22:10:42 +0800836 case MMC_TIMING_MMC_HS200:
Haibo Chen28b07672015-08-11 19:38:26 +0800837 case MMC_TIMING_MMC_HS400:
Dong Aishengad932202013-09-13 19:11:35 +0800838 pinctrl = imx_data->pins_200mhz;
839 break;
840 default:
841 /* back to default state for other legacy timing */
842 pinctrl = imx_data->pins_default;
843 }
844
845 return pinctrl_select_state(imx_data->pinctrl, pinctrl);
846}
847
Haibo Chen28b07672015-08-11 19:38:26 +0800848/*
849 * For HS400 eMMC, there is a data_strobe line, this signal is generated
850 * by the device and used for data output and CRC status response output
851 * in HS400 mode. The frequency of this signal follows the frequency of
852 * CLK generated by host. Host receive the data which is aligned to the
853 * edge of data_strobe line. Due to the time delay between CLK line and
854 * data_strobe line, if the delay time is larger than one clock cycle,
855 * then CLK and data_strobe line will misaligned, read error shows up.
856 * So when the CLK is higher than 100MHz, each clock cycle is short enough,
857 * host should config the delay target.
858 */
859static void esdhc_set_strobe_dll(struct sdhci_host *host)
860{
861 u32 v;
862
863 if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
Dong Aisheng7ac6da22016-07-12 15:46:20 +0800864 /* disable clock before enabling strobe dll */
865 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) &
866 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
867 host->ioaddr + ESDHC_VENDOR_SPEC);
868
Haibo Chen28b07672015-08-11 19:38:26 +0800869 /* force a reset on strobe dll */
870 writel(ESDHC_STROBE_DLL_CTRL_RESET,
871 host->ioaddr + ESDHC_STROBE_DLL_CTRL);
872 /*
873 * enable strobe dll ctrl and adjust the delay target
874 * for the uSDHC loopback read clock
875 */
876 v = ESDHC_STROBE_DLL_CTRL_ENABLE |
877 (7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
878 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
879 /* wait 1us to make sure strobe dll status register stable */
880 udelay(1);
881 v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
882 if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
883 dev_warn(mmc_dev(host->mmc),
884 "warning! HS400 strobe DLL status REF not lock!\n");
885 if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
886 dev_warn(mmc_dev(host->mmc),
887 "warning! HS400 strobe DLL status SLV not lock!\n");
888 }
889}
890
Russell King850a29b2014-04-25 12:59:41 +0100891static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
Dong Aishengad932202013-09-13 19:11:35 +0800892{
Haibo Chen28b07672015-08-11 19:38:26 +0800893 u32 m;
Dong Aishengad932202013-09-13 19:11:35 +0800894 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800895 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aisheng602519b2013-10-18 19:48:47 +0800896 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
Dong Aishengad932202013-09-13 19:11:35 +0800897
Haibo Chen28b07672015-08-11 19:38:26 +0800898 /* disable ddr mode and disable HS400 mode */
899 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
900 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
901 imx_data->is_ddr = 0;
902
Russell King850a29b2014-04-25 12:59:41 +0100903 switch (timing) {
Dong Aishengad932202013-09-13 19:11:35 +0800904 case MMC_TIMING_UHS_SDR12:
Dong Aishengad932202013-09-13 19:11:35 +0800905 case MMC_TIMING_UHS_SDR25:
Dong Aishengad932202013-09-13 19:11:35 +0800906 case MMC_TIMING_UHS_SDR50:
Dong Aishengad932202013-09-13 19:11:35 +0800907 case MMC_TIMING_UHS_SDR104:
Dong Aisheng429a5b42013-10-30 22:10:42 +0800908 case MMC_TIMING_MMC_HS200:
Haibo Chen28b07672015-08-11 19:38:26 +0800909 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
Dong Aishengad932202013-09-13 19:11:35 +0800910 break;
911 case MMC_TIMING_UHS_DDR50:
Aisheng Dong69f5bf32014-05-09 14:53:15 +0800912 case MMC_TIMING_MMC_DDR52:
Haibo Chen28b07672015-08-11 19:38:26 +0800913 m |= ESDHC_MIX_CTRL_DDREN;
914 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
Dong Aishengde5bdbf2013-10-18 19:48:46 +0800915 imx_data->is_ddr = 1;
Dong Aisheng602519b2013-10-18 19:48:47 +0800916 if (boarddata->delay_line) {
917 u32 v;
918 v = boarddata->delay_line <<
919 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
920 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
921 if (is_imx53_esdhc(imx_data))
922 v <<= 1;
923 writel(v, host->ioaddr + ESDHC_DLL_CTRL);
924 }
Dong Aishengad932202013-09-13 19:11:35 +0800925 break;
Haibo Chen28b07672015-08-11 19:38:26 +0800926 case MMC_TIMING_MMC_HS400:
927 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
928 writel(m, host->ioaddr + ESDHC_MIX_CTRL);
929 imx_data->is_ddr = 1;
Dong Aisheng7ac6da22016-07-12 15:46:20 +0800930 /* update clock after enable DDR for strobe DLL lock */
931 host->ops->set_clock(host, host->clock);
Haibo Chen28b07672015-08-11 19:38:26 +0800932 esdhc_set_strobe_dll(host);
933 break;
Dong Aishengad932202013-09-13 19:11:35 +0800934 }
935
Russell King850a29b2014-04-25 12:59:41 +0100936 esdhc_change_pinstate(host, timing);
Dong Aishengad932202013-09-13 19:11:35 +0800937}
938
Russell King0718e592014-04-25 12:57:18 +0100939static void esdhc_reset(struct sdhci_host *host, u8 mask)
940{
941 sdhci_reset(host, mask);
942
943 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
944 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
945}
946
Aisheng Dong10fd0ad2014-08-27 15:26:28 +0800947static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host)
948{
949 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800950 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Aisheng Dong10fd0ad2014-08-27 15:26:28 +0800951
Haibo Chen2fb0b022016-08-15 16:31:33 +0800952 /* Doc Errata: the uSDHC actual maximum timeout count is 1 << 29 */
953 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27;
Aisheng Dong10fd0ad2014-08-27 15:26:28 +0800954}
955
Aisheng Donge33eb8e22014-08-27 15:26:30 +0800956static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
957{
958 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +0800959 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Aisheng Donge33eb8e22014-08-27 15:26:30 +0800960
961 /* use maximum timeout counter */
Haibo Chena2151862016-08-15 16:19:38 +0800962 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
963 esdhc_is_usdhc(imx_data) ? 0xF : 0xE,
Aisheng Donge33eb8e22014-08-27 15:26:30 +0800964 SDHCI_TIMEOUT_CONTROL);
965}
966
Dong Aisheng6e9fd282013-10-18 19:48:43 +0800967static struct sdhci_ops sdhci_esdhc_ops = {
Richard Zhue1498602011-03-25 09:18:27 -0400968 .read_l = esdhc_readl_le,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100969 .read_w = esdhc_readw_le,
Aaron Brice77da3da2016-10-10 11:39:52 -0700970 .read_b = esdhc_readb_le,
Richard Zhue1498602011-03-25 09:18:27 -0400971 .write_l = esdhc_writel_le,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100972 .write_w = esdhc_writew_le,
973 .write_b = esdhc_writeb_le,
Lucas Stach8ba95802013-06-05 15:13:25 +0200974 .set_clock = esdhc_pltfm_set_clock,
Lucas Stach0ddf03c2013-06-05 15:13:26 +0200975 .get_max_clock = esdhc_pltfm_get_max_clock,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100976 .get_min_clock = esdhc_pltfm_get_min_clock,
Aisheng Dong10fd0ad2014-08-27 15:26:28 +0800977 .get_max_timeout_count = esdhc_get_max_timeout_count,
Shawn Guo913413c2011-06-21 22:41:51 +0800978 .get_ro = esdhc_pltfm_get_ro,
Aisheng Donge33eb8e22014-08-27 15:26:30 +0800979 .set_timeout = esdhc_set_timeout,
Russell King2317f562014-04-25 12:57:07 +0100980 .set_bus_width = esdhc_pltfm_set_bus_width,
Dong Aishengad932202013-09-13 19:11:35 +0800981 .set_uhs_signaling = esdhc_set_uhs_signaling,
Russell King0718e592014-04-25 12:57:18 +0100982 .reset = esdhc_reset,
Wolfram Sang0c6d49c2011-02-26 14:44:39 +0100983};
984
Lars-Peter Clausen1db5eeb2013-03-13 19:26:03 +0100985static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
Richard Zhu97e4ba62011-08-11 16:51:46 -0400986 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
987 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
988 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
Shawn Guo85d65092011-05-27 23:48:12 +0800989 | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
Shawn Guo85d65092011-05-27 23:48:12 +0800990 .ops = &sdhci_esdhc_ops,
991};
992
Dong Aishengf3f5cf32016-07-12 15:46:21 +0800993static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host)
994{
995 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
996 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aisheng2b16cf32016-07-12 15:46:22 +0800997 int tmp;
Dong Aishengf3f5cf32016-07-12 15:46:21 +0800998
999 if (esdhc_is_usdhc(imx_data)) {
1000 /*
1001 * The imx6q ROM code will change the default watermark
1002 * level setting to something insane. Change it back here.
1003 */
1004 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
1005
1006 /*
1007 * ROM code will change the bit burst_length_enable setting
1008 * to zero if this usdhc is choosed to boot system. Change
1009 * it back here, otherwise it will impact the performance a
1010 * lot. This bit is used to enable/disable the burst length
1011 * for the external AHB2AXI bridge, it's usefully especially
1012 * for INCR transfer because without burst length indicator,
1013 * the AHB2AXI bridge does not know the burst length in
1014 * advance. And without burst length indicator, AHB INCR
1015 * transfer can only be converted to singles on the AXI side.
1016 */
1017 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
1018 | ESDHC_BURST_LEN_EN_INCR,
1019 host->ioaddr + SDHCI_HOST_CONTROL);
1020 /*
1021 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1022 * TO1.1, it's harmless for MX6SL
1023 */
1024 writel(readl(host->ioaddr + 0x6c) | BIT(7),
1025 host->ioaddr + 0x6c);
1026
1027 /* disable DLL_CTRL delay line settings */
1028 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL);
Dong Aisheng2b16cf32016-07-12 15:46:22 +08001029
1030 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
1031 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
1032 tmp |= ESDHC_STD_TUNING_EN |
1033 ESDHC_TUNING_START_TAP_DEFAULT;
1034 if (imx_data->boarddata.tuning_start_tap) {
1035 tmp &= ~ESDHC_TUNING_START_TAP_MASK;
1036 tmp |= imx_data->boarddata.tuning_start_tap;
1037 }
1038
1039 if (imx_data->boarddata.tuning_step) {
1040 tmp &= ~ESDHC_TUNING_STEP_MASK;
1041 tmp |= imx_data->boarddata.tuning_step
1042 << ESDHC_TUNING_STEP_SHIFT;
1043 }
1044 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
1045 }
Dong Aishengf3f5cf32016-07-12 15:46:21 +08001046 }
1047}
1048
Shawn Guoabfafc22011-06-30 15:44:44 +08001049#ifdef CONFIG_OF
Bill Pembertonc3be1ef2012-11-19 13:23:06 -05001050static int
Shawn Guoabfafc22011-06-30 15:44:44 +08001051sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
Sascha Hauer07bf2b52015-03-24 14:45:04 +01001052 struct sdhci_host *host,
Dong Aisheng91fa4252015-07-22 20:53:06 +08001053 struct pltfm_imx_data *imx_data)
Shawn Guoabfafc22011-06-30 15:44:44 +08001054{
1055 struct device_node *np = pdev->dev.of_node;
Dong Aisheng91fa4252015-07-22 20:53:06 +08001056 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
Dong Aisheng4800e872015-07-22 20:53:05 +08001057 int ret;
Shawn Guoabfafc22011-06-30 15:44:44 +08001058
Shawn Guoabfafc22011-06-30 15:44:44 +08001059 if (of_get_property(np, "fsl,wp-controller", NULL))
1060 boarddata->wp_type = ESDHC_WP_CONTROLLER;
1061
Shawn Guoabfafc22011-06-30 15:44:44 +08001062 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
1063 if (gpio_is_valid(boarddata->wp_gpio))
1064 boarddata->wp_type = ESDHC_WP_GPIO;
1065
Haibo Chend407e30ba2015-08-11 19:38:27 +08001066 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
Dong Aishengd87fc962016-07-12 15:46:15 +08001067 of_property_read_u32(np, "fsl,tuning-start-tap",
1068 &boarddata->tuning_start_tap);
Haibo Chend407e30ba2015-08-11 19:38:27 +08001069
Dong Aishengad932202013-09-13 19:11:35 +08001070 if (of_find_property(np, "no-1-8-v", NULL))
1071 boarddata->support_vsel = false;
1072 else
1073 boarddata->support_vsel = true;
1074
Dong Aisheng602519b2013-10-18 19:48:47 +08001075 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
1076 boarddata->delay_line = 0;
1077
Sascha Hauer07bf2b52015-03-24 14:45:04 +01001078 mmc_of_parse_voltage(np, &host->ocr_mask);
1079
Dong Aisheng91fa4252015-07-22 20:53:06 +08001080 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1081 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data) &&
1082 !IS_ERR(imx_data->pins_default)) {
1083 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1084 ESDHC_PINCTRL_STATE_100MHZ);
1085 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1086 ESDHC_PINCTRL_STATE_200MHZ);
1087 if (IS_ERR(imx_data->pins_100mhz) ||
1088 IS_ERR(imx_data->pins_200mhz)) {
1089 dev_warn(mmc_dev(host->mmc),
1090 "could not get ultra high speed state, work on normal mode\n");
1091 /*
1092 * fall back to not support uhs by specify no 1.8v quirk
1093 */
1094 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1095 }
1096 } else {
1097 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1098 }
1099
Fabio Estevam15064112015-05-09 09:57:08 -03001100 /* call to generic mmc_of_parse to support additional capabilities */
Dong Aisheng4800e872015-07-22 20:53:05 +08001101 ret = mmc_of_parse(host->mmc);
1102 if (ret)
1103 return ret;
1104
Arnd Bergmann287980e2016-05-27 23:23:25 +02001105 if (mmc_gpio_get_cd(host->mmc) >= 0)
Dong Aisheng4800e872015-07-22 20:53:05 +08001106 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1107
1108 return 0;
Shawn Guoabfafc22011-06-30 15:44:44 +08001109}
1110#else
1111static inline int
1112sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
Sascha Hauer07bf2b52015-03-24 14:45:04 +01001113 struct sdhci_host *host,
Dong Aisheng91fa4252015-07-22 20:53:06 +08001114 struct pltfm_imx_data *imx_data)
Shawn Guoabfafc22011-06-30 15:44:44 +08001115{
1116 return -ENODEV;
1117}
1118#endif
1119
Dong Aisheng91fa4252015-07-22 20:53:06 +08001120static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev,
1121 struct sdhci_host *host,
1122 struct pltfm_imx_data *imx_data)
1123{
1124 struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1125 int err;
1126
1127 if (!host->mmc->parent->platform_data) {
1128 dev_err(mmc_dev(host->mmc), "no board data!\n");
1129 return -EINVAL;
1130 }
1131
1132 imx_data->boarddata = *((struct esdhc_platform_data *)
1133 host->mmc->parent->platform_data);
1134 /* write_protect */
1135 if (boarddata->wp_type == ESDHC_WP_GPIO) {
1136 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1137 if (err) {
1138 dev_err(mmc_dev(host->mmc),
1139 "failed to request write-protect gpio!\n");
1140 return err;
1141 }
1142 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1143 }
1144
1145 /* card_detect */
1146 switch (boarddata->cd_type) {
1147 case ESDHC_CD_GPIO:
1148 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1149 if (err) {
1150 dev_err(mmc_dev(host->mmc),
1151 "failed to request card-detect gpio!\n");
1152 return err;
1153 }
1154 /* fall through */
1155
1156 case ESDHC_CD_CONTROLLER:
1157 /* we have a working card_detect back */
1158 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1159 break;
1160
1161 case ESDHC_CD_PERMANENT:
1162 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1163 break;
1164
1165 case ESDHC_CD_NONE:
1166 break;
1167 }
1168
1169 switch (boarddata->max_bus_width) {
1170 case 8:
1171 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1172 break;
1173 case 4:
1174 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1175 break;
1176 case 1:
1177 default:
1178 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1179 break;
1180 }
1181
1182 return 0;
1183}
1184
Bill Pembertonc3be1ef2012-11-19 13:23:06 -05001185static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001186{
Shawn Guoabfafc22011-06-30 15:44:44 +08001187 const struct of_device_id *of_id =
1188 of_match_device(imx_esdhc_dt_ids, &pdev->dev);
Shawn Guo85d65092011-05-27 23:48:12 +08001189 struct sdhci_pltfm_host *pltfm_host;
1190 struct sdhci_host *host;
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001191 int err;
Richard Zhue1498602011-03-25 09:18:27 -04001192 struct pltfm_imx_data *imx_data;
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001193
Jisheng Zhang070e6d32016-02-16 21:08:20 +08001194 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata,
1195 sizeof(*imx_data));
Shawn Guo85d65092011-05-27 23:48:12 +08001196 if (IS_ERR(host))
1197 return PTR_ERR(host);
1198
1199 pltfm_host = sdhci_priv(host);
1200
Jisheng Zhang070e6d32016-02-16 21:08:20 +08001201 imx_data = sdhci_pltfm_priv(pltfm_host);
Shawn Guo57ed3312011-06-30 09:24:26 +08001202
Shawn Guof47c4bb2013-10-17 15:19:47 +08001203 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
1204 pdev->id_entry->driver_data;
Shawn Guo85d65092011-05-27 23:48:12 +08001205
Sascha Hauer52dac612012-03-07 09:31:34 +01001206 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1207 if (IS_ERR(imx_data->clk_ipg)) {
1208 err = PTR_ERR(imx_data->clk_ipg);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001209 goto free_sdhci;
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001210 }
Sascha Hauer52dac612012-03-07 09:31:34 +01001211
1212 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1213 if (IS_ERR(imx_data->clk_ahb)) {
1214 err = PTR_ERR(imx_data->clk_ahb);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001215 goto free_sdhci;
Sascha Hauer52dac612012-03-07 09:31:34 +01001216 }
1217
1218 imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
1219 if (IS_ERR(imx_data->clk_per)) {
1220 err = PTR_ERR(imx_data->clk_per);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001221 goto free_sdhci;
Sascha Hauer52dac612012-03-07 09:31:34 +01001222 }
1223
1224 pltfm_host->clk = imx_data->clk_per;
Dong Aishenga9748622013-12-26 15:23:53 +08001225 pltfm_host->clock = clk_get_rate(pltfm_host->clk);
Sascha Hauer52dac612012-03-07 09:31:34 +01001226 clk_prepare_enable(imx_data->clk_per);
1227 clk_prepare_enable(imx_data->clk_ipg);
1228 clk_prepare_enable(imx_data->clk_ahb);
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001229
Dong Aishengad932202013-09-13 19:11:35 +08001230 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
Dong Aishenge62d8b82012-05-11 14:56:01 +08001231 if (IS_ERR(imx_data->pinctrl)) {
1232 err = PTR_ERR(imx_data->pinctrl);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001233 goto disable_clk;
Dong Aishenge62d8b82012-05-11 14:56:01 +08001234 }
1235
Dong Aishengad932202013-09-13 19:11:35 +08001236 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1237 PINCTRL_STATE_DEFAULT);
Dirk Behmecd529af2014-10-01 04:25:32 -05001238 if (IS_ERR(imx_data->pins_default))
1239 dev_warn(mmc_dev(host->mmc), "could not get default state\n");
Dong Aishengad932202013-09-13 19:11:35 +08001240
Shawn Guof47c4bb2013-10-17 15:19:47 +08001241 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001242 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
Richard Zhu97e4ba62011-08-11 16:51:46 -04001243 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1244 | SDHCI_QUIRK_BROKEN_ADMA;
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001245
Dong Aisheng69ed60e2013-10-18 19:48:49 +08001246 if (esdhc_is_usdhc(imx_data)) {
Dong Aisheng69ed60e2013-10-18 19:48:49 +08001247 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
Dong Aishenge2997c92013-10-30 22:09:52 +08001248 host->mmc->caps |= MMC_CAP_1_8V_DDR;
Dong Aisheng4245aff2015-05-27 18:13:31 +08001249 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
1250 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
Dong Aishenga75dcbf2016-07-12 15:46:24 +08001251
1252 /* clear tuning bits in case ROM has set it already */
1253 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
1254 writel(0x0, host->ioaddr + SDHCI_ACMD12_ERR);
1255 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
Dong Aisheng69ed60e2013-10-18 19:48:49 +08001256 }
Shawn Guof750ba92011-11-10 16:39:32 +08001257
Dong Aisheng6e9fd282013-10-18 19:48:43 +08001258 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1259 sdhci_esdhc_ops.platform_execute_tuning =
1260 esdhc_executing_tuning;
Dong Aisheng8b2bb0ad2013-11-04 16:38:27 +08001261
Dong Aisheng18094432015-05-27 18:13:28 +08001262 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
1263 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1264
Haibo Chen28b07672015-08-11 19:38:26 +08001265 if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
1266 host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
1267
Dong Aisheng91fa4252015-07-22 20:53:06 +08001268 if (of_id)
1269 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
1270 else
1271 err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data);
1272 if (err)
1273 goto disable_clk;
Dong Aishengad932202013-09-13 19:11:35 +08001274
Dong Aishengf3f5cf32016-07-12 15:46:21 +08001275 sdhci_esdhc_imx_hwinit(host);
1276
Shawn Guo85d65092011-05-27 23:48:12 +08001277 err = sdhci_add_host(host);
1278 if (err)
Shawn Guoe3af31c2012-11-26 14:39:43 +08001279 goto disable_clk;
Shawn Guo85d65092011-05-27 23:48:12 +08001280
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001281 pm_runtime_set_active(&pdev->dev);
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001282 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1283 pm_runtime_use_autosuspend(&pdev->dev);
1284 pm_suspend_ignore_children(&pdev->dev, 1);
Ulf Hansson77903c02014-12-11 15:12:25 +01001285 pm_runtime_enable(&pdev->dev);
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001286
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001287 return 0;
Wolfram Sang7e29c302011-02-26 14:44:41 +01001288
Shawn Guoe3af31c2012-11-26 14:39:43 +08001289disable_clk:
Sascha Hauer52dac612012-03-07 09:31:34 +01001290 clk_disable_unprepare(imx_data->clk_per);
1291 clk_disable_unprepare(imx_data->clk_ipg);
1292 clk_disable_unprepare(imx_data->clk_ahb);
Shawn Guoe3af31c2012-11-26 14:39:43 +08001293free_sdhci:
Shawn Guo85d65092011-05-27 23:48:12 +08001294 sdhci_pltfm_free(pdev);
1295 return err;
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001296}
1297
Bill Pemberton6e0ee712012-11-19 13:26:03 -05001298static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001299{
Shawn Guo85d65092011-05-27 23:48:12 +08001300 struct sdhci_host *host = platform_get_drvdata(pdev);
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001301 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +08001302 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Shawn Guo85d65092011-05-27 23:48:12 +08001303 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1304
Ulf Hansson0b414362014-12-11 14:56:15 +01001305 pm_runtime_get_sync(&pdev->dev);
1306 pm_runtime_disable(&pdev->dev);
1307 pm_runtime_put_noidle(&pdev->dev);
1308
Shawn Guo85d65092011-05-27 23:48:12 +08001309 sdhci_remove_host(host, dead);
Wolfram Sang0c6d49c2011-02-26 14:44:39 +01001310
Ulf Hansson0b414362014-12-11 14:56:15 +01001311 clk_disable_unprepare(imx_data->clk_per);
1312 clk_disable_unprepare(imx_data->clk_ipg);
1313 clk_disable_unprepare(imx_data->clk_ahb);
Sascha Hauer52dac612012-03-07 09:31:34 +01001314
Shawn Guo85d65092011-05-27 23:48:12 +08001315 sdhci_pltfm_free(pdev);
1316
1317 return 0;
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001318}
1319
Ulf Hansson2788ed42016-07-27 11:46:25 +02001320#ifdef CONFIG_PM_SLEEP
Dong Aisheng04143fb2016-07-12 15:46:12 +08001321static int sdhci_esdhc_suspend(struct device *dev)
1322{
Ulf Hansson3e3274a2016-07-27 12:17:14 +02001323 struct sdhci_host *host = dev_get_drvdata(dev);
1324
1325 return sdhci_suspend_host(host);
Dong Aisheng04143fb2016-07-12 15:46:12 +08001326}
1327
1328static int sdhci_esdhc_resume(struct device *dev)
1329{
Dong Aishengcc17e122016-07-12 15:46:13 +08001330 struct sdhci_host *host = dev_get_drvdata(dev);
Dong Aishengcc17e122016-07-12 15:46:13 +08001331
Dong Aisheng19dbfdd32016-07-12 15:46:23 +08001332 /* re-initialize hw state in case it's lost in low power mode */
1333 sdhci_esdhc_imx_hwinit(host);
Dong Aishengcc17e122016-07-12 15:46:13 +08001334
Ulf Hansson3e3274a2016-07-27 12:17:14 +02001335 return sdhci_resume_host(host);
Dong Aisheng04143fb2016-07-12 15:46:12 +08001336}
Ulf Hansson2788ed42016-07-27 11:46:25 +02001337#endif
Dong Aisheng04143fb2016-07-12 15:46:12 +08001338
Ulf Hansson2788ed42016-07-27 11:46:25 +02001339#ifdef CONFIG_PM
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001340static int sdhci_esdhc_runtime_suspend(struct device *dev)
1341{
1342 struct sdhci_host *host = dev_get_drvdata(dev);
1343 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +08001344 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001345 int ret;
1346
1347 ret = sdhci_runtime_suspend_host(host);
1348
Russell Kingbe138552014-04-25 12:55:56 +01001349 if (!sdhci_sdio_irq_enabled(host)) {
1350 clk_disable_unprepare(imx_data->clk_per);
1351 clk_disable_unprepare(imx_data->clk_ipg);
1352 }
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001353 clk_disable_unprepare(imx_data->clk_ahb);
1354
1355 return ret;
1356}
1357
1358static int sdhci_esdhc_runtime_resume(struct device *dev)
1359{
1360 struct sdhci_host *host = dev_get_drvdata(dev);
1361 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
Jisheng Zhang070e6d32016-02-16 21:08:20 +08001362 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001363
Russell Kingbe138552014-04-25 12:55:56 +01001364 if (!sdhci_sdio_irq_enabled(host)) {
1365 clk_prepare_enable(imx_data->clk_per);
1366 clk_prepare_enable(imx_data->clk_ipg);
1367 }
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001368 clk_prepare_enable(imx_data->clk_ahb);
1369
1370 return sdhci_runtime_resume_host(host);
1371}
1372#endif
1373
1374static const struct dev_pm_ops sdhci_esdhc_pmops = {
Dong Aisheng04143fb2016-07-12 15:46:12 +08001375 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume)
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001376 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend,
1377 sdhci_esdhc_runtime_resume, NULL)
1378};
1379
Shawn Guo85d65092011-05-27 23:48:12 +08001380static struct platform_driver sdhci_esdhc_imx_driver = {
1381 .driver = {
1382 .name = "sdhci-esdhc-imx",
Shawn Guoabfafc22011-06-30 15:44:44 +08001383 .of_match_table = imx_esdhc_dt_ids,
Dong Aisheng89d7e5c2013-11-04 16:38:29 +08001384 .pm = &sdhci_esdhc_pmops,
Shawn Guo85d65092011-05-27 23:48:12 +08001385 },
Shawn Guo57ed3312011-06-30 09:24:26 +08001386 .id_table = imx_esdhc_devtype,
Shawn Guo85d65092011-05-27 23:48:12 +08001387 .probe = sdhci_esdhc_imx_probe,
Bill Pemberton0433c142012-11-19 13:20:26 -05001388 .remove = sdhci_esdhc_imx_remove,
Wolfram Sang95f25ef2010-10-15 12:21:04 +02001389};
Shawn Guo85d65092011-05-27 23:48:12 +08001390
Axel Lind1f81a62011-11-26 12:55:43 +08001391module_platform_driver(sdhci_esdhc_imx_driver);
Shawn Guo85d65092011-05-27 23:48:12 +08001392
1393MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
Wolfram Sang035ff832015-04-20 15:51:42 +02001394MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
Shawn Guo85d65092011-05-27 23:48:12 +08001395MODULE_LICENSE("GPL v2");