| Srinivas Kandagatla | 20aedaf | 2019-01-28 14:27:47 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | |
| 3 | #ifndef __WCD9335_H__ |
| 4 | #define __WCD9335_H__ |
| 5 | |
| 6 | /* |
| Randy Dunlap | 09e5209 | 2020-07-19 11:09:01 -0700 | [diff] [blame] | 7 | * WCD9335 register base can change according to the mode it works in. |
| 8 | * In slimbus mode the reg base starts from 0x800. |
| 9 | * In i2s/i2c mode the reg base is 0x0. |
| Srinivas Kandagatla | 20aedaf | 2019-01-28 14:27:47 +0000 | [diff] [blame] | 10 | */ |
| Srinivas Kandagatla | d902e78 | 2020-03-06 15:26:33 +0000 | [diff] [blame] | 11 | #define WCD9335_REG(pg, r) ((pg << 8) | (r)) |
| Srinivas Kandagatla | 20aedaf | 2019-01-28 14:27:47 +0000 | [diff] [blame] | 12 | #define WCD9335_REG_OFFSET(r) (r & 0xFF) |
| Srinivas Kandagatla | d902e78 | 2020-03-06 15:26:33 +0000 | [diff] [blame] | 13 | #define WCD9335_PAGE_OFFSET(r) ((r >> 8) & 0xFF) |
| Srinivas Kandagatla | 20aedaf | 2019-01-28 14:27:47 +0000 | [diff] [blame] | 14 | |
| 15 | /* Page-0 Registers */ |
| 16 | #define WCD9335_PAGE0_PAGE_REGISTER WCD9335_REG(0x00, 0x000) |
| 17 | #define WCD9335_CODEC_RPM_CLK_GATE WCD9335_REG(0x00, 0x002) |
| 18 | #define WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK GENMASK(1, 0) |
| 19 | #define WCD9335_CODEC_RPM_CLK_MCLK_CFG WCD9335_REG(0x00, 0x003) |
| 20 | #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ BIT(0) |
| 21 | #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ BIT(0) |
| 22 | #define WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK GENMASK(1, 0) |
| 23 | #define WCD9335_CODEC_RPM_RST_CTL WCD9335_REG(0x00, 0x009) |
| 24 | #define WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL WCD9335_REG(0x00, 0x011) |
| 25 | #define WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0 WCD9335_REG(0x00, 0x021) |
| 26 | #define WCD9335_CHIP_TIER_CTRL_EFUSE_CTL WCD9335_REG(0x00, 0x025) |
| 27 | #define WCD9335_CHIP_TIER_CTRL_EFUSE_SSTATE_MASK GENMASK(4, 1) |
| 28 | #define WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK BIT(0) |
| 29 | #define WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE BIT(0) |
| 30 | #define WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0 WCD9335_REG(0x00, 0x029) |
| 31 | #define WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS WCD9335_REG(0x00, 0x039) |
| 32 | #define WCD9335_INTR_CFG WCD9335_REG(0x00, 0x081) |
| 33 | #define WCD9335_INTR_CLR_COMMIT WCD9335_REG(0x00, 0x082) |
| 34 | #define WCD9335_INTR_PIN1_MASK0 WCD9335_REG(0x00, 0x089) |
| 35 | #define WCD9335_INTR_PIN1_MASK1 WCD9335_REG(0x00, 0x08a) |
| 36 | #define WCD9335_INTR_PIN1_MASK2 WCD9335_REG(0x00, 0x08b) |
| 37 | #define WCD9335_INTR_PIN1_MASK3 WCD9335_REG(0x00, 0x08c) |
| 38 | #define WCD9335_INTR_PIN1_STATUS0 WCD9335_REG(0x00, 0x091) |
| 39 | #define WCD9335_INTR_PIN1_STATUS1 WCD9335_REG(0x00, 0x092) |
| 40 | #define WCD9335_INTR_PIN1_STATUS2 WCD9335_REG(0x00, 0x093) |
| 41 | #define WCD9335_INTR_PIN1_STATUS3 WCD9335_REG(0x00, 0x094) |
| 42 | #define WCD9335_INTR_PIN1_CLEAR0 WCD9335_REG(0x00, 0x099) |
| 43 | #define WCD9335_INTR_PIN1_CLEAR1 WCD9335_REG(0x00, 0x09a) |
| 44 | #define WCD9335_INTR_PIN1_CLEAR2 WCD9335_REG(0x00, 0x09b) |
| 45 | #define WCD9335_INTR_PIN1_CLEAR3 WCD9335_REG(0x00, 0x09c) |
| 46 | #define WCD9335_INTR_PIN2_MASK0 WCD9335_REG(0x00, 0x0a1) |
| 47 | #define WCD9335_INTR_PIN2_MASK1 WCD9335_REG(0x00, 0x0a2) |
| 48 | #define WCD9335_INTR_PIN2_MASK2 WCD9335_REG(0x00, 0x0a3) |
| 49 | #define WCD9335_INTR_PIN2_MASK3 WCD9335_REG(0x00, 0x0a4) |
| 50 | #define WCD9335_INTR_PIN2_STATUS0 WCD9335_REG(0x00, 0x0a9) |
| 51 | #define WCD9335_INTR_PIN2_STATUS1 WCD9335_REG(0x00, 0x0aa) |
| 52 | #define WCD9335_INTR_PIN2_STATUS2 WCD9335_REG(0x00, 0x0ab) |
| 53 | #define WCD9335_INTR_PIN2_STATUS3 WCD9335_REG(0x00, 0x0ac) |
| 54 | #define WCD9335_INTR_PIN2_CLEAR0 WCD9335_REG(0x00, 0x0b1) |
| 55 | #define WCD9335_INTR_PIN2_CLEAR1 WCD9335_REG(0x00, 0x0b2) |
| 56 | #define WCD9335_INTR_PIN2_CLEAR2 WCD9335_REG(0x00, 0x0b3) |
| 57 | #define WCD9335_INTR_PIN2_CLEAR3 WCD9335_REG(0x00, 0x0b4) |
| 58 | #define WCD9335_INTR_LEVEL0 WCD9335_REG(0x00, 0x0e1) |
| 59 | #define WCD9335_INTR_LEVEL1 WCD9335_REG(0x00, 0x0e2) |
| 60 | #define WCD9335_INTR_LEVEL2 WCD9335_REG(0x00, 0x0e3) |
| 61 | #define WCD9335_INTR_LEVEL3 WCD9335_REG(0x00, 0x0e4) |
| 62 | |
| 63 | /* Page-1 Registers */ |
| 64 | #define WCD9335_CPE_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x001) |
| 65 | #define WCD9335_CPE_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x002) |
| 66 | #define WCD9335_CPE_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x003) |
| 67 | #define WCD9335_CPE_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x004) |
| 68 | #define WCD9335_CPE_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x005) |
| 69 | #define WCD9335_CPE_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x006) |
| 70 | #define WCD9335_CPE_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x007) |
| 71 | #define WCD9335_CPE_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x008) |
| 72 | #define WCD9335_CPE_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x009) |
| 73 | #define WCD9335_CPE_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x00a) |
| 74 | #define WCD9335_CPE_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x00b) |
| 75 | #define WCD9335_CPE_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x00c) |
| 76 | #define WCD9335_CPE_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x00d) |
| 77 | #define WCD9335_CPE_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x00e) |
| 78 | #define WCD9335_CPE_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x00f) |
| 79 | #define WCD9335_CPE_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x010) |
| 80 | #define WCD9335_CPE_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x011) |
| 81 | #define WCD9335_CPE_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x012) |
| 82 | #define WCD9335_CPE_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x013) |
| 83 | #define WCD9335_CPE_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x014) |
| 84 | #define WCD9335_CPE_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x015) |
| 85 | #define WCD9335_CPE_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x016) |
| 86 | #define WCD9335_CPE_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x017) |
| 87 | #define WCD9335_CPE_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x018) |
| 88 | #define WCD9335_CPE_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x019) |
| 89 | #define WCD9335_CPE_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x01a) |
| 90 | #define WCD9335_CPE_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x01b) |
| 91 | #define WCD9335_CPE_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x01c) |
| 92 | #define WCD9335_CPE_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x01d) |
| 93 | #define WCD9335_CPE_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x01e) |
| 94 | #define WCD9335_CPE_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x01f) |
| 95 | #define WCD9335_CPE_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x020) |
| 96 | #define WCD9335_CPE_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x021) |
| 97 | #define WCD9335_CPE_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x022) |
| 98 | #define WCD9335_CPE_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x023) |
| 99 | #define WCD9335_CPE_FLL_FLL_MODE WCD9335_REG(0x01, 0x024) |
| 100 | #define WCD9335_CPE_FLL_STATUS_0 WCD9335_REG(0x01, 0x025) |
| 101 | #define WCD9335_CPE_FLL_STATUS_1 WCD9335_REG(0x01, 0x026) |
| 102 | #define WCD9335_CPE_FLL_STATUS_2 WCD9335_REG(0x01, 0x027) |
| 103 | #define WCD9335_CPE_FLL_STATUS_3 WCD9335_REG(0x01, 0x028) |
| 104 | #define WCD9335_I2S_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x041) |
| 105 | #define WCD9335_I2S_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x042) |
| 106 | #define WCD9335_I2S_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x043) |
| 107 | #define WCD9335_I2S_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x044) |
| 108 | #define WCD9335_I2S_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x045) |
| 109 | #define WCD9335_I2S_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x046) |
| 110 | #define WCD9335_I2S_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x047) |
| 111 | #define WCD9335_I2S_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x048) |
| 112 | #define WCD9335_I2S_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x049) |
| 113 | #define WCD9335_I2S_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x04a) |
| 114 | #define WCD9335_I2S_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x04b) |
| 115 | #define WCD9335_I2S_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x04c) |
| 116 | #define WCD9335_I2S_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x04d) |
| 117 | #define WCD9335_I2S_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x04e) |
| 118 | #define WCD9335_I2S_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x04f) |
| 119 | #define WCD9335_I2S_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x050) |
| 120 | #define WCD9335_I2S_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x051) |
| 121 | #define WCD9335_I2S_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x052) |
| 122 | #define WCD9335_I2S_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x053) |
| 123 | #define WCD9335_I2S_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x054) |
| 124 | #define WCD9335_I2S_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x055) |
| 125 | #define WCD9335_I2S_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x056) |
| 126 | #define WCD9335_I2S_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x057) |
| 127 | #define WCD9335_I2S_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x058) |
| 128 | #define WCD9335_I2S_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x059) |
| 129 | #define WCD9335_I2S_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x05a) |
| 130 | #define WCD9335_I2S_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x05b) |
| 131 | #define WCD9335_I2S_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x05c) |
| 132 | #define WCD9335_I2S_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x05d) |
| 133 | #define WCD9335_I2S_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x05e) |
| 134 | #define WCD9335_I2S_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x05f) |
| 135 | #define WCD9335_I2S_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x060) |
| 136 | #define WCD9335_I2S_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x061) |
| 137 | #define WCD9335_I2S_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x062) |
| 138 | #define WCD9335_I2S_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x063) |
| 139 | #define WCD9335_I2S_FLL_FLL_MODE WCD9335_REG(0x01, 0x064) |
| 140 | #define WCD9335_I2S_FLL_STATUS_0 WCD9335_REG(0x01, 0x065) |
| 141 | #define WCD9335_I2S_FLL_STATUS_1 WCD9335_REG(0x01, 0x066) |
| 142 | #define WCD9335_I2S_FLL_STATUS_2 WCD9335_REG(0x01, 0x067) |
| 143 | #define WCD9335_I2S_FLL_STATUS_3 WCD9335_REG(0x01, 0x068) |
| 144 | #define WCD9335_SB_FLL_USER_CTL_0 WCD9335_REG(0x01, 0x081) |
| 145 | #define WCD9335_SB_FLL_USER_CTL_1 WCD9335_REG(0x01, 0x082) |
| 146 | #define WCD9335_SB_FLL_USER_CTL_2 WCD9335_REG(0x01, 0x083) |
| 147 | #define WCD9335_SB_FLL_USER_CTL_3 WCD9335_REG(0x01, 0x084) |
| 148 | #define WCD9335_SB_FLL_USER_CTL_4 WCD9335_REG(0x01, 0x085) |
| 149 | #define WCD9335_SB_FLL_USER_CTL_5 WCD9335_REG(0x01, 0x086) |
| 150 | #define WCD9335_SB_FLL_USER_CTL_6 WCD9335_REG(0x01, 0x087) |
| 151 | #define WCD9335_SB_FLL_USER_CTL_7 WCD9335_REG(0x01, 0x088) |
| 152 | #define WCD9335_SB_FLL_USER_CTL_8 WCD9335_REG(0x01, 0x089) |
| 153 | #define WCD9335_SB_FLL_USER_CTL_9 WCD9335_REG(0x01, 0x08a) |
| 154 | #define WCD9335_SB_FLL_L_VAL_CTL_0 WCD9335_REG(0x01, 0x08b) |
| 155 | #define WCD9335_SB_FLL_L_VAL_CTL_1 WCD9335_REG(0x01, 0x08c) |
| 156 | #define WCD9335_SB_FLL_DSM_FRAC_CTL_0 WCD9335_REG(0x01, 0x08d) |
| 157 | #define WCD9335_SB_FLL_DSM_FRAC_CTL_1 WCD9335_REG(0x01, 0x08e) |
| 158 | #define WCD9335_SB_FLL_CONFIG_CTL_0 WCD9335_REG(0x01, 0x08f) |
| 159 | #define WCD9335_SB_FLL_CONFIG_CTL_1 WCD9335_REG(0x01, 0x090) |
| 160 | #define WCD9335_SB_FLL_CONFIG_CTL_2 WCD9335_REG(0x01, 0x091) |
| 161 | #define WCD9335_SB_FLL_CONFIG_CTL_3 WCD9335_REG(0x01, 0x092) |
| 162 | #define WCD9335_SB_FLL_CONFIG_CTL_4 WCD9335_REG(0x01, 0x093) |
| 163 | #define WCD9335_SB_FLL_TEST_CTL_0 WCD9335_REG(0x01, 0x094) |
| 164 | #define WCD9335_SB_FLL_TEST_CTL_1 WCD9335_REG(0x01, 0x095) |
| 165 | #define WCD9335_SB_FLL_TEST_CTL_2 WCD9335_REG(0x01, 0x096) |
| 166 | #define WCD9335_SB_FLL_TEST_CTL_3 WCD9335_REG(0x01, 0x097) |
| 167 | #define WCD9335_SB_FLL_TEST_CTL_4 WCD9335_REG(0x01, 0x098) |
| 168 | #define WCD9335_SB_FLL_TEST_CTL_5 WCD9335_REG(0x01, 0x099) |
| 169 | #define WCD9335_SB_FLL_TEST_CTL_6 WCD9335_REG(0x01, 0x09a) |
| 170 | #define WCD9335_SB_FLL_TEST_CTL_7 WCD9335_REG(0x01, 0x09b) |
| 171 | #define WCD9335_SB_FLL_FREQ_CTL_0 WCD9335_REG(0x01, 0x09c) |
| 172 | #define WCD9335_SB_FLL_FREQ_CTL_1 WCD9335_REG(0x01, 0x09d) |
| 173 | #define WCD9335_SB_FLL_FREQ_CTL_2 WCD9335_REG(0x01, 0x09e) |
| 174 | #define WCD9335_SB_FLL_FREQ_CTL_3 WCD9335_REG(0x01, 0x09f) |
| 175 | #define WCD9335_SB_FLL_SSC_CTL_0 WCD9335_REG(0x01, 0x0a0) |
| 176 | #define WCD9335_SB_FLL_SSC_CTL_1 WCD9335_REG(0x01, 0x0a1) |
| 177 | #define WCD9335_SB_FLL_SSC_CTL_2 WCD9335_REG(0x01, 0x0a2) |
| 178 | #define WCD9335_SB_FLL_SSC_CTL_3 WCD9335_REG(0x01, 0x0a3) |
| 179 | #define WCD9335_SB_FLL_FLL_MODE WCD9335_REG(0x01, 0x0a4) |
| 180 | #define WCD9335_SB_FLL_STATUS_0 WCD9335_REG(0x01, 0x0a5) |
| 181 | #define WCD9335_SB_FLL_STATUS_1 WCD9335_REG(0x01, 0x0a6) |
| 182 | #define WCD9335_SB_FLL_STATUS_2 WCD9335_REG(0x01, 0x0a7) |
| 183 | #define WCD9335_SB_FLL_STATUS_3 WCD9335_REG(0x01, 0x0a8) |
| 184 | |
| 185 | /* Page-2 Registers */ |
| 186 | #define WCD9335_PAGE2_PAGE_REGISTER WCD9335_REG(0x02, 0x000) |
| 187 | #define WCD9335_CPE_SS_DMIC0_CTL WCD9335_REG(0x02, 0x063) |
| 188 | #define WCD9335_CPE_SS_DMIC1_CTL WCD9335_REG(0x02, 0x064) |
| 189 | #define WCD9335_CPE_SS_DMIC2_CTL WCD9335_REG(0x02, 0x065) |
| 190 | #define WCD9335_CPE_SS_DMIC_CFG WCD9335_REG(0x02, 0x066) |
| 191 | #define WCD9335_SOC_MAD_AUDIO_CTL_2 WCD9335_REG(0x02, 0x084) |
| 192 | |
| 193 | /* Page-6 Registers */ |
| 194 | #define WCD9335_PAGE6_PAGE_REGISTER WCD9335_REG(0x06, 0x000) |
| 195 | #define WCD9335_ANA_BIAS WCD9335_REG(0x06, 0x001) |
| 196 | #define WCD9335_ANA_BIAS_EN_MASK BIT(7) |
| 197 | #define WCD9335_ANA_BIAS_ENABLE BIT(7) |
| 198 | #define WCD9335_ANA_BIAS_DISABLE 0 |
| 199 | #define WCD9335_ANA_BIAS_PRECHRG_EN_MASK BIT(6) |
| 200 | #define WCD9335_ANA_BIAS_PRECHRG_ENABLE BIT(6) |
| 201 | #define WCD9335_ANA_BIAS_PRECHRG_DISABLE 0 |
| 202 | #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE BIT(5) |
| 203 | #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_AUTO BIT(5) |
| 204 | #define WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL 0 |
| 205 | #define WCD9335_ANA_CLK_TOP WCD9335_REG(0x06, 0x002) |
| 206 | #define WCD9335_ANA_CLK_MCLK_EN_MASK BIT(2) |
| 207 | #define WCD9335_ANA_CLK_MCLK_ENABLE BIT(2) |
| 208 | #define WCD9335_ANA_CLK_MCLK_DISABLE 0 |
| 209 | #define WCD9335_ANA_CLK_MCLK_SRC_MASK BIT(3) |
| 210 | #define WCD9335_ANA_CLK_MCLK_SRC_RCO BIT(3) |
| 211 | #define WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL 0 |
| 212 | #define WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK BIT(7) |
| 213 | #define WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE BIT(7) |
| 214 | #define WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE 0 |
| 215 | #define WCD9335_ANA_RCO WCD9335_REG(0x06, 0x003) |
| 216 | #define WCD9335_ANA_RCO_BG_EN_MASK BIT(7) |
| 217 | #define WCD9335_ANA_RCO_BG_ENABLE BIT(7) |
| 218 | #define WCD9335_ANA_BUCK_VOUT_D WCD9335_REG(0x06, 0x005) |
| 219 | #define WCD9335_ANA_BUCK_VOUT_MASK GENMASK(7, 0) |
| 220 | #define WCD9335_ANA_BUCK_CTL WCD9335_REG(0x06, 0x006) |
| 221 | #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK BIT(1) |
| 222 | #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT BIT(1) |
| 223 | #define WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_INT 0 |
| 224 | #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK BIT(2) |
| 225 | #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT BIT(2) |
| 226 | #define WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_INT 0 |
| 227 | #define WCD9335_ANA_BUCK_CTL_RAMP_START_MASK BIT(7) |
| 228 | #define WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE BIT(7) |
| 229 | #define WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE 0 |
| 230 | #define WCD9335_ANA_RX_SUPPLIES WCD9335_REG(0x06, 0x008) |
| 231 | #define WCD9335_ANA_RX_BIAS_ENABLE_MASK BIT(0) |
| 232 | #define WCD9335_ANA_RX_BIAS_ENABLE BIT(0) |
| 233 | #define WCD9335_ANA_RX_BIAS_DISABLE 0 |
| 234 | #define WCD9335_ANA_HPH WCD9335_REG(0x06, 0x009) |
| 235 | #define WCD9335_ANA_EAR WCD9335_REG(0x06, 0x00a) |
| 236 | #define WCD9335_ANA_LO_1_2 WCD9335_REG(0x06, 0x00b) |
| 237 | #define WCD9335_ANA_LO_3_4 WCD9335_REG(0x06, 0x00c) |
| 238 | #define WCD9335_ANA_AMIC1 WCD9335_REG(0x06, 0x00e) |
| 239 | #define WCD9335_ANA_AMIC2 WCD9335_REG(0x06, 0x00f) |
| 240 | #define WCD9335_ANA_AMIC3 WCD9335_REG(0x06, 0x010) |
| 241 | #define WCD9335_ANA_AMIC4 WCD9335_REG(0x06, 0x011) |
| 242 | #define WCD9335_ANA_AMIC5 WCD9335_REG(0x06, 0x012) |
| 243 | #define WCD9335_ANA_AMIC6 WCD9335_REG(0x06, 0x013) |
| 244 | #define WCD9335_ANA_MBHC_MECH WCD9335_REG(0x06, 0x014) |
| 245 | #define WCD9335_MBHC_L_DET_EN_MASK BIT(7) |
| 246 | #define WCD9335_MBHC_L_DET_EN BIT(7) |
| 247 | #define WCD9335_MBHC_GND_DET_EN_MASK BIT(6) |
| 248 | #define WCD9335_MBHC_MECH_DETECT_TYPE_MASK BIT(5) |
| 249 | #define WCD9335_MBHC_MECH_DETECT_TYPE_SHIFT 5 |
| 250 | #define WCD9335_MBHC_HPHL_PLUG_TYPE_MASK BIT(4) |
| 251 | #define WCD9335_MBHC_HPHL_PLUG_TYPE_NO BIT(4) |
| 252 | #define WCD9335_MBHC_GND_PLUG_TYPE_MASK BIT(3) |
| 253 | #define WCD9335_MBHC_GND_PLUG_TYPE_NO BIT(3) |
| 254 | #define WCD9335_MBHC_HSL_PULLUP_COMP_EN BIT(2) |
| 255 | #define WCD9335_MBHC_HPHL_100K_TO_GND_EN BIT(0) |
| 256 | |
| 257 | #define WCD9335_ANA_MBHC_ELECT WCD9335_REG(0x06, 0x015) |
| 258 | #define WCD9335_ANA_MBHC_BD_ISRC_CTL_MASK GENMASK(6, 4) |
| 259 | #define WCD9335_ANA_MBHC_BD_ISRC_100UA GENMASK(5, 4) |
| 260 | #define WCD9335_ANA_MBHC_BD_ISRC_OFF 0 |
| 261 | #define WCD9335_ANA_MBHC_BIAS_EN_MASK BIT(0) |
| 262 | #define WCD9335_ANA_MBHC_BIAS_EN BIT(0) |
| 263 | #define WCD9335_ANA_MBHC_ZDET WCD9335_REG(0x06, 0x016) |
| 264 | #define WCD9335_ANA_MBHC_RESULT_1 WCD9335_REG(0x06, 0x017) |
| 265 | #define WCD9335_ANA_MBHC_RESULT_2 WCD9335_REG(0x06, 0x018) |
| 266 | #define WCD9335_ANA_MBHC_RESULT_3 WCD9335_REG(0x06, 0x019) |
| 267 | #define WCD9335_MBHC_BTN_RESULT_MASK GENMASK(2, 0) |
| 268 | #define WCD9335_ANA_MBHC_BTN0 WCD9335_REG(0x06, 0x01a) |
| 269 | #define WCD9335_ANA_MBHC_BTN1 WCD9335_REG(0x06, 0x01b) |
| 270 | #define WCD9335_ANA_MBHC_BTN2 WCD9335_REG(0x06, 0x01c) |
| 271 | #define WCD9335_ANA_MBHC_BTN3 WCD9335_REG(0x06, 0x01d) |
| 272 | #define WCD9335_ANA_MBHC_BTN4 WCD9335_REG(0x06, 0x01e) |
| 273 | #define WCD9335_ANA_MBHC_BTN5 WCD9335_REG(0x06, 0x01f) |
| 274 | #define WCD9335_ANA_MBHC_BTN6 WCD9335_REG(0x06, 0x020) |
| 275 | #define WCD9335_ANA_MBHC_BTN7 WCD9335_REG(0x06, 0x021) |
| 276 | #define WCD9335_ANA_MICB1 WCD9335_REG(0x06, 0x022) |
| 277 | #define WCD9335_ANA_MICB2 WCD9335_REG(0x06, 0x023) |
| 278 | #define WCD9335_ANA_MICB2_ENABLE BIT(6) |
| 279 | #define WCD9335_ANA_MICB2_RAMP WCD9335_REG(0x06, 0x024) |
| 280 | #define WCD9335_ANA_MICB3 WCD9335_REG(0x06, 0x025) |
| 281 | #define WCD9335_ANA_MICB4 WCD9335_REG(0x06, 0x026) |
| 282 | #define WCD9335_ANA_VBADC WCD9335_REG(0x06, 0x027) |
| 283 | #define WCD9335_BIAS_VBG_FINE_ADJ WCD9335_REG(0x06, 0x029) |
| 284 | #define WCD9335_RCO_CTRL_2 WCD9335_REG(0x06, 0x02f) |
| 285 | #define WCD9335_SIDO_SIDO_CCL_2 WCD9335_REG(0x06, 0x042) |
| 286 | #define WCD9335_SIDO_SIDO_CCL_4 WCD9335_REG(0x06, 0x044) |
| 287 | #define WCD9335_SIDO_SIDO_CCL_8 WCD9335_REG(0x06, 0x048) |
| 288 | #define WCD9335_SIDO_SIDO_CCL_10 WCD9335_REG(0x06, 0x04a) |
| 289 | #define WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF 0x2 |
| 290 | /* Comparator 1 and 2 Bias current at 1P0UA with start pulse width of C320FF */ |
| 291 | #define WCD9335_SIDO_SIDO_CCL_DEF_VALUE 0x6e |
| 292 | #define WCD9335_SIDO_SIDO_TEST_2 WCD9335_REG(0x06, 0x055) |
| 293 | #define WCD9335_MBHC_CTL_1 WCD9335_REG(0x06, 0x056) |
| 294 | #define WCD9335_MBHC_BTN_DBNC_MASK GENMASK(1, 0) |
| 295 | #define WCD9335_MBHC_BTN_DBNC_T_16_MS 0x2 |
| 296 | #define WCD9335_MBHC_CTL_RCO_EN_MASK BIT(7) |
| 297 | #define WCD9335_MBHC_CTL_RCO_EN BIT(7) |
| 298 | |
| 299 | #define WCD9335_MBHC_CTL_2 WCD9335_REG(0x06, 0x057) |
| 300 | #define WCD9335_MBHC_HS_VREF_CTL_MASK GENMASK(1, 0) |
| 301 | #define WCD9335_MBHC_HS_VREF_1P5_V 0x1 |
| 302 | #define WCD9335_MBHC_PLUG_DETECT_CTL WCD9335_REG(0x06, 0x058) |
| 303 | #define WCD9335_MBHC_HSDET_PULLUP_CTL_MASK GENMASK(7, 6) |
| 304 | #define WCD9335_MBHC_HSDET_PULLUP_CTL_SHIFT 6 |
| 305 | #define WCD9335_MBHC_HSDET_PULLUP_CTL_1_2P0_UA 0x80 |
| 306 | #define WCD9335_MBHC_DBNC_TIMER_INSREM_DBNC_T_96_MS 0x6 |
| 307 | |
| 308 | #define WCD9335_MBHC_ZDET_RAMP_CTL WCD9335_REG(0x06, 0x05a) |
| 309 | #define WCD9335_VBADC_IBIAS_FE WCD9335_REG(0x06, 0x05e) |
| 310 | #define WCD9335_FLYBACK_CTRL_1 WCD9335_REG(0x06, 0x0b1) |
| 311 | #define WCD9335_RX_BIAS_HPH_PA WCD9335_REG(0x06, 0x0bb) |
| 312 | #define WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK GENMASK(3, 0) |
| 313 | #define WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2 WCD9335_REG(0x06, 0x0bc) |
| 314 | #define WCD9335_RX_BIAS_HPH_RDAC_LDO WCD9335_REG(0x06, 0x0bd) |
| 315 | #define WCD9335_RX_BIAS_FLYB_BUFF WCD9335_REG(0x06, 0x0c7) |
| 316 | #define WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK GENMASK(3, 0) |
| 317 | #define WCD9335_RX_BIAS_FLYB_I_0P0_UA 0 |
| 318 | #define WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK GENMASK(7, 4) |
| 319 | #define WCD9335_RX_BIAS_FLYB_MID_RST WCD9335_REG(0x06, 0x0c8) |
| 320 | #define WCD9335_HPH_CNP_WG_CTL WCD9335_REG(0x06, 0x0cc) |
| 321 | #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK GENMASK(2, 0) |
| 322 | #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500 0x2 |
| 323 | #define WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000 0x3 |
| 324 | #define WCD9335_HPH_OCP_CTL WCD9335_REG(0x06, 0x0ce) |
| 325 | #define WCD9335_HPH_AUTO_CHOP WCD9335_REG(0x06, 0x0cf) |
| 326 | #define WCD9335_HPH_AUTO_CHOP_MASK BIT(5) |
| 327 | #define WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE BIT(5) |
| 328 | #define WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN 0 |
| 329 | #define WCD9335_HPH_PA_CTL1 WCD9335_REG(0x06, 0x0d1) |
| 330 | #define WCD9335_HPH_PA_GM3_IB_SCALE_MASK GENMASK(3, 1) |
| 331 | #define WCD9335_HPH_PA_CTL2 WCD9335_REG(0x06, 0x0d2) |
| 332 | #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK BIT(2) |
| 333 | #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE BIT(2) |
| 334 | #define WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE 0 |
| 335 | #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK BIT(3) |
| 336 | #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE BIT(3) |
| 337 | #define WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE 0 |
| 338 | #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK BIT(5) |
| 339 | #define WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE BIT(5) |
| 340 | #define WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE 0 |
| 341 | #define WCD9335_HPH_L_EN WCD9335_REG(0x06, 0x0d3) |
| 342 | #define WCD9335_HPH_CONST_SEL_L_MASK GENMASK(7, 6) |
| 343 | #define WCD9335_HPH_CONST_SEL_L_BYPASS 0 |
| 344 | #define WCD9335_HPH_CONST_SEL_L_LP_PATH 0x40 |
| 345 | #define WCD9335_HPH_CONST_SEL_L_HQ_PATH 0x80 |
| 346 | #define WCD9335_HPH_PA_GAIN_MASK GENMASK(4, 0) |
| 347 | #define WCD9335_HPH_GAIN_SRC_SEL_MASK BIT(5) |
| 348 | #define WCD9335_HPH_GAIN_SRC_SEL_COMPANDER 0 |
| 349 | #define WCD9335_HPH_GAIN_SRC_SEL_REGISTER BIT(5) |
| 350 | #define WCD9335_HPH_L_TEST WCD9335_REG(0x06, 0x0d4) |
| 351 | #define WCD9335_HPH_R_EN WCD9335_REG(0x06, 0x0d6) |
| 352 | #define WCD9335_HPH_R_TEST WCD9335_REG(0x06, 0x0d7) |
| 353 | #define WCD9335_HPH_R_ATEST WCD9335_REG(0x06, 0x0d8) |
| 354 | #define WCD9335_HPH_RDAC_LDO_CTL WCD9335_REG(0x06, 0x0db) |
| 355 | #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK GENMASK(2, 0) |
| 356 | #define WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60 0x1 |
| 357 | #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK GENMASK(6, 4) |
| 358 | #define WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60 0x10 |
| 359 | #define WCD9335_HPH_REFBUFF_LP_CTL WCD9335_REG(0x06, 0x0de) |
| 360 | #define WCD9335_HPH_L_DAC_CTL WCD9335_REG(0x06, 0x0df) |
| 361 | #define WCD9335_HPH_DAC_LDO_POWERMODE_MASK BIT(0) |
| 362 | #define WCD9335_HPH_DAC_LDO_POWERMODE_LOWPOWER 0 |
| 363 | #define WCD9335_HPH_DAC_LDO_POWERMODE_UHQA BIT(0) |
| 364 | #define WCD9335_HPH_DAC_LDO_UHQA_OV_MASK BIT(1) |
| 365 | #define WCD9335_HPH_DAC_LDO_UHQA_OV_ENABLE BIT(1) |
| 366 | #define WCD9335_HPH_DAC_LDO_UHQA_OV_DISABLE 0 |
| 367 | |
| 368 | #define WCD9335_EAR_CMBUFF WCD9335_REG(0x06, 0x0e2) |
| 369 | #define WCD9335_DIFF_LO_LO2_COMPANDER WCD9335_REG(0x06, 0x0ea) |
| 370 | #define WCD9335_DIFF_LO_LO1_COMPANDER WCD9335_REG(0x06, 0x0eb) |
| 371 | #define WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ WCD9335_REG(0x06, 0x0f1) |
| 372 | #define WCD9335_DIFF_LO_COM_PA_FREQ WCD9335_REG(0x06, 0x0f2) |
| 373 | #define WCD9335_SE_LO_LO3_GAIN WCD9335_REG(0x06, 0x0f8) |
| 374 | #define WCD9335_SE_LO_LO3_CTRL WCD9335_REG(0x06, 0x0f9) |
| 375 | #define WCD9335_SE_LO_LO4_GAIN WCD9335_REG(0x06, 0x0fa) |
| 376 | |
| 377 | /* Page-10 Registers */ |
| 378 | #define WCD9335_CDC_TX0_TX_PATH_CTL WCD9335_REG(0x0a, 0x031) |
| 379 | #define WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK GENMASK(3, 0) |
| 380 | #define WCD9335_CDC_TX_PATH_CTL(dec) WCD9335_REG(0xa, (0x31 + dec * 0x10)) |
| 381 | #define WCD9335_CDC_TX0_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x032) |
| 382 | #define WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK BIT(7) |
| 383 | #define WCD9335_CDC_TX_ADC_DMIC_SEL BIT(7) |
| 384 | #define WCD9335_CDC_TX_ADC_AMIC_SEL 0 |
| 385 | #define WCD9335_CDC_TX0_TX_VOL_CTL WCD9335_REG(0x0a, 0x034) |
| 386 | #define WCD9335_CDC_TX0_TX_PATH_SEC2 WCD9335_REG(0x0a, 0x039) |
| 387 | #define WCD9335_CDC_TX0_TX_PATH_SEC7 WCD9335_REG(0x0a, 0x03e) |
| 388 | #define WCD9335_CDC_TX1_TX_PATH_CTL WCD9335_REG(0x0a, 0x041) |
| 389 | #define WCD9335_CDC_TX1_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x042) |
| 390 | #define WCD9335_CDC_TX2_TX_PATH_CTL WCD9335_REG(0x0a, 0x051) |
| 391 | #define WCD9335_CDC_TX2_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x052) |
| 392 | #define WCD9335_CDC_TX2_TX_VOL_CTL WCD9335_REG(0x0a, 0x054) |
| 393 | #define WCD9335_CDC_TX3_TX_PATH_CTL WCD9335_REG(0x0a, 0x061) |
| 394 | #define WCD9335_CDC_TX3_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x062) |
| 395 | #define WCD9335_CDC_TX3_TX_VOL_CTL WCD9335_REG(0x0a, 0x064) |
| 396 | #define WCD9335_CDC_TX4_TX_PATH_CTL WCD9335_REG(0x0a, 0x071) |
| 397 | #define WCD9335_CDC_TX4_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x072) |
| 398 | #define WCD9335_CDC_TX4_TX_VOL_CTL WCD9335_REG(0x0a, 0x074) |
| 399 | #define WCD9335_CDC_TX5_TX_PATH_CTL WCD9335_REG(0x0a, 0x081) |
| 400 | #define WCD9335_CDC_TX5_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x082) |
| 401 | #define WCD9335_CDC_TX5_TX_VOL_CTL WCD9335_REG(0x0a, 0x084) |
| 402 | #define WCD9335_CDC_TX6_TX_PATH_CTL WCD9335_REG(0x0a, 0x091) |
| 403 | #define WCD9335_CDC_TX6_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x092) |
| 404 | #define WCD9335_CDC_TX6_TX_VOL_CTL WCD9335_REG(0x0a, 0x094) |
| 405 | #define WCD9335_CDC_TX7_TX_PATH_CTL WCD9335_REG(0x0a, 0x0a1) |
| 406 | #define WCD9335_CDC_TX7_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x0a2) |
| 407 | #define WCD9335_CDC_TX7_TX_VOL_CTL WCD9335_REG(0x0a, 0x0a4) |
| 408 | #define WCD9335_CDC_TX8_TX_PATH_CTL WCD9335_REG(0x0a, 0x0b1) |
| 409 | #define WCD9335_CDC_TX8_TX_PATH_CFG0 WCD9335_REG(0x0a, 0x0b2) |
| 410 | #define WCD9335_CDC_TX8_TX_VOL_CTL WCD9335_REG(0x0a, 0x0b4) |
| 411 | #define WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0c3) |
| 412 | #define WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0c7) |
| 413 | #define WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0cb) |
| 414 | #define WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0 WCD9335_REG(0x0a, 0x0cf) |
| 415 | |
| 416 | /* Page-11 Registers */ |
| 417 | #define WCD9335_PAGE11_PAGE_REGISTER WCD9335_REG(0x0b, 0x000) |
| 418 | #define WCD9335_CDC_COMPANDER1_CTL0 WCD9335_REG(0x0b, 0x001) |
| 419 | #define WCD9335_CDC_COMPANDER1_CTL(c) WCD9335_REG(0x0b, (0x001 + c * 0x8)) |
| 420 | #define WCD9335_CDC_COMPANDER_CLK_EN_MASK BIT(0) |
| 421 | #define WCD9335_CDC_COMPANDER_CLK_ENABLE BIT(0) |
| 422 | #define WCD9335_CDC_COMPANDER_CLK_DISABLE 0 |
| 423 | #define WCD9335_CDC_COMPANDER_SOFT_RST_MASK BIT(1) |
| 424 | #define WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE BIT(1) |
| 425 | #define WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE 0 |
| 426 | #define WCD9335_CDC_COMPANDER_HALT_MASK BIT(2) |
| 427 | #define WCD9335_CDC_COMPANDER_HALT BIT(2) |
| 428 | #define WCD9335_CDC_COMPANDER_NOHALT 0 |
| 429 | #define WCD9335_CDC_COMPANDER7_CTL3 WCD9335_REG(0x0b, 0x034) |
| 430 | #define WCD9335_CDC_COMPANDER7_CTL7 WCD9335_REG(0x0b, 0x038) |
| 431 | #define WCD9335_CDC_COMPANDER8_CTL3 WCD9335_REG(0x0b, 0x03c) |
| 432 | #define WCD9335_CDC_COMPANDER8_CTL7 WCD9335_REG(0x0b, 0x040) |
| 433 | #define WCD9335_CDC_RX0_RX_PATH_CTL WCD9335_REG(0x0b, 0x041) |
| 434 | #define WCD9335_CDC_RX_PGA_MUTE_EN_MASK BIT(4) |
| 435 | #define WCD9335_CDC_RX_PGA_MUTE_ENABLE BIT(4) |
| 436 | #define WCD9335_CDC_RX_PGA_MUTE_DISABLE 0 |
| 437 | #define WCD9335_CDC_RX_CLK_EN_MASK BIT(5) |
| 438 | #define WCD9335_CDC_RX_CLK_ENABLE BIT(5) |
| 439 | #define WCD9335_CDC_RX_CLK_DISABLE 0 |
| 440 | #define WCD9335_CDC_RX_RESET_MASK BIT(6) |
| 441 | #define WCD9335_CDC_RX_RESET_ENABLE BIT(6) |
| 442 | #define WCD9335_CDC_RX_RESET_DISABLE 0 |
| 443 | #define WCD9335_CDC_RX_PATH_CTL(rx) WCD9335_REG(0x0b, (0x041 + rx * 0x14)) |
| 444 | #define WCD9335_CDC_RX0_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x042) |
| 445 | #define WCD9335_CDC_RX0_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x043) |
| 446 | #define WCD9335_CDC_RX0_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x044) |
| 447 | #define WCD9335_CDC_RX0_RX_VOL_CTL WCD9335_REG(0x0b, 0x045) |
| 448 | #define WCD9335_CDC_RX0_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x046) |
| 449 | #define WCD9335_CDC_MIX_PCM_RATE_MASK GENMASK(3, 0) |
| 450 | #define WCD9335_CDC_RX_PATH_MIX_CTL(rx) WCD9335_REG(0x0b, (0x46 + rx * 0x14)) |
| 451 | #define WCD9335_CDC_RX0_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x047) |
| 452 | #define WCD9335_CDC_RX0_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x048) |
| 453 | #define WCD9335_CDC_RX0_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x049) |
| 454 | #define WCD9335_CDC_RX0_RX_PATH_SEC7 WCD9335_REG(0x0b, 0x050) |
| 455 | #define WCD9335_CDC_RX0_RX_PATH_MIX_SEC0 WCD9335_REG(0x0b, 0x051) |
| 456 | #define WCD9335_CDC_RX1_RX_PATH_CTL WCD9335_REG(0x0b, 0x055) |
| 457 | #define WCD9335_CDC_RX1_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x056) |
| 458 | #define WCD9335_CDC_RX1_RX_PATH_CFG(c) WCD9335_REG(0x0b, (0x056 + c * 0x14)) |
| 459 | #define WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK BIT(1) |
| 460 | #define WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE BIT(1) |
| 461 | #define WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE 0 |
| 462 | #define WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK BIT(2) |
| 463 | #define WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE BIT(2) |
| 464 | #define WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE 0 |
| 465 | #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK BIT(3) |
| 466 | #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN BIT(3) |
| 467 | #define WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_DISABLE 0 |
| 468 | #define WCD9335_CDC_RX1_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x058) |
| 469 | #define WCD9335_CDC_RX1_RX_VOL_CTL WCD9335_REG(0x0b, 0x059) |
| 470 | #define WCD9335_CDC_RX1_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x05a) |
| 471 | #define WCD9335_CDC_RX1_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x05b) |
| 472 | #define WCD9335_CDC_RX1_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x05c) |
| 473 | #define WCD9335_CDC_RX1_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x05d) |
| 474 | #define WCD9335_CDC_RX1_RX_PATH_SEC3 WCD9335_REG(0x0b, 0x060) |
| 475 | #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK GENMASK(1, 0) |
| 476 | #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2 0x1 |
| 477 | #define WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1 0 |
| 478 | #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK GENMASK(5, 2) |
| 479 | #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500 0x10 |
| 480 | #define WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000 0 |
| 481 | #define WCD9335_CDC_RX2_RX_PATH_CTL WCD9335_REG(0x0b, 0x069) |
| 482 | #define WCD9335_CDC_RX2_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x06a) |
| 483 | #define WCD9335_CDC_RX2_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x06c) |
| 484 | #define WCD9335_CDC_RX2_RX_VOL_CTL WCD9335_REG(0x0b, 0x06d) |
| 485 | #define WCD9335_CDC_RX2_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x06e) |
| 486 | #define WCD9335_CDC_RX2_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x06f) |
| 487 | #define WCD9335_CDC_RX2_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x070) |
| 488 | #define WCD9335_CDC_RX2_RX_PATH_SEC0 WCD9335_REG(0x0b, 0x071) |
| 489 | #define WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK GENMASK(1, 0) |
| 490 | #define WCD9335_CDC_RX2_RX_PATH_SEC3 WCD9335_REG(0x0b, 0x074) |
| 491 | #define WCD9335_CDC_RX3_RX_PATH_CTL WCD9335_REG(0x0b, 0x07d) |
| 492 | #define WCD9335_CDC_RX3_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x07e) |
| 493 | #define WCD9335_CDC_RX3_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x080) |
| 494 | #define WCD9335_CDC_RX3_RX_VOL_CTL WCD9335_REG(0x0b, 0x081) |
| 495 | #define WCD9335_CDC_RX3_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x082) |
| 496 | #define WCD9335_CDC_RX3_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x083) |
| 497 | #define WCD9335_CDC_RX3_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x084) |
| 498 | #define WCD9335_CDC_RX4_RX_PATH_CTL WCD9335_REG(0x0b, 0x091) |
| 499 | #define WCD9335_CDC_RX4_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x092) |
| 500 | #define WCD9335_CDC_RX4_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x094) |
| 501 | #define WCD9335_CDC_RX4_RX_VOL_CTL WCD9335_REG(0x0b, 0x095) |
| 502 | #define WCD9335_CDC_RX4_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x096) |
| 503 | #define WCD9335_CDC_RX4_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x097) |
| 504 | #define WCD9335_CDC_RX4_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x098) |
| 505 | #define WCD9335_CDC_RX5_RX_PATH_CTL WCD9335_REG(0x0b, 0x0a5) |
| 506 | #define WCD9335_CDC_RX5_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0a6) |
| 507 | #define WCD9335_CDC_RX5_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0a8) |
| 508 | #define WCD9335_CDC_RX5_RX_VOL_CTL WCD9335_REG(0x0b, 0x0a9) |
| 509 | #define WCD9335_CDC_RX5_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0aa) |
| 510 | #define WCD9335_CDC_RX5_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0ab) |
| 511 | #define WCD9335_CDC_RX5_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0ac) |
| 512 | #define WCD9335_CDC_RX6_RX_PATH_CTL WCD9335_REG(0x0b, 0x0b9) |
| 513 | #define WCD9335_CDC_RX6_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ba) |
| 514 | #define WCD9335_CDC_RX6_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0bc) |
| 515 | #define WCD9335_CDC_RX6_RX_VOL_CTL WCD9335_REG(0x0b, 0x0bd) |
| 516 | #define WCD9335_CDC_RX6_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0be) |
| 517 | #define WCD9335_CDC_RX6_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0bf) |
| 518 | #define WCD9335_CDC_RX6_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0c0) |
| 519 | #define WCD9335_CDC_RX7_RX_PATH_CTL WCD9335_REG(0x0b, 0x0cd) |
| 520 | #define WCD9335_CDC_RX7_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0ce) |
| 521 | #define WCD9335_CDC_RX7_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0cf) |
| 522 | #define WCD9335_CDC_RX7_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0d0) |
| 523 | #define WCD9335_CDC_RX7_RX_VOL_CTL WCD9335_REG(0x0b, 0x0d1) |
| 524 | #define WCD9335_CDC_RX7_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0d2) |
| 525 | #define WCD9335_CDC_RX7_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0d3) |
| 526 | #define WCD9335_CDC_RX7_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0d4) |
| 527 | #define WCD9335_CDC_RX8_RX_PATH_CTL WCD9335_REG(0x0b, 0x0e1) |
| 528 | #define WCD9335_CDC_RX8_RX_PATH_CFG0 WCD9335_REG(0x0b, 0x0e2) |
| 529 | #define WCD9335_CDC_RX8_RX_PATH_CFG1 WCD9335_REG(0x0b, 0x0e3) |
| 530 | #define WCD9335_CDC_RX8_RX_PATH_CFG2 WCD9335_REG(0x0b, 0x0e4) |
| 531 | #define WCD9335_CDC_RX8_RX_VOL_CTL WCD9335_REG(0x0b, 0x0e5) |
| 532 | #define WCD9335_CDC_RX8_RX_PATH_MIX_CTL WCD9335_REG(0x0b, 0x0e6) |
| 533 | #define WCD9335_CDC_RX8_RX_PATH_MIX_CFG WCD9335_REG(0x0b, 0x0e7) |
| 534 | #define WCD9335_CDC_RX8_RX_VOL_MIX_CTL WCD9335_REG(0x0b, 0x0e8) |
| 535 | |
| 536 | /* Page-12 Registers */ |
| 537 | #define WCD9335_PAGE12_PAGE_REGISTER WCD9335_REG(0x0c, 0x000) |
| 538 | #define WCD9335_CDC_CLSH_K2_MSB WCD9335_REG(0x0c, 0x00a) |
| 539 | #define WCD9335_CDC_CLSH_K2_LSB WCD9335_REG(0x0c, 0x00b) |
| 540 | #define WCD9335_CDC_BOOST0_BOOST_CTL WCD9335_REG(0x0c, 0x01a) |
| 541 | #define WCD9335_CDC_BOOST0_BOOST_CFG1 WCD9335_REG(0x0c, 0x01b) |
| 542 | #define WCD9335_CDC_BOOST0_BOOST_CFG2 WCD9335_REG(0x0c, 0x01c) |
| 543 | #define WCD9335_CDC_BOOST1_BOOST_CTL WCD9335_REG(0x0c, 0x022) |
| 544 | #define WCD9335_CDC_BOOST1_BOOST_CFG1 WCD9335_REG(0x0c, 0x023) |
| 545 | #define WCD9335_CDC_BOOST1_BOOST_CFG2 WCD9335_REG(0x0c, 0x024) |
| 546 | |
| 547 | /* Page-13 Registers */ |
| 548 | #define WCD9335_PAGE13_PAGE_REGISTER WCD9335_REG(0x0d, 0x000) |
| 549 | #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0 WCD9335_REG(0x0d, 0x001) |
| 550 | #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(i) WCD9335_REG(0xd, (0x1 + i * 0x2)) |
| 551 | #define WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1 WCD9335_REG(0xd, 0x002) |
| 552 | #define WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK GENMASK(3, 0) |
| 553 | #define WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(i) WCD9335_REG(0xd, (0x2 + i * 0x2)) |
| 554 | |
| 555 | #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0 WCD9335_REG(0x0d, 0x003) |
| 556 | #define WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1 WCD9335_REG(0x0d, 0x004) |
| 557 | #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0 WCD9335_REG(0x0d, 0x005) |
| 558 | #define WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1 WCD9335_REG(0x0d, 0x006) |
| 559 | #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0 WCD9335_REG(0x0d, 0x007) |
| 560 | #define WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1 WCD9335_REG(0x0d, 0x008) |
| 561 | #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0 WCD9335_REG(0x0d, 0x009) |
| 562 | #define WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1 WCD9335_REG(0x0d, 0x00a) |
| 563 | #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0 WCD9335_REG(0x0d, 0x00b) |
| 564 | #define WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1 WCD9335_REG(0x0d, 0x00c) |
| 565 | #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0 WCD9335_REG(0x0d, 0x00d) |
| 566 | #define WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1 WCD9335_REG(0x0d, 0x00e) |
| 567 | #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0 WCD9335_REG(0x0d, 0x00f) |
| 568 | #define WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1 WCD9335_REG(0x0d, 0x010) |
| 569 | #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0 WCD9335_REG(0x0d, 0x011) |
| 570 | #define WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1 WCD9335_REG(0x0d, 0x012) |
| 571 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 WCD9335_REG(0x0d, 0x01d) |
| 572 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 WCD9335_REG(0x0d, 0x01e) |
| 573 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0 WCD9335_REG(0x0d, 0x01f) |
| 574 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1 WCD9335_REG(0x0d, 0x020) |
| 575 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0 WCD9335_REG(0x0d, 0x021) |
| 576 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1 WCD9335_REG(0x0d, 0x022) |
| 577 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0 WCD9335_REG(0x0d, 0x023) |
| 578 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1 WCD9335_REG(0x0d, 0x024) |
| 579 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 WCD9335_REG(0x0d, 0x025) |
| 580 | #define WCD9335_CDC_TX_INP_MUX_SEL_AMIC 0x1 |
| 581 | #define WCD9335_CDC_TX_INP_MUX_SEL_DMIC 0 |
| 582 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0 WCD9335_REG(0x0d, 0x026) |
| 583 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0 WCD9335_REG(0x0d, 0x027) |
| 584 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0 WCD9335_REG(0x0d, 0x028) |
| 585 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0 WCD9335_REG(0x0d, 0x029) |
| 586 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0 WCD9335_REG(0x0d, 0x02b) |
| 587 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0 WCD9335_REG(0x0d, 0x02c) |
| 588 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0 WCD9335_REG(0x0d, 0x02d) |
| 589 | #define WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0 WCD9335_REG(0x0d, 0x02e) |
| 590 | #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0 WCD9335_REG(0x0d, 0x03a) |
| 591 | #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1 WCD9335_REG(0x0d, 0x03b) |
| 592 | #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2 WCD9335_REG(0x0d, 0x03c) |
| 593 | #define WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3 WCD9335_REG(0x0d, 0x03d) |
| 594 | #define WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL WCD9335_REG(0x0d, 0x041) |
| 595 | #define WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK BIT(0) |
| 596 | #define WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE BIT(0) |
| 597 | #define WCD9335_CDC_CLK_RST_CTRL_MCLK_DISABLE 0 |
| 598 | #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL WCD9335_REG(0x0d, 0x042) |
| 599 | #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK BIT(0) |
| 600 | #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE BIT(0) |
| 601 | #define WCD9335_CDC_CLK_RST_CTRL_FS_CNT_DISABLE 0 |
| 602 | #define WCD9335_CDC_TOP_TOP_CFG1 WCD9335_REG(0x0d, 0x082) |
| Srinivas Kandagatla | d902e78 | 2020-03-06 15:26:33 +0000 | [diff] [blame] | 603 | #define WCD9335_MAX_REGISTER 0xffff |
| 604 | #define WCD9335_SEL_REGISTER 0x800 |
| Srinivas Kandagatla | 20aedaf | 2019-01-28 14:27:47 +0000 | [diff] [blame] | 605 | |
| 606 | /* SLIMBUS Slave Registers */ |
| 607 | #define WCD9335_SLIM_PGD_PORT_INT_EN0 WCD9335_REG(0, 0x30) |
| 608 | #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0 WCD9335_REG(0, 0x34) |
| 609 | #define WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_1 WCD9335_REG(0, 0x35) |
| 610 | #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_0 WCD9335_REG(0, 0x36) |
| 611 | #define WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1 WCD9335_REG(0, 0x37) |
| 612 | #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 WCD9335_REG(0, 0x38) |
| 613 | #define WCD9335_SLIM_PGD_PORT_INT_CLR_RX_1 WCD9335_REG(0, 0x39) |
| 614 | #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_0 WCD9335_REG(0, 0x3A) |
| 615 | #define WCD9335_SLIM_PGD_PORT_INT_CLR_TX_1 WCD9335_REG(0, 0x3B) |
| 616 | #define WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 WCD9335_REG(0, 0x60) |
| 617 | #define WCD9335_SLIM_PGD_PORT_INT_TX_SOURCE0 WCD9335_REG(0, 0x70) |
| 618 | #define WCD9335_SLIM_PGD_RX_PORT_CFG(p) WCD9335_REG(0, (0x30 + p)) |
| 619 | #define WCD9335_SLIM_PGD_PORT_CFG(p) WCD9335_REG(0, (0x40 + p)) |
| 620 | #define WCD9335_SLIM_PGD_TX_PORT_CFG(p) WCD9335_REG(0, (0x50 + p)) |
| 621 | #define WCD9335_SLIM_PGD_PORT_INT_SRC(p) WCD9335_REG(0, (0x60 + p)) |
| 622 | #define WCD9335_SLIM_PGD_PORT_INT_STATUS(p) WCD9335_REG(0, (0x80 + p)) |
| 623 | #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x100 + 4 * p)) |
| 624 | /* ports range from 10-16 */ |
| 625 | #define WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(p) WCD9335_REG(0, (0x101 + 4 * p)) |
| 626 | #define WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(p) WCD9335_REG(0, (0x140 + 4 * p)) |
| 627 | |
| 628 | #define WCD9335_IRQ_SLIMBUS 0 |
| 629 | #define WCD9335_IRQ_MBHC_SW_DET 8 |
| 630 | #define WCD9335_IRQ_MBHC_ELECT_INS_REM_DET 9 |
| 631 | #define WCD9335_IRQ_MBHC_BUTTON_PRESS_DET 10 |
| 632 | #define WCD9335_IRQ_MBHC_BUTTON_RELEASE_DET 11 |
| 633 | #define WCD9335_IRQ_MBHC_ELECT_INS_REM_LEG_DET 12 |
| 634 | |
| 635 | #define SLIM_MANF_ID_QCOM 0x217 |
| 636 | #define SLIM_PROD_CODE_WCD9335 0x1a0 |
| 637 | |
| 638 | #define WCD9335_VERSION_2_0 2 |
| 639 | #define WCD9335_MAX_SUPPLY 5 |
| 640 | |
| 641 | #endif /* __WCD9335_H__ */ |