Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4 Clock data |
| 3 | * |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) |
| 8 | * Rajendra Nayak (rnayak@ti.com) |
| 9 | * Benoit Cousson (b-cousson@ti.com) |
| 10 | * |
| 11 | * This file is automatically generated from the OMAP hardware databases. |
| 12 | * We respectfully ask that any modifications to this file be coordinated |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 14 | * authors above to ensure that the autogeneration scripts are kept |
| 15 | * up-to-date with the file contents. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or modify |
| 18 | * it under the terms of the GNU General Public License version 2 as |
| 19 | * published by the Free Software Foundation. |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 20 | * |
| 21 | * XXX Some of the ES1 clocks have been removed/changed; once support |
| 22 | * is added for discriminating clocks by ES level, these should be added back |
| 23 | * in. |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #include <linux/kernel.h> |
Paul Walmsley | 93340a2 | 2010-02-22 22:09:12 -0700 | [diff] [blame] | 27 | #include <linux/list.h> |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 28 | #include <linux/clk.h> |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 29 | #include <plat/clkdev_omap.h> |
| 30 | |
| 31 | #include "clock.h" |
| 32 | #include "clock44xx.h" |
Paul Walmsley | d198b51 | 2010-12-21 15:30:54 -0700 | [diff] [blame] | 33 | #include "cm1_44xx.h" |
| 34 | #include "cm2_44xx.h" |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 35 | #include "cm-regbits-44xx.h" |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 36 | #include "prm44xx.h" |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 37 | #include "prm-regbits-44xx.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 38 | #include "control.h" |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 39 | #include "scrm44xx.h" |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 40 | |
Paul Walmsley | 59fb659 | 2010-12-21 15:30:55 -0700 | [diff] [blame] | 41 | /* OMAP4 modulemode control */ |
| 42 | #define OMAP4430_MODULEMODE_HWCTRL 0 |
| 43 | #define OMAP4430_MODULEMODE_SWCTRL 1 |
| 44 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 45 | /* Root clocks */ |
| 46 | |
| 47 | static struct clk extalt_clkin_ck = { |
| 48 | .name = "extalt_clkin_ck", |
| 49 | .rate = 59000000, |
| 50 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 51 | }; |
| 52 | |
| 53 | static struct clk pad_clks_ck = { |
| 54 | .name = "pad_clks_ck", |
| 55 | .rate = 12000000, |
Benoit Cousson | d9b98f5 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 56 | .ops = &clkops_omap2_dflt, |
| 57 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, |
| 58 | .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | static struct clk pad_slimbus_core_clks_ck = { |
| 62 | .name = "pad_slimbus_core_clks_ck", |
| 63 | .rate = 12000000, |
| 64 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 65 | }; |
| 66 | |
| 67 | static struct clk secure_32k_clk_src_ck = { |
| 68 | .name = "secure_32k_clk_src_ck", |
| 69 | .rate = 32768, |
| 70 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | static struct clk slimbus_clk = { |
| 74 | .name = "slimbus_clk", |
| 75 | .rate = 12000000, |
Benoit Cousson | d9b98f5 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 76 | .ops = &clkops_omap2_dflt, |
| 77 | .enable_reg = OMAP4430_CM_CLKSEL_ABE, |
| 78 | .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 79 | }; |
| 80 | |
| 81 | static struct clk sys_32k_ck = { |
| 82 | .name = "sys_32k_ck", |
| 83 | .rate = 32768, |
| 84 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | static struct clk virt_12000000_ck = { |
| 88 | .name = "virt_12000000_ck", |
| 89 | .ops = &clkops_null, |
| 90 | .rate = 12000000, |
| 91 | }; |
| 92 | |
| 93 | static struct clk virt_13000000_ck = { |
| 94 | .name = "virt_13000000_ck", |
| 95 | .ops = &clkops_null, |
| 96 | .rate = 13000000, |
| 97 | }; |
| 98 | |
| 99 | static struct clk virt_16800000_ck = { |
| 100 | .name = "virt_16800000_ck", |
| 101 | .ops = &clkops_null, |
| 102 | .rate = 16800000, |
| 103 | }; |
| 104 | |
| 105 | static struct clk virt_19200000_ck = { |
| 106 | .name = "virt_19200000_ck", |
| 107 | .ops = &clkops_null, |
| 108 | .rate = 19200000, |
| 109 | }; |
| 110 | |
| 111 | static struct clk virt_26000000_ck = { |
| 112 | .name = "virt_26000000_ck", |
| 113 | .ops = &clkops_null, |
| 114 | .rate = 26000000, |
| 115 | }; |
| 116 | |
| 117 | static struct clk virt_27000000_ck = { |
| 118 | .name = "virt_27000000_ck", |
| 119 | .ops = &clkops_null, |
| 120 | .rate = 27000000, |
| 121 | }; |
| 122 | |
| 123 | static struct clk virt_38400000_ck = { |
| 124 | .name = "virt_38400000_ck", |
| 125 | .ops = &clkops_null, |
| 126 | .rate = 38400000, |
| 127 | }; |
| 128 | |
| 129 | static const struct clksel_rate div_1_0_rates[] = { |
| 130 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 131 | { .div = 0 }, |
| 132 | }; |
| 133 | |
| 134 | static const struct clksel_rate div_1_1_rates[] = { |
| 135 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, |
| 136 | { .div = 0 }, |
| 137 | }; |
| 138 | |
| 139 | static const struct clksel_rate div_1_2_rates[] = { |
| 140 | { .div = 1, .val = 2, .flags = RATE_IN_4430 }, |
| 141 | { .div = 0 }, |
| 142 | }; |
| 143 | |
| 144 | static const struct clksel_rate div_1_3_rates[] = { |
| 145 | { .div = 1, .val = 3, .flags = RATE_IN_4430 }, |
| 146 | { .div = 0 }, |
| 147 | }; |
| 148 | |
| 149 | static const struct clksel_rate div_1_4_rates[] = { |
| 150 | { .div = 1, .val = 4, .flags = RATE_IN_4430 }, |
| 151 | { .div = 0 }, |
| 152 | }; |
| 153 | |
| 154 | static const struct clksel_rate div_1_5_rates[] = { |
| 155 | { .div = 1, .val = 5, .flags = RATE_IN_4430 }, |
| 156 | { .div = 0 }, |
| 157 | }; |
| 158 | |
| 159 | static const struct clksel_rate div_1_6_rates[] = { |
| 160 | { .div = 1, .val = 6, .flags = RATE_IN_4430 }, |
| 161 | { .div = 0 }, |
| 162 | }; |
| 163 | |
| 164 | static const struct clksel_rate div_1_7_rates[] = { |
| 165 | { .div = 1, .val = 7, .flags = RATE_IN_4430 }, |
| 166 | { .div = 0 }, |
| 167 | }; |
| 168 | |
| 169 | static const struct clksel sys_clkin_sel[] = { |
| 170 | { .parent = &virt_12000000_ck, .rates = div_1_1_rates }, |
| 171 | { .parent = &virt_13000000_ck, .rates = div_1_2_rates }, |
| 172 | { .parent = &virt_16800000_ck, .rates = div_1_3_rates }, |
| 173 | { .parent = &virt_19200000_ck, .rates = div_1_4_rates }, |
| 174 | { .parent = &virt_26000000_ck, .rates = div_1_5_rates }, |
| 175 | { .parent = &virt_27000000_ck, .rates = div_1_6_rates }, |
| 176 | { .parent = &virt_38400000_ck, .rates = div_1_7_rates }, |
| 177 | { .parent = NULL }, |
| 178 | }; |
| 179 | |
| 180 | static struct clk sys_clkin_ck = { |
| 181 | .name = "sys_clkin_ck", |
| 182 | .rate = 38400000, |
| 183 | .clksel = sys_clkin_sel, |
| 184 | .init = &omap2_init_clksel_parent, |
| 185 | .clksel_reg = OMAP4430_CM_SYS_CLKSEL, |
| 186 | .clksel_mask = OMAP4430_SYS_CLKSEL_MASK, |
| 187 | .ops = &clkops_null, |
| 188 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 189 | }; |
| 190 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 191 | static struct clk tie_low_clock_ck = { |
| 192 | .name = "tie_low_clock_ck", |
| 193 | .rate = 0, |
| 194 | .ops = &clkops_null, |
| 195 | }; |
| 196 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 197 | static struct clk utmi_phy_clkout_ck = { |
| 198 | .name = "utmi_phy_clkout_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 199 | .rate = 60000000, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 200 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 201 | }; |
| 202 | |
| 203 | static struct clk xclk60mhsp1_ck = { |
| 204 | .name = "xclk60mhsp1_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 205 | .rate = 60000000, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 206 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 207 | }; |
| 208 | |
| 209 | static struct clk xclk60mhsp2_ck = { |
| 210 | .name = "xclk60mhsp2_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 211 | .rate = 60000000, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 212 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 213 | }; |
| 214 | |
| 215 | static struct clk xclk60motg_ck = { |
| 216 | .name = "xclk60motg_ck", |
| 217 | .rate = 60000000, |
| 218 | .ops = &clkops_null, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 219 | }; |
| 220 | |
| 221 | /* Module clocks and DPLL outputs */ |
| 222 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 223 | static const struct clksel abe_dpll_bypass_clk_mux_sel[] = { |
| 224 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 225 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, |
| 226 | { .parent = NULL }, |
| 227 | }; |
| 228 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 229 | static struct clk abe_dpll_bypass_clk_mux_ck = { |
| 230 | .name = "abe_dpll_bypass_clk_mux_ck", |
| 231 | .parent = &sys_clkin_ck, |
| 232 | .ops = &clkops_null, |
| 233 | .recalc = &followparent_recalc, |
| 234 | }; |
| 235 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 236 | static struct clk abe_dpll_refclk_mux_ck = { |
| 237 | .name = "abe_dpll_refclk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 238 | .parent = &sys_clkin_ck, |
| 239 | .clksel = abe_dpll_bypass_clk_mux_sel, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 240 | .init = &omap2_init_clksel_parent, |
| 241 | .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, |
| 242 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 243 | .ops = &clkops_null, |
| 244 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 245 | }; |
| 246 | |
| 247 | /* DPLL_ABE */ |
| 248 | static struct dpll_data dpll_abe_dd = { |
| 249 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 250 | .clk_bypass = &abe_dpll_bypass_clk_mux_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 251 | .clk_ref = &abe_dpll_refclk_mux_ck, |
| 252 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, |
| 253 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 254 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE, |
| 255 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE, |
| 256 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 257 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 258 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 259 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 260 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
| 261 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 262 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 263 | .min_divider = 1, |
| 264 | }; |
| 265 | |
| 266 | |
| 267 | static struct clk dpll_abe_ck = { |
| 268 | .name = "dpll_abe_ck", |
| 269 | .parent = &abe_dpll_refclk_mux_ck, |
| 270 | .dpll_data = &dpll_abe_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 271 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 272 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 273 | .recalc = &omap3_dpll_recalc, |
| 274 | .round_rate = &omap2_dpll_round_rate, |
| 275 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 276 | }; |
| 277 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 278 | static struct clk dpll_abe_x2_ck = { |
| 279 | .name = "dpll_abe_x2_ck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 280 | .parent = &dpll_abe_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 281 | .flags = CLOCK_CLKOUTX2, |
| 282 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 283 | .recalc = &omap3_clkoutx2_recalc, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 284 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 285 | }; |
| 286 | |
| 287 | static const struct clksel_rate div31_1to31_rates[] = { |
| 288 | { .div = 1, .val = 1, .flags = RATE_IN_4430 }, |
| 289 | { .div = 2, .val = 2, .flags = RATE_IN_4430 }, |
| 290 | { .div = 3, .val = 3, .flags = RATE_IN_4430 }, |
| 291 | { .div = 4, .val = 4, .flags = RATE_IN_4430 }, |
| 292 | { .div = 5, .val = 5, .flags = RATE_IN_4430 }, |
| 293 | { .div = 6, .val = 6, .flags = RATE_IN_4430 }, |
| 294 | { .div = 7, .val = 7, .flags = RATE_IN_4430 }, |
| 295 | { .div = 8, .val = 8, .flags = RATE_IN_4430 }, |
| 296 | { .div = 9, .val = 9, .flags = RATE_IN_4430 }, |
| 297 | { .div = 10, .val = 10, .flags = RATE_IN_4430 }, |
| 298 | { .div = 11, .val = 11, .flags = RATE_IN_4430 }, |
| 299 | { .div = 12, .val = 12, .flags = RATE_IN_4430 }, |
| 300 | { .div = 13, .val = 13, .flags = RATE_IN_4430 }, |
| 301 | { .div = 14, .val = 14, .flags = RATE_IN_4430 }, |
| 302 | { .div = 15, .val = 15, .flags = RATE_IN_4430 }, |
| 303 | { .div = 16, .val = 16, .flags = RATE_IN_4430 }, |
| 304 | { .div = 17, .val = 17, .flags = RATE_IN_4430 }, |
| 305 | { .div = 18, .val = 18, .flags = RATE_IN_4430 }, |
| 306 | { .div = 19, .val = 19, .flags = RATE_IN_4430 }, |
| 307 | { .div = 20, .val = 20, .flags = RATE_IN_4430 }, |
| 308 | { .div = 21, .val = 21, .flags = RATE_IN_4430 }, |
| 309 | { .div = 22, .val = 22, .flags = RATE_IN_4430 }, |
| 310 | { .div = 23, .val = 23, .flags = RATE_IN_4430 }, |
| 311 | { .div = 24, .val = 24, .flags = RATE_IN_4430 }, |
| 312 | { .div = 25, .val = 25, .flags = RATE_IN_4430 }, |
| 313 | { .div = 26, .val = 26, .flags = RATE_IN_4430 }, |
| 314 | { .div = 27, .val = 27, .flags = RATE_IN_4430 }, |
| 315 | { .div = 28, .val = 28, .flags = RATE_IN_4430 }, |
| 316 | { .div = 29, .val = 29, .flags = RATE_IN_4430 }, |
| 317 | { .div = 30, .val = 30, .flags = RATE_IN_4430 }, |
| 318 | { .div = 31, .val = 31, .flags = RATE_IN_4430 }, |
| 319 | { .div = 0 }, |
| 320 | }; |
| 321 | |
| 322 | static const struct clksel dpll_abe_m2x2_div[] = { |
| 323 | { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates }, |
| 324 | { .parent = NULL }, |
| 325 | }; |
| 326 | |
| 327 | static struct clk dpll_abe_m2x2_ck = { |
| 328 | .name = "dpll_abe_m2x2_ck", |
| 329 | .parent = &dpll_abe_x2_ck, |
| 330 | .clksel = dpll_abe_m2x2_div, |
| 331 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
| 332 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 333 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 334 | .recalc = &omap2_clksel_recalc, |
| 335 | .round_rate = &omap2_clksel_round_rate, |
| 336 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 337 | }; |
| 338 | |
| 339 | static struct clk abe_24m_fclk = { |
| 340 | .name = "abe_24m_fclk", |
| 341 | .parent = &dpll_abe_m2x2_ck, |
| 342 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 343 | .fixed_div = 8, |
| 344 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 345 | }; |
| 346 | |
| 347 | static const struct clksel_rate div3_1to4_rates[] = { |
| 348 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 349 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, |
| 350 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, |
| 351 | { .div = 0 }, |
| 352 | }; |
| 353 | |
| 354 | static const struct clksel abe_clk_div[] = { |
| 355 | { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates }, |
| 356 | { .parent = NULL }, |
| 357 | }; |
| 358 | |
| 359 | static struct clk abe_clk = { |
| 360 | .name = "abe_clk", |
| 361 | .parent = &dpll_abe_m2x2_ck, |
| 362 | .clksel = abe_clk_div, |
| 363 | .clksel_reg = OMAP4430_CM_CLKSEL_ABE, |
| 364 | .clksel_mask = OMAP4430_CLKSEL_OPP_MASK, |
| 365 | .ops = &clkops_null, |
| 366 | .recalc = &omap2_clksel_recalc, |
| 367 | .round_rate = &omap2_clksel_round_rate, |
| 368 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 369 | }; |
| 370 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 371 | static const struct clksel_rate div2_1to2_rates[] = { |
| 372 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 373 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, |
| 374 | { .div = 0 }, |
| 375 | }; |
| 376 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 377 | static const struct clksel aess_fclk_div[] = { |
| 378 | { .parent = &abe_clk, .rates = div2_1to2_rates }, |
| 379 | { .parent = NULL }, |
| 380 | }; |
| 381 | |
| 382 | static struct clk aess_fclk = { |
| 383 | .name = "aess_fclk", |
| 384 | .parent = &abe_clk, |
| 385 | .clksel = aess_fclk_div, |
| 386 | .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
| 387 | .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK, |
| 388 | .ops = &clkops_null, |
| 389 | .recalc = &omap2_clksel_recalc, |
| 390 | .round_rate = &omap2_clksel_round_rate, |
| 391 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 392 | }; |
| 393 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 394 | static struct clk dpll_abe_m3x2_ck = { |
| 395 | .name = "dpll_abe_m3x2_ck", |
| 396 | .parent = &dpll_abe_x2_ck, |
| 397 | .clksel = dpll_abe_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 398 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE, |
| 399 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 400 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 401 | .recalc = &omap2_clksel_recalc, |
| 402 | .round_rate = &omap2_clksel_round_rate, |
| 403 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 404 | }; |
| 405 | |
| 406 | static const struct clksel core_hsd_byp_clk_mux_sel[] = { |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 407 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 408 | { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 409 | { .parent = NULL }, |
| 410 | }; |
| 411 | |
| 412 | static struct clk core_hsd_byp_clk_mux_ck = { |
| 413 | .name = "core_hsd_byp_clk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 414 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 415 | .clksel = core_hsd_byp_clk_mux_sel, |
| 416 | .init = &omap2_init_clksel_parent, |
| 417 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, |
| 418 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
| 419 | .ops = &clkops_null, |
| 420 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 421 | }; |
| 422 | |
| 423 | /* DPLL_CORE */ |
| 424 | static struct dpll_data dpll_core_dd = { |
| 425 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, |
| 426 | .clk_bypass = &core_hsd_byp_clk_mux_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 427 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 428 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, |
| 429 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 430 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, |
| 431 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE, |
| 432 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 433 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 434 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 435 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 436 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
| 437 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 438 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 439 | .min_divider = 1, |
| 440 | }; |
| 441 | |
| 442 | |
| 443 | static struct clk dpll_core_ck = { |
| 444 | .name = "dpll_core_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 445 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 446 | .dpll_data = &dpll_core_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 447 | .init = &omap2_init_dpll_parent, |
Rajendra Nayak | 6c6f5a7 | 2011-02-25 15:49:00 -0700 | [diff] [blame] | 448 | .ops = &clkops_omap3_core_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 449 | .recalc = &omap3_dpll_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 450 | }; |
| 451 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 452 | static struct clk dpll_core_x2_ck = { |
| 453 | .name = "dpll_core_x2_ck", |
| 454 | .parent = &dpll_core_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 455 | .flags = CLOCK_CLKOUTX2, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 456 | .ops = &clkops_null, |
| 457 | .recalc = &omap3_clkoutx2_recalc, |
| 458 | }; |
| 459 | |
| 460 | static const struct clksel dpll_core_m6x2_div[] = { |
| 461 | { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 462 | { .parent = NULL }, |
| 463 | }; |
| 464 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 465 | static struct clk dpll_core_m6x2_ck = { |
| 466 | .name = "dpll_core_m6x2_ck", |
| 467 | .parent = &dpll_core_x2_ck, |
| 468 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 469 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE, |
| 470 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 471 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 472 | .recalc = &omap2_clksel_recalc, |
| 473 | .round_rate = &omap2_clksel_round_rate, |
| 474 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 475 | }; |
| 476 | |
| 477 | static const struct clksel dbgclk_mux_sel[] = { |
| 478 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 479 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 480 | { .parent = NULL }, |
| 481 | }; |
| 482 | |
| 483 | static struct clk dbgclk_mux_ck = { |
| 484 | .name = "dbgclk_mux_ck", |
| 485 | .parent = &sys_clkin_ck, |
| 486 | .ops = &clkops_null, |
| 487 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 488 | }; |
| 489 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 490 | static const struct clksel dpll_core_m2_div[] = { |
| 491 | { .parent = &dpll_core_ck, .rates = div31_1to31_rates }, |
| 492 | { .parent = NULL }, |
| 493 | }; |
| 494 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 495 | static struct clk dpll_core_m2_ck = { |
| 496 | .name = "dpll_core_m2_ck", |
| 497 | .parent = &dpll_core_ck, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 498 | .clksel = dpll_core_m2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 499 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE, |
| 500 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 501 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 502 | .recalc = &omap2_clksel_recalc, |
| 503 | .round_rate = &omap2_clksel_round_rate, |
| 504 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 505 | }; |
| 506 | |
| 507 | static struct clk ddrphy_ck = { |
| 508 | .name = "ddrphy_ck", |
| 509 | .parent = &dpll_core_m2_ck, |
| 510 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 511 | .fixed_div = 2, |
| 512 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 513 | }; |
| 514 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 515 | static struct clk dpll_core_m5x2_ck = { |
| 516 | .name = "dpll_core_m5x2_ck", |
| 517 | .parent = &dpll_core_x2_ck, |
| 518 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 519 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE, |
| 520 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 521 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 522 | .recalc = &omap2_clksel_recalc, |
| 523 | .round_rate = &omap2_clksel_round_rate, |
| 524 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 525 | }; |
| 526 | |
| 527 | static const struct clksel div_core_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 528 | { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 529 | { .parent = NULL }, |
| 530 | }; |
| 531 | |
| 532 | static struct clk div_core_ck = { |
| 533 | .name = "div_core_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 534 | .parent = &dpll_core_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 535 | .clksel = div_core_div, |
| 536 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, |
| 537 | .clksel_mask = OMAP4430_CLKSEL_CORE_MASK, |
| 538 | .ops = &clkops_null, |
| 539 | .recalc = &omap2_clksel_recalc, |
| 540 | .round_rate = &omap2_clksel_round_rate, |
| 541 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 542 | }; |
| 543 | |
| 544 | static const struct clksel_rate div4_1to8_rates[] = { |
| 545 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 546 | { .div = 2, .val = 1, .flags = RATE_IN_4430 }, |
| 547 | { .div = 4, .val = 2, .flags = RATE_IN_4430 }, |
| 548 | { .div = 8, .val = 3, .flags = RATE_IN_4430 }, |
| 549 | { .div = 0 }, |
| 550 | }; |
| 551 | |
| 552 | static const struct clksel div_iva_hs_clk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 553 | { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 554 | { .parent = NULL }, |
| 555 | }; |
| 556 | |
| 557 | static struct clk div_iva_hs_clk = { |
| 558 | .name = "div_iva_hs_clk", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 559 | .parent = &dpll_core_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 560 | .clksel = div_iva_hs_clk_div, |
| 561 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA, |
| 562 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, |
| 563 | .ops = &clkops_null, |
| 564 | .recalc = &omap2_clksel_recalc, |
| 565 | .round_rate = &omap2_clksel_round_rate, |
| 566 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 567 | }; |
| 568 | |
| 569 | static struct clk div_mpu_hs_clk = { |
| 570 | .name = "div_mpu_hs_clk", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 571 | .parent = &dpll_core_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 572 | .clksel = div_iva_hs_clk_div, |
| 573 | .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU, |
| 574 | .clksel_mask = OMAP4430_CLKSEL_0_1_MASK, |
| 575 | .ops = &clkops_null, |
| 576 | .recalc = &omap2_clksel_recalc, |
| 577 | .round_rate = &omap2_clksel_round_rate, |
| 578 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 579 | }; |
| 580 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 581 | static struct clk dpll_core_m4x2_ck = { |
| 582 | .name = "dpll_core_m4x2_ck", |
| 583 | .parent = &dpll_core_x2_ck, |
| 584 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 585 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE, |
| 586 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 587 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 588 | .recalc = &omap2_clksel_recalc, |
| 589 | .round_rate = &omap2_clksel_round_rate, |
| 590 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 591 | }; |
| 592 | |
| 593 | static struct clk dll_clk_div_ck = { |
| 594 | .name = "dll_clk_div_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 595 | .parent = &dpll_core_m4x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 596 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 597 | .fixed_div = 2, |
| 598 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 599 | }; |
| 600 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 601 | static const struct clksel dpll_abe_m2_div[] = { |
| 602 | { .parent = &dpll_abe_ck, .rates = div31_1to31_rates }, |
| 603 | { .parent = NULL }, |
| 604 | }; |
| 605 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 606 | static struct clk dpll_abe_m2_ck = { |
| 607 | .name = "dpll_abe_m2_ck", |
| 608 | .parent = &dpll_abe_ck, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 609 | .clksel = dpll_abe_m2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 610 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE, |
| 611 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 612 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 613 | .recalc = &omap2_clksel_recalc, |
| 614 | .round_rate = &omap2_clksel_round_rate, |
| 615 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 616 | }; |
| 617 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 618 | static struct clk dpll_core_m3x2_ck = { |
| 619 | .name = "dpll_core_m3x2_ck", |
| 620 | .parent = &dpll_core_x2_ck, |
| 621 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 622 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
| 623 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
Rajendra Nayak | cb13459 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 624 | .ops = &clkops_omap2_dflt, |
| 625 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE, |
| 626 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 627 | .recalc = &omap2_clksel_recalc, |
| 628 | .round_rate = &omap2_clksel_round_rate, |
| 629 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 630 | }; |
| 631 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 632 | static struct clk dpll_core_m7x2_ck = { |
| 633 | .name = "dpll_core_m7x2_ck", |
| 634 | .parent = &dpll_core_x2_ck, |
| 635 | .clksel = dpll_core_m6x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 636 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE, |
| 637 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 638 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 639 | .recalc = &omap2_clksel_recalc, |
| 640 | .round_rate = &omap2_clksel_round_rate, |
| 641 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 642 | }; |
| 643 | |
| 644 | static const struct clksel iva_hsd_byp_clk_mux_sel[] = { |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 645 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 646 | { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, |
| 647 | { .parent = NULL }, |
| 648 | }; |
| 649 | |
| 650 | static struct clk iva_hsd_byp_clk_mux_ck = { |
| 651 | .name = "iva_hsd_byp_clk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 652 | .parent = &sys_clkin_ck, |
Jonathan Bergsagel | 768ab94 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 653 | .clksel = iva_hsd_byp_clk_mux_sel, |
| 654 | .init = &omap2_init_clksel_parent, |
| 655 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, |
| 656 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 657 | .ops = &clkops_null, |
Jonathan Bergsagel | 768ab94 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 658 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 659 | }; |
| 660 | |
| 661 | /* DPLL_IVA */ |
| 662 | static struct dpll_data dpll_iva_dd = { |
| 663 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, |
| 664 | .clk_bypass = &iva_hsd_byp_clk_mux_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 665 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 666 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, |
| 667 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 668 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, |
| 669 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA, |
| 670 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 671 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 672 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 673 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 674 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
| 675 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 676 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 677 | .min_divider = 1, |
| 678 | }; |
| 679 | |
| 680 | |
| 681 | static struct clk dpll_iva_ck = { |
| 682 | .name = "dpll_iva_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 683 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 684 | .dpll_data = &dpll_iva_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 685 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 686 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 687 | .recalc = &omap3_dpll_recalc, |
| 688 | .round_rate = &omap2_dpll_round_rate, |
| 689 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 690 | }; |
| 691 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 692 | static struct clk dpll_iva_x2_ck = { |
| 693 | .name = "dpll_iva_x2_ck", |
| 694 | .parent = &dpll_iva_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 695 | .flags = CLOCK_CLKOUTX2, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 696 | .ops = &clkops_null, |
| 697 | .recalc = &omap3_clkoutx2_recalc, |
| 698 | }; |
| 699 | |
| 700 | static const struct clksel dpll_iva_m4x2_div[] = { |
| 701 | { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 702 | { .parent = NULL }, |
| 703 | }; |
| 704 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 705 | static struct clk dpll_iva_m4x2_ck = { |
| 706 | .name = "dpll_iva_m4x2_ck", |
| 707 | .parent = &dpll_iva_x2_ck, |
| 708 | .clksel = dpll_iva_m4x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 709 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA, |
| 710 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 711 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 712 | .recalc = &omap2_clksel_recalc, |
| 713 | .round_rate = &omap2_clksel_round_rate, |
| 714 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 715 | }; |
| 716 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 717 | static struct clk dpll_iva_m5x2_ck = { |
| 718 | .name = "dpll_iva_m5x2_ck", |
| 719 | .parent = &dpll_iva_x2_ck, |
| 720 | .clksel = dpll_iva_m4x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 721 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA, |
| 722 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 723 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 724 | .recalc = &omap2_clksel_recalc, |
| 725 | .round_rate = &omap2_clksel_round_rate, |
| 726 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 727 | }; |
| 728 | |
| 729 | /* DPLL_MPU */ |
| 730 | static struct dpll_data dpll_mpu_dd = { |
| 731 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, |
| 732 | .clk_bypass = &div_mpu_hs_clk, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 733 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 734 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, |
| 735 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 736 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, |
| 737 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU, |
| 738 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 739 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 740 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 741 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 742 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
| 743 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 744 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 745 | .min_divider = 1, |
| 746 | }; |
| 747 | |
| 748 | |
| 749 | static struct clk dpll_mpu_ck = { |
| 750 | .name = "dpll_mpu_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 751 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 752 | .dpll_data = &dpll_mpu_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 753 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 754 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 755 | .recalc = &omap3_dpll_recalc, |
| 756 | .round_rate = &omap2_dpll_round_rate, |
| 757 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 758 | }; |
| 759 | |
| 760 | static const struct clksel dpll_mpu_m2_div[] = { |
| 761 | { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates }, |
| 762 | { .parent = NULL }, |
| 763 | }; |
| 764 | |
| 765 | static struct clk dpll_mpu_m2_ck = { |
| 766 | .name = "dpll_mpu_m2_ck", |
| 767 | .parent = &dpll_mpu_ck, |
| 768 | .clksel = dpll_mpu_m2_div, |
| 769 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU, |
| 770 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 771 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 772 | .recalc = &omap2_clksel_recalc, |
| 773 | .round_rate = &omap2_clksel_round_rate, |
| 774 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 775 | }; |
| 776 | |
| 777 | static struct clk per_hs_clk_div_ck = { |
| 778 | .name = "per_hs_clk_div_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 779 | .parent = &dpll_abe_m3x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 780 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 781 | .fixed_div = 2, |
| 782 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 783 | }; |
| 784 | |
| 785 | static const struct clksel per_hsd_byp_clk_mux_sel[] = { |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 786 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 787 | { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, |
| 788 | { .parent = NULL }, |
| 789 | }; |
| 790 | |
| 791 | static struct clk per_hsd_byp_clk_mux_ck = { |
| 792 | .name = "per_hsd_byp_clk_mux_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 793 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 794 | .clksel = per_hsd_byp_clk_mux_sel, |
| 795 | .init = &omap2_init_clksel_parent, |
| 796 | .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, |
| 797 | .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK, |
| 798 | .ops = &clkops_null, |
| 799 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 800 | }; |
| 801 | |
| 802 | /* DPLL_PER */ |
| 803 | static struct dpll_data dpll_per_dd = { |
| 804 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, |
| 805 | .clk_bypass = &per_hsd_byp_clk_mux_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 806 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 807 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, |
| 808 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 809 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, |
| 810 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER, |
| 811 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 812 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 813 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 814 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 815 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
| 816 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 817 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 818 | .min_divider = 1, |
| 819 | }; |
| 820 | |
| 821 | |
| 822 | static struct clk dpll_per_ck = { |
| 823 | .name = "dpll_per_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 824 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 825 | .dpll_data = &dpll_per_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 826 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 827 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 828 | .recalc = &omap3_dpll_recalc, |
| 829 | .round_rate = &omap2_dpll_round_rate, |
| 830 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 831 | }; |
| 832 | |
| 833 | static const struct clksel dpll_per_m2_div[] = { |
| 834 | { .parent = &dpll_per_ck, .rates = div31_1to31_rates }, |
| 835 | { .parent = NULL }, |
| 836 | }; |
| 837 | |
| 838 | static struct clk dpll_per_m2_ck = { |
| 839 | .name = "dpll_per_m2_ck", |
| 840 | .parent = &dpll_per_ck, |
| 841 | .clksel = dpll_per_m2_div, |
| 842 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, |
| 843 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 844 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 845 | .recalc = &omap2_clksel_recalc, |
| 846 | .round_rate = &omap2_clksel_round_rate, |
| 847 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 848 | }; |
| 849 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 850 | static struct clk dpll_per_x2_ck = { |
| 851 | .name = "dpll_per_x2_ck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 852 | .parent = &dpll_per_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 853 | .flags = CLOCK_CLKOUTX2, |
| 854 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 855 | .recalc = &omap3_clkoutx2_recalc, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 856 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 857 | }; |
| 858 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 859 | static const struct clksel dpll_per_m2x2_div[] = { |
| 860 | { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates }, |
| 861 | { .parent = NULL }, |
| 862 | }; |
| 863 | |
| 864 | static struct clk dpll_per_m2x2_ck = { |
| 865 | .name = "dpll_per_m2x2_ck", |
| 866 | .parent = &dpll_per_x2_ck, |
| 867 | .clksel = dpll_per_m2x2_div, |
| 868 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER, |
| 869 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 870 | .ops = &clkops_omap4_dpllmx_ops, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 871 | .recalc = &omap2_clksel_recalc, |
| 872 | .round_rate = &omap2_clksel_round_rate, |
| 873 | .set_rate = &omap2_clksel_set_rate, |
| 874 | }; |
| 875 | |
| 876 | static struct clk dpll_per_m3x2_ck = { |
| 877 | .name = "dpll_per_m3x2_ck", |
| 878 | .parent = &dpll_per_x2_ck, |
| 879 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 880 | .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
| 881 | .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK, |
Rajendra Nayak | cb13459 | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 882 | .ops = &clkops_omap2_dflt, |
| 883 | .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER, |
| 884 | .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 885 | .recalc = &omap2_clksel_recalc, |
| 886 | .round_rate = &omap2_clksel_round_rate, |
| 887 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 888 | }; |
| 889 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 890 | static struct clk dpll_per_m4x2_ck = { |
| 891 | .name = "dpll_per_m4x2_ck", |
| 892 | .parent = &dpll_per_x2_ck, |
| 893 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 894 | .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER, |
| 895 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 896 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 897 | .recalc = &omap2_clksel_recalc, |
| 898 | .round_rate = &omap2_clksel_round_rate, |
| 899 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 900 | }; |
| 901 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 902 | static struct clk dpll_per_m5x2_ck = { |
| 903 | .name = "dpll_per_m5x2_ck", |
| 904 | .parent = &dpll_per_x2_ck, |
| 905 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 906 | .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER, |
| 907 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 908 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 909 | .recalc = &omap2_clksel_recalc, |
| 910 | .round_rate = &omap2_clksel_round_rate, |
| 911 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 912 | }; |
| 913 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 914 | static struct clk dpll_per_m6x2_ck = { |
| 915 | .name = "dpll_per_m6x2_ck", |
| 916 | .parent = &dpll_per_x2_ck, |
| 917 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 918 | .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER, |
| 919 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 920 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 921 | .recalc = &omap2_clksel_recalc, |
| 922 | .round_rate = &omap2_clksel_round_rate, |
| 923 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 924 | }; |
| 925 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 926 | static struct clk dpll_per_m7x2_ck = { |
| 927 | .name = "dpll_per_m7x2_ck", |
| 928 | .parent = &dpll_per_x2_ck, |
| 929 | .clksel = dpll_per_m2x2_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 930 | .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER, |
| 931 | .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 932 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 933 | .recalc = &omap2_clksel_recalc, |
| 934 | .round_rate = &omap2_clksel_round_rate, |
| 935 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 936 | }; |
| 937 | |
| 938 | /* DPLL_UNIPRO */ |
| 939 | static struct dpll_data dpll_unipro_dd = { |
| 940 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 941 | .clk_bypass = &sys_clkin_ck, |
| 942 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 943 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, |
| 944 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 945 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, |
| 946 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO, |
| 947 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 948 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 949 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 950 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 951 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 952 | .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 953 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 954 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 955 | .min_divider = 1, |
| 956 | }; |
| 957 | |
| 958 | |
| 959 | static struct clk dpll_unipro_ck = { |
| 960 | .name = "dpll_unipro_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 961 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 962 | .dpll_data = &dpll_unipro_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 963 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 964 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 965 | .recalc = &omap3_dpll_recalc, |
| 966 | .round_rate = &omap2_dpll_round_rate, |
| 967 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 968 | }; |
| 969 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 970 | static struct clk dpll_unipro_x2_ck = { |
| 971 | .name = "dpll_unipro_x2_ck", |
| 972 | .parent = &dpll_unipro_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 973 | .flags = CLOCK_CLKOUTX2, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 974 | .ops = &clkops_null, |
| 975 | .recalc = &omap3_clkoutx2_recalc, |
| 976 | }; |
| 977 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 978 | static const struct clksel dpll_unipro_m2x2_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 979 | { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 980 | { .parent = NULL }, |
| 981 | }; |
| 982 | |
| 983 | static struct clk dpll_unipro_m2x2_ck = { |
| 984 | .name = "dpll_unipro_m2x2_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 985 | .parent = &dpll_unipro_x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 986 | .clksel = dpll_unipro_m2x2_div, |
| 987 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO, |
| 988 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 989 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 990 | .recalc = &omap2_clksel_recalc, |
| 991 | .round_rate = &omap2_clksel_round_rate, |
| 992 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 993 | }; |
| 994 | |
| 995 | static struct clk usb_hs_clk_div_ck = { |
| 996 | .name = "usb_hs_clk_div_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 997 | .parent = &dpll_abe_m3x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 998 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 999 | .fixed_div = 3, |
| 1000 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1001 | }; |
| 1002 | |
| 1003 | /* DPLL_USB */ |
| 1004 | static struct dpll_data dpll_usb_dd = { |
| 1005 | .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, |
| 1006 | .clk_bypass = &usb_hs_clk_div_ck, |
Jon Hunter | a36795c | 2010-12-21 21:31:43 -0700 | [diff] [blame] | 1007 | .flags = DPLL_J_TYPE, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1008 | .clk_ref = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1009 | .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, |
| 1010 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| 1011 | .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, |
| 1012 | .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB, |
| 1013 | .mult_mask = OMAP4430_DPLL_MULT_MASK, |
| 1014 | .div1_mask = OMAP4430_DPLL_DIV_MASK, |
| 1015 | .enable_mask = OMAP4430_DPLL_EN_MASK, |
| 1016 | .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK, |
| 1017 | .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK, |
| 1018 | .max_multiplier = OMAP4430_MAX_DPLL_MULT, |
| 1019 | .max_divider = OMAP4430_MAX_DPLL_DIV, |
| 1020 | .min_divider = 1, |
| 1021 | }; |
| 1022 | |
| 1023 | |
| 1024 | static struct clk dpll_usb_ck = { |
| 1025 | .name = "dpll_usb_ck", |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1026 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1027 | .dpll_data = &dpll_usb_dd, |
Rajendra Nayak | 911bd73 | 2009-12-08 18:47:17 -0700 | [diff] [blame] | 1028 | .init = &omap2_init_dpll_parent, |
Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 1029 | .ops = &clkops_omap3_noncore_dpll_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1030 | .recalc = &omap3_dpll_recalc, |
| 1031 | .round_rate = &omap2_dpll_round_rate, |
| 1032 | .set_rate = &omap3_noncore_dpll_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1033 | }; |
| 1034 | |
| 1035 | static struct clk dpll_usb_clkdcoldo_ck = { |
| 1036 | .name = "dpll_usb_clkdcoldo_ck", |
| 1037 | .parent = &dpll_usb_ck, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 1038 | .ops = &clkops_omap4_dpllmx_ops, |
| 1039 | .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1040 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1041 | }; |
| 1042 | |
| 1043 | static const struct clksel dpll_usb_m2_div[] = { |
| 1044 | { .parent = &dpll_usb_ck, .rates = div31_1to31_rates }, |
| 1045 | { .parent = NULL }, |
| 1046 | }; |
| 1047 | |
| 1048 | static struct clk dpll_usb_m2_ck = { |
| 1049 | .name = "dpll_usb_m2_ck", |
| 1050 | .parent = &dpll_usb_ck, |
| 1051 | .clksel = dpll_usb_m2_div, |
| 1052 | .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB, |
| 1053 | .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK, |
Rajendra Nayak | 70db8a6 | 2011-02-25 15:49:02 -0700 | [diff] [blame] | 1054 | .ops = &clkops_omap4_dpllmx_ops, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1055 | .recalc = &omap2_clksel_recalc, |
| 1056 | .round_rate = &omap2_clksel_round_rate, |
| 1057 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1058 | }; |
| 1059 | |
| 1060 | static const struct clksel ducati_clk_mux_sel[] = { |
| 1061 | { .parent = &div_core_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1062 | { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1063 | { .parent = NULL }, |
| 1064 | }; |
| 1065 | |
| 1066 | static struct clk ducati_clk_mux_ck = { |
| 1067 | .name = "ducati_clk_mux_ck", |
| 1068 | .parent = &div_core_ck, |
| 1069 | .clksel = ducati_clk_mux_sel, |
| 1070 | .init = &omap2_init_clksel_parent, |
| 1071 | .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, |
| 1072 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1073 | .ops = &clkops_null, |
| 1074 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1075 | }; |
| 1076 | |
| 1077 | static struct clk func_12m_fclk = { |
| 1078 | .name = "func_12m_fclk", |
| 1079 | .parent = &dpll_per_m2x2_ck, |
| 1080 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1081 | .fixed_div = 16, |
| 1082 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1083 | }; |
| 1084 | |
| 1085 | static struct clk func_24m_clk = { |
| 1086 | .name = "func_24m_clk", |
| 1087 | .parent = &dpll_per_m2_ck, |
| 1088 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1089 | .fixed_div = 4, |
| 1090 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1091 | }; |
| 1092 | |
| 1093 | static struct clk func_24mc_fclk = { |
| 1094 | .name = "func_24mc_fclk", |
| 1095 | .parent = &dpll_per_m2x2_ck, |
| 1096 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1097 | .fixed_div = 8, |
| 1098 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1099 | }; |
| 1100 | |
| 1101 | static const struct clksel_rate div2_4to8_rates[] = { |
| 1102 | { .div = 4, .val = 0, .flags = RATE_IN_4430 }, |
| 1103 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, |
| 1104 | { .div = 0 }, |
| 1105 | }; |
| 1106 | |
| 1107 | static const struct clksel func_48m_fclk_div[] = { |
| 1108 | { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates }, |
| 1109 | { .parent = NULL }, |
| 1110 | }; |
| 1111 | |
| 1112 | static struct clk func_48m_fclk = { |
| 1113 | .name = "func_48m_fclk", |
| 1114 | .parent = &dpll_per_m2x2_ck, |
| 1115 | .clksel = func_48m_fclk_div, |
| 1116 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1117 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 1118 | .ops = &clkops_null, |
| 1119 | .recalc = &omap2_clksel_recalc, |
| 1120 | .round_rate = &omap2_clksel_round_rate, |
| 1121 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1122 | }; |
| 1123 | |
| 1124 | static struct clk func_48mc_fclk = { |
| 1125 | .name = "func_48mc_fclk", |
| 1126 | .parent = &dpll_per_m2x2_ck, |
| 1127 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1128 | .fixed_div = 4, |
| 1129 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1130 | }; |
| 1131 | |
| 1132 | static const struct clksel_rate div2_2to4_rates[] = { |
| 1133 | { .div = 2, .val = 0, .flags = RATE_IN_4430 }, |
| 1134 | { .div = 4, .val = 1, .flags = RATE_IN_4430 }, |
| 1135 | { .div = 0 }, |
| 1136 | }; |
| 1137 | |
| 1138 | static const struct clksel func_64m_fclk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1139 | { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1140 | { .parent = NULL }, |
| 1141 | }; |
| 1142 | |
| 1143 | static struct clk func_64m_fclk = { |
| 1144 | .name = "func_64m_fclk", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1145 | .parent = &dpll_per_m4x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1146 | .clksel = func_64m_fclk_div, |
| 1147 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1148 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 1149 | .ops = &clkops_null, |
| 1150 | .recalc = &omap2_clksel_recalc, |
| 1151 | .round_rate = &omap2_clksel_round_rate, |
| 1152 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1153 | }; |
| 1154 | |
| 1155 | static const struct clksel func_96m_fclk_div[] = { |
| 1156 | { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates }, |
| 1157 | { .parent = NULL }, |
| 1158 | }; |
| 1159 | |
| 1160 | static struct clk func_96m_fclk = { |
| 1161 | .name = "func_96m_fclk", |
| 1162 | .parent = &dpll_per_m2x2_ck, |
| 1163 | .clksel = func_96m_fclk_div, |
| 1164 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1165 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 1166 | .ops = &clkops_null, |
| 1167 | .recalc = &omap2_clksel_recalc, |
| 1168 | .round_rate = &omap2_clksel_round_rate, |
| 1169 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1170 | }; |
| 1171 | |
| 1172 | static const struct clksel hsmmc6_fclk_sel[] = { |
| 1173 | { .parent = &func_64m_fclk, .rates = div_1_0_rates }, |
| 1174 | { .parent = &func_96m_fclk, .rates = div_1_1_rates }, |
| 1175 | { .parent = NULL }, |
| 1176 | }; |
| 1177 | |
| 1178 | static struct clk hsmmc6_fclk = { |
| 1179 | .name = "hsmmc6_fclk", |
| 1180 | .parent = &func_64m_fclk, |
| 1181 | .ops = &clkops_null, |
| 1182 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1183 | }; |
| 1184 | |
| 1185 | static const struct clksel_rate div2_1to8_rates[] = { |
| 1186 | { .div = 1, .val = 0, .flags = RATE_IN_4430 }, |
| 1187 | { .div = 8, .val = 1, .flags = RATE_IN_4430 }, |
| 1188 | { .div = 0 }, |
| 1189 | }; |
| 1190 | |
| 1191 | static const struct clksel init_60m_fclk_div[] = { |
| 1192 | { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates }, |
| 1193 | { .parent = NULL }, |
| 1194 | }; |
| 1195 | |
| 1196 | static struct clk init_60m_fclk = { |
| 1197 | .name = "init_60m_fclk", |
| 1198 | .parent = &dpll_usb_m2_ck, |
| 1199 | .clksel = init_60m_fclk_div, |
| 1200 | .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ, |
| 1201 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1202 | .ops = &clkops_null, |
| 1203 | .recalc = &omap2_clksel_recalc, |
| 1204 | .round_rate = &omap2_clksel_round_rate, |
| 1205 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1206 | }; |
| 1207 | |
| 1208 | static const struct clksel l3_div_div[] = { |
| 1209 | { .parent = &div_core_ck, .rates = div2_1to2_rates }, |
| 1210 | { .parent = NULL }, |
| 1211 | }; |
| 1212 | |
| 1213 | static struct clk l3_div_ck = { |
| 1214 | .name = "l3_div_ck", |
| 1215 | .parent = &div_core_ck, |
| 1216 | .clksel = l3_div_div, |
| 1217 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, |
| 1218 | .clksel_mask = OMAP4430_CLKSEL_L3_MASK, |
| 1219 | .ops = &clkops_null, |
| 1220 | .recalc = &omap2_clksel_recalc, |
| 1221 | .round_rate = &omap2_clksel_round_rate, |
| 1222 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1223 | }; |
| 1224 | |
| 1225 | static const struct clksel l4_div_div[] = { |
| 1226 | { .parent = &l3_div_ck, .rates = div2_1to2_rates }, |
| 1227 | { .parent = NULL }, |
| 1228 | }; |
| 1229 | |
| 1230 | static struct clk l4_div_ck = { |
| 1231 | .name = "l4_div_ck", |
| 1232 | .parent = &l3_div_ck, |
| 1233 | .clksel = l4_div_div, |
| 1234 | .clksel_reg = OMAP4430_CM_CLKSEL_CORE, |
| 1235 | .clksel_mask = OMAP4430_CLKSEL_L4_MASK, |
| 1236 | .ops = &clkops_null, |
| 1237 | .recalc = &omap2_clksel_recalc, |
| 1238 | .round_rate = &omap2_clksel_round_rate, |
| 1239 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1240 | }; |
| 1241 | |
| 1242 | static struct clk lp_clk_div_ck = { |
| 1243 | .name = "lp_clk_div_ck", |
| 1244 | .parent = &dpll_abe_m2x2_ck, |
| 1245 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1246 | .fixed_div = 16, |
| 1247 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1248 | }; |
| 1249 | |
| 1250 | static const struct clksel l4_wkup_clk_mux_sel[] = { |
| 1251 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
| 1252 | { .parent = &lp_clk_div_ck, .rates = div_1_1_rates }, |
| 1253 | { .parent = NULL }, |
| 1254 | }; |
| 1255 | |
| 1256 | static struct clk l4_wkup_clk_mux_ck = { |
| 1257 | .name = "l4_wkup_clk_mux_ck", |
| 1258 | .parent = &sys_clkin_ck, |
| 1259 | .clksel = l4_wkup_clk_mux_sel, |
| 1260 | .init = &omap2_init_clksel_parent, |
| 1261 | .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL, |
| 1262 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1263 | .ops = &clkops_null, |
| 1264 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1265 | }; |
| 1266 | |
| 1267 | static const struct clksel per_abe_nc_fclk_div[] = { |
| 1268 | { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates }, |
| 1269 | { .parent = NULL }, |
| 1270 | }; |
| 1271 | |
| 1272 | static struct clk per_abe_nc_fclk = { |
| 1273 | .name = "per_abe_nc_fclk", |
| 1274 | .parent = &dpll_abe_m2_ck, |
| 1275 | .clksel = per_abe_nc_fclk_div, |
| 1276 | .clksel_reg = OMAP4430_CM_SCALE_FCLK, |
| 1277 | .clksel_mask = OMAP4430_SCALE_FCLK_MASK, |
| 1278 | .ops = &clkops_null, |
| 1279 | .recalc = &omap2_clksel_recalc, |
| 1280 | .round_rate = &omap2_clksel_round_rate, |
| 1281 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1282 | }; |
| 1283 | |
| 1284 | static const struct clksel mcasp2_fclk_sel[] = { |
| 1285 | { .parent = &func_96m_fclk, .rates = div_1_0_rates }, |
| 1286 | { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates }, |
| 1287 | { .parent = NULL }, |
| 1288 | }; |
| 1289 | |
| 1290 | static struct clk mcasp2_fclk = { |
| 1291 | .name = "mcasp2_fclk", |
| 1292 | .parent = &func_96m_fclk, |
| 1293 | .ops = &clkops_null, |
| 1294 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1295 | }; |
| 1296 | |
| 1297 | static struct clk mcasp3_fclk = { |
| 1298 | .name = "mcasp3_fclk", |
| 1299 | .parent = &func_96m_fclk, |
| 1300 | .ops = &clkops_null, |
| 1301 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1302 | }; |
| 1303 | |
| 1304 | static struct clk ocp_abe_iclk = { |
| 1305 | .name = "ocp_abe_iclk", |
| 1306 | .parent = &aess_fclk, |
| 1307 | .ops = &clkops_null, |
| 1308 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1309 | }; |
| 1310 | |
| 1311 | static struct clk per_abe_24m_fclk = { |
| 1312 | .name = "per_abe_24m_fclk", |
| 1313 | .parent = &dpll_abe_m2_ck, |
| 1314 | .ops = &clkops_null, |
Jon Hunter | f17f972 | 2010-12-09 23:13:40 +0100 | [diff] [blame] | 1315 | .fixed_div = 4, |
| 1316 | .recalc = &omap_fixed_divisor_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1317 | }; |
| 1318 | |
| 1319 | static const struct clksel pmd_stm_clock_mux_sel[] = { |
| 1320 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1321 | { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1322 | { .parent = &tie_low_clock_ck, .rates = div_1_2_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1323 | { .parent = NULL }, |
| 1324 | }; |
| 1325 | |
| 1326 | static struct clk pmd_stm_clock_mux_ck = { |
| 1327 | .name = "pmd_stm_clock_mux_ck", |
| 1328 | .parent = &sys_clkin_ck, |
| 1329 | .ops = &clkops_null, |
| 1330 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1331 | }; |
| 1332 | |
| 1333 | static struct clk pmd_trace_clk_mux_ck = { |
| 1334 | .name = "pmd_trace_clk_mux_ck", |
| 1335 | .parent = &sys_clkin_ck, |
| 1336 | .ops = &clkops_null, |
| 1337 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1338 | }; |
| 1339 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1340 | static const struct clksel syc_clk_div_div[] = { |
| 1341 | { .parent = &sys_clkin_ck, .rates = div2_1to2_rates }, |
| 1342 | { .parent = NULL }, |
| 1343 | }; |
| 1344 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1345 | static struct clk syc_clk_div_ck = { |
| 1346 | .name = "syc_clk_div_ck", |
| 1347 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1348 | .clksel = syc_clk_div_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1349 | .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, |
| 1350 | .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, |
| 1351 | .ops = &clkops_null, |
| 1352 | .recalc = &omap2_clksel_recalc, |
| 1353 | .round_rate = &omap2_clksel_round_rate, |
| 1354 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1355 | }; |
| 1356 | |
| 1357 | /* Leaf clocks controlled by modules */ |
| 1358 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1359 | static struct clk aes1_fck = { |
| 1360 | .name = "aes1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1361 | .ops = &clkops_omap2_dflt, |
| 1362 | .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL, |
| 1363 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1364 | .clkdm_name = "l4_secure_clkdm", |
| 1365 | .parent = &l3_div_ck, |
| 1366 | .recalc = &followparent_recalc, |
| 1367 | }; |
| 1368 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1369 | static struct clk aes2_fck = { |
| 1370 | .name = "aes2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1371 | .ops = &clkops_omap2_dflt, |
| 1372 | .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL, |
| 1373 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1374 | .clkdm_name = "l4_secure_clkdm", |
| 1375 | .parent = &l3_div_ck, |
| 1376 | .recalc = &followparent_recalc, |
| 1377 | }; |
| 1378 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1379 | static struct clk aess_fck = { |
| 1380 | .name = "aess_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1381 | .ops = &clkops_omap2_dflt, |
| 1382 | .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL, |
| 1383 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1384 | .clkdm_name = "abe_clkdm", |
| 1385 | .parent = &aess_fclk, |
| 1386 | .recalc = &followparent_recalc, |
| 1387 | }; |
| 1388 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1389 | static struct clk bandgap_fclk = { |
| 1390 | .name = "bandgap_fclk", |
| 1391 | .ops = &clkops_omap2_dflt, |
| 1392 | .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL, |
| 1393 | .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, |
| 1394 | .clkdm_name = "l4_wkup_clkdm", |
| 1395 | .parent = &sys_32k_ck, |
| 1396 | .recalc = &followparent_recalc, |
| 1397 | }; |
| 1398 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1399 | static struct clk des3des_fck = { |
| 1400 | .name = "des3des_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1401 | .ops = &clkops_omap2_dflt, |
| 1402 | .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL, |
| 1403 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1404 | .clkdm_name = "l4_secure_clkdm", |
| 1405 | .parent = &l4_div_ck, |
| 1406 | .recalc = &followparent_recalc, |
| 1407 | }; |
| 1408 | |
| 1409 | static const struct clksel dmic_sync_mux_sel[] = { |
| 1410 | { .parent = &abe_24m_fclk, .rates = div_1_0_rates }, |
| 1411 | { .parent = &syc_clk_div_ck, .rates = div_1_1_rates }, |
| 1412 | { .parent = &func_24m_clk, .rates = div_1_2_rates }, |
| 1413 | { .parent = NULL }, |
| 1414 | }; |
| 1415 | |
| 1416 | static struct clk dmic_sync_mux_ck = { |
| 1417 | .name = "dmic_sync_mux_ck", |
| 1418 | .parent = &abe_24m_fclk, |
| 1419 | .clksel = dmic_sync_mux_sel, |
| 1420 | .init = &omap2_init_clksel_parent, |
| 1421 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
| 1422 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1423 | .ops = &clkops_null, |
| 1424 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1425 | }; |
| 1426 | |
| 1427 | static const struct clksel func_dmic_abe_gfclk_sel[] = { |
| 1428 | { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates }, |
| 1429 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1430 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1431 | { .parent = NULL }, |
| 1432 | }; |
| 1433 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1434 | /* Merged func_dmic_abe_gfclk into dmic */ |
| 1435 | static struct clk dmic_fck = { |
| 1436 | .name = "dmic_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1437 | .parent = &dmic_sync_mux_ck, |
| 1438 | .clksel = func_dmic_abe_gfclk_sel, |
| 1439 | .init = &omap2_init_clksel_parent, |
| 1440 | .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
| 1441 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1442 | .ops = &clkops_omap2_dflt, |
| 1443 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1444 | .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL, |
| 1445 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1446 | .clkdm_name = "abe_clkdm", |
| 1447 | }; |
| 1448 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1449 | static struct clk dsp_fck = { |
| 1450 | .name = "dsp_fck", |
| 1451 | .ops = &clkops_omap2_dflt, |
| 1452 | .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, |
| 1453 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1454 | .clkdm_name = "tesla_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1455 | .parent = &dpll_iva_m4x2_ck, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1456 | .recalc = &followparent_recalc, |
| 1457 | }; |
| 1458 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1459 | static struct clk dss_sys_clk = { |
| 1460 | .name = "dss_sys_clk", |
| 1461 | .ops = &clkops_omap2_dflt, |
| 1462 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1463 | .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, |
| 1464 | .clkdm_name = "l3_dss_clkdm", |
| 1465 | .parent = &syc_clk_div_ck, |
| 1466 | .recalc = &followparent_recalc, |
| 1467 | }; |
| 1468 | |
| 1469 | static struct clk dss_tv_clk = { |
| 1470 | .name = "dss_tv_clk", |
| 1471 | .ops = &clkops_omap2_dflt, |
| 1472 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1473 | .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, |
| 1474 | .clkdm_name = "l3_dss_clkdm", |
| 1475 | .parent = &extalt_clkin_ck, |
| 1476 | .recalc = &followparent_recalc, |
| 1477 | }; |
| 1478 | |
| 1479 | static struct clk dss_dss_clk = { |
| 1480 | .name = "dss_dss_clk", |
| 1481 | .ops = &clkops_omap2_dflt, |
| 1482 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1483 | .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT, |
| 1484 | .clkdm_name = "l3_dss_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1485 | .parent = &dpll_per_m5x2_ck, |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1486 | .recalc = &followparent_recalc, |
| 1487 | }; |
| 1488 | |
| 1489 | static struct clk dss_48mhz_clk = { |
| 1490 | .name = "dss_48mhz_clk", |
| 1491 | .ops = &clkops_omap2_dflt, |
| 1492 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1493 | .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT, |
| 1494 | .clkdm_name = "l3_dss_clkdm", |
| 1495 | .parent = &func_48mc_fclk, |
| 1496 | .recalc = &followparent_recalc, |
| 1497 | }; |
| 1498 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1499 | static struct clk dss_fck = { |
| 1500 | .name = "dss_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1501 | .ops = &clkops_omap2_dflt, |
| 1502 | .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL, |
| 1503 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1504 | .clkdm_name = "l3_dss_clkdm", |
| 1505 | .parent = &l3_div_ck, |
| 1506 | .recalc = &followparent_recalc, |
| 1507 | }; |
| 1508 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1509 | static struct clk efuse_ctrl_cust_fck = { |
| 1510 | .name = "efuse_ctrl_cust_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1511 | .ops = &clkops_omap2_dflt, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1512 | .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, |
| 1513 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1514 | .clkdm_name = "l4_cefuse_clkdm", |
| 1515 | .parent = &sys_clkin_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1516 | .recalc = &followparent_recalc, |
| 1517 | }; |
| 1518 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1519 | static struct clk emif1_fck = { |
| 1520 | .name = "emif1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1521 | .ops = &clkops_omap2_dflt, |
| 1522 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, |
| 1523 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 090830b | 2010-06-16 19:01:33 +0300 | [diff] [blame] | 1524 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1525 | .clkdm_name = "l3_emif_clkdm", |
| 1526 | .parent = &ddrphy_ck, |
| 1527 | .recalc = &followparent_recalc, |
| 1528 | }; |
| 1529 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1530 | static struct clk emif2_fck = { |
| 1531 | .name = "emif2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1532 | .ops = &clkops_omap2_dflt, |
| 1533 | .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, |
| 1534 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Santosh Shilimkar | 090830b | 2010-06-16 19:01:33 +0300 | [diff] [blame] | 1535 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1536 | .clkdm_name = "l3_emif_clkdm", |
| 1537 | .parent = &ddrphy_ck, |
| 1538 | .recalc = &followparent_recalc, |
| 1539 | }; |
| 1540 | |
| 1541 | static const struct clksel fdif_fclk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1542 | { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1543 | { .parent = NULL }, |
| 1544 | }; |
| 1545 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1546 | /* Merged fdif_fclk into fdif */ |
| 1547 | static struct clk fdif_fck = { |
| 1548 | .name = "fdif_fck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1549 | .parent = &dpll_per_m4x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1550 | .clksel = fdif_fclk_div, |
| 1551 | .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
| 1552 | .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK, |
| 1553 | .ops = &clkops_omap2_dflt, |
| 1554 | .recalc = &omap2_clksel_recalc, |
| 1555 | .round_rate = &omap2_clksel_round_rate, |
| 1556 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1557 | .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL, |
| 1558 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1559 | .clkdm_name = "iss_clkdm", |
| 1560 | }; |
| 1561 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1562 | static struct clk fpka_fck = { |
| 1563 | .name = "fpka_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1564 | .ops = &clkops_omap2_dflt, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1565 | .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1566 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1567 | .clkdm_name = "l4_secure_clkdm", |
| 1568 | .parent = &l4_div_ck, |
| 1569 | .recalc = &followparent_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1570 | }; |
| 1571 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1572 | static struct clk gpio1_dbclk = { |
| 1573 | .name = "gpio1_dbclk", |
| 1574 | .ops = &clkops_omap2_dflt, |
| 1575 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
| 1576 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1577 | .clkdm_name = "l4_wkup_clkdm", |
| 1578 | .parent = &sys_32k_ck, |
| 1579 | .recalc = &followparent_recalc, |
| 1580 | }; |
| 1581 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1582 | static struct clk gpio1_ick = { |
| 1583 | .name = "gpio1_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1584 | .ops = &clkops_omap2_dflt, |
| 1585 | .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL, |
| 1586 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1587 | .clkdm_name = "l4_wkup_clkdm", |
| 1588 | .parent = &l4_wkup_clk_mux_ck, |
| 1589 | .recalc = &followparent_recalc, |
| 1590 | }; |
| 1591 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1592 | static struct clk gpio2_dbclk = { |
| 1593 | .name = "gpio2_dbclk", |
| 1594 | .ops = &clkops_omap2_dflt, |
| 1595 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
| 1596 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1597 | .clkdm_name = "l4_per_clkdm", |
| 1598 | .parent = &sys_32k_ck, |
| 1599 | .recalc = &followparent_recalc, |
| 1600 | }; |
| 1601 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1602 | static struct clk gpio2_ick = { |
| 1603 | .name = "gpio2_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1604 | .ops = &clkops_omap2_dflt, |
| 1605 | .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL, |
| 1606 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1607 | .clkdm_name = "l4_per_clkdm", |
| 1608 | .parent = &l4_div_ck, |
| 1609 | .recalc = &followparent_recalc, |
| 1610 | }; |
| 1611 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1612 | static struct clk gpio3_dbclk = { |
| 1613 | .name = "gpio3_dbclk", |
| 1614 | .ops = &clkops_omap2_dflt, |
| 1615 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
| 1616 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1617 | .clkdm_name = "l4_per_clkdm", |
| 1618 | .parent = &sys_32k_ck, |
| 1619 | .recalc = &followparent_recalc, |
| 1620 | }; |
| 1621 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1622 | static struct clk gpio3_ick = { |
| 1623 | .name = "gpio3_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1624 | .ops = &clkops_omap2_dflt, |
| 1625 | .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, |
| 1626 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1627 | .clkdm_name = "l4_per_clkdm", |
| 1628 | .parent = &l4_div_ck, |
| 1629 | .recalc = &followparent_recalc, |
| 1630 | }; |
| 1631 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1632 | static struct clk gpio4_dbclk = { |
| 1633 | .name = "gpio4_dbclk", |
| 1634 | .ops = &clkops_omap2_dflt, |
| 1635 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
| 1636 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1637 | .clkdm_name = "l4_per_clkdm", |
| 1638 | .parent = &sys_32k_ck, |
| 1639 | .recalc = &followparent_recalc, |
| 1640 | }; |
| 1641 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1642 | static struct clk gpio4_ick = { |
| 1643 | .name = "gpio4_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1644 | .ops = &clkops_omap2_dflt, |
| 1645 | .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL, |
| 1646 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1647 | .clkdm_name = "l4_per_clkdm", |
| 1648 | .parent = &l4_div_ck, |
| 1649 | .recalc = &followparent_recalc, |
| 1650 | }; |
| 1651 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1652 | static struct clk gpio5_dbclk = { |
| 1653 | .name = "gpio5_dbclk", |
| 1654 | .ops = &clkops_omap2_dflt, |
| 1655 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
| 1656 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1657 | .clkdm_name = "l4_per_clkdm", |
| 1658 | .parent = &sys_32k_ck, |
| 1659 | .recalc = &followparent_recalc, |
| 1660 | }; |
| 1661 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1662 | static struct clk gpio5_ick = { |
| 1663 | .name = "gpio5_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1664 | .ops = &clkops_omap2_dflt, |
| 1665 | .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, |
| 1666 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1667 | .clkdm_name = "l4_per_clkdm", |
| 1668 | .parent = &l4_div_ck, |
| 1669 | .recalc = &followparent_recalc, |
| 1670 | }; |
| 1671 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1672 | static struct clk gpio6_dbclk = { |
| 1673 | .name = "gpio6_dbclk", |
| 1674 | .ops = &clkops_omap2_dflt, |
| 1675 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, |
| 1676 | .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT, |
| 1677 | .clkdm_name = "l4_per_clkdm", |
| 1678 | .parent = &sys_32k_ck, |
| 1679 | .recalc = &followparent_recalc, |
| 1680 | }; |
| 1681 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1682 | static struct clk gpio6_ick = { |
| 1683 | .name = "gpio6_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1684 | .ops = &clkops_omap2_dflt, |
| 1685 | .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL, |
| 1686 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1687 | .clkdm_name = "l4_per_clkdm", |
| 1688 | .parent = &l4_div_ck, |
| 1689 | .recalc = &followparent_recalc, |
| 1690 | }; |
| 1691 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1692 | static struct clk gpmc_ick = { |
| 1693 | .name = "gpmc_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1694 | .ops = &clkops_omap2_dflt, |
| 1695 | .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL, |
| 1696 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1697 | .clkdm_name = "l3_2_clkdm", |
| 1698 | .parent = &l3_div_ck, |
| 1699 | .recalc = &followparent_recalc, |
| 1700 | }; |
| 1701 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1702 | static const struct clksel sgx_clk_mux_sel[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1703 | { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates }, |
| 1704 | { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates }, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1705 | { .parent = NULL }, |
| 1706 | }; |
| 1707 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1708 | /* Merged sgx_clk_mux into gpu */ |
| 1709 | static struct clk gpu_fck = { |
| 1710 | .name = "gpu_fck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1711 | .parent = &dpll_core_m7x2_ck, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1712 | .clksel = sgx_clk_mux_sel, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1713 | .init = &omap2_init_clksel_parent, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1714 | .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
| 1715 | .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1716 | .ops = &clkops_omap2_dflt, |
| 1717 | .recalc = &omap2_clksel_recalc, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1718 | .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1719 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1720 | .clkdm_name = "l3_gfx_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1721 | }; |
| 1722 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1723 | static struct clk hdq1w_fck = { |
| 1724 | .name = "hdq1w_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1725 | .ops = &clkops_omap2_dflt, |
| 1726 | .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL, |
| 1727 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1728 | .clkdm_name = "l4_per_clkdm", |
| 1729 | .parent = &func_12m_fclk, |
| 1730 | .recalc = &followparent_recalc, |
| 1731 | }; |
| 1732 | |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1733 | static const struct clksel hsi_fclk_div[] = { |
| 1734 | { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, |
| 1735 | { .parent = NULL }, |
| 1736 | }; |
| 1737 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1738 | /* Merged hsi_fclk into hsi */ |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1739 | static struct clk hsi_fck = { |
| 1740 | .name = "hsi_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1741 | .parent = &dpll_per_m2x2_ck, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1742 | .clksel = hsi_fclk_div, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1743 | .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
| 1744 | .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, |
| 1745 | .ops = &clkops_omap2_dflt, |
| 1746 | .recalc = &omap2_clksel_recalc, |
| 1747 | .round_rate = &omap2_clksel_round_rate, |
| 1748 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1749 | .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, |
| 1750 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1751 | .clkdm_name = "l3_init_clkdm", |
| 1752 | }; |
| 1753 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1754 | static struct clk i2c1_fck = { |
| 1755 | .name = "i2c1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1756 | .ops = &clkops_omap2_dflt, |
| 1757 | .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, |
| 1758 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1759 | .clkdm_name = "l4_per_clkdm", |
| 1760 | .parent = &func_96m_fclk, |
| 1761 | .recalc = &followparent_recalc, |
| 1762 | }; |
| 1763 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1764 | static struct clk i2c2_fck = { |
| 1765 | .name = "i2c2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1766 | .ops = &clkops_omap2_dflt, |
| 1767 | .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, |
| 1768 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1769 | .clkdm_name = "l4_per_clkdm", |
| 1770 | .parent = &func_96m_fclk, |
| 1771 | .recalc = &followparent_recalc, |
| 1772 | }; |
| 1773 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1774 | static struct clk i2c3_fck = { |
| 1775 | .name = "i2c3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1776 | .ops = &clkops_omap2_dflt, |
| 1777 | .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, |
| 1778 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1779 | .clkdm_name = "l4_per_clkdm", |
| 1780 | .parent = &func_96m_fclk, |
| 1781 | .recalc = &followparent_recalc, |
| 1782 | }; |
| 1783 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1784 | static struct clk i2c4_fck = { |
| 1785 | .name = "i2c4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1786 | .ops = &clkops_omap2_dflt, |
| 1787 | .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, |
| 1788 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1789 | .clkdm_name = "l4_per_clkdm", |
| 1790 | .parent = &func_96m_fclk, |
| 1791 | .recalc = &followparent_recalc, |
| 1792 | }; |
| 1793 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1794 | static struct clk ipu_fck = { |
| 1795 | .name = "ipu_fck", |
| 1796 | .ops = &clkops_omap2_dflt, |
| 1797 | .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, |
| 1798 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1799 | .clkdm_name = "ducati_clkdm", |
| 1800 | .parent = &ducati_clk_mux_ck, |
| 1801 | .recalc = &followparent_recalc, |
| 1802 | }; |
| 1803 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 1804 | static struct clk iss_ctrlclk = { |
| 1805 | .name = "iss_ctrlclk", |
| 1806 | .ops = &clkops_omap2_dflt, |
| 1807 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, |
| 1808 | .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT, |
| 1809 | .clkdm_name = "iss_clkdm", |
| 1810 | .parent = &func_96m_fclk, |
| 1811 | .recalc = &followparent_recalc, |
| 1812 | }; |
| 1813 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1814 | static struct clk iss_fck = { |
| 1815 | .name = "iss_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1816 | .ops = &clkops_omap2_dflt, |
| 1817 | .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL, |
| 1818 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1819 | .clkdm_name = "iss_clkdm", |
| 1820 | .parent = &ducati_clk_mux_ck, |
| 1821 | .recalc = &followparent_recalc, |
| 1822 | }; |
| 1823 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1824 | static struct clk iva_fck = { |
| 1825 | .name = "iva_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1826 | .ops = &clkops_omap2_dflt, |
| 1827 | .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, |
| 1828 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1829 | .clkdm_name = "ivahd_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 1830 | .parent = &dpll_iva_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1831 | .recalc = &followparent_recalc, |
| 1832 | }; |
| 1833 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1834 | static struct clk kbd_fck = { |
| 1835 | .name = "kbd_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1836 | .ops = &clkops_omap2_dflt, |
| 1837 | .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, |
| 1838 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1839 | .clkdm_name = "l4_wkup_clkdm", |
| 1840 | .parent = &sys_32k_ck, |
| 1841 | .recalc = &followparent_recalc, |
| 1842 | }; |
| 1843 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1844 | static struct clk l3_instr_ick = { |
| 1845 | .name = "l3_instr_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1846 | .ops = &clkops_omap2_dflt, |
| 1847 | .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, |
| 1848 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1849 | .clkdm_name = "l3_instr_clkdm", |
Santosh Shilimkar | 60a0e5d | 2010-12-21 22:37:29 -0700 | [diff] [blame] | 1850 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1851 | .parent = &l3_div_ck, |
| 1852 | .recalc = &followparent_recalc, |
| 1853 | }; |
| 1854 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 1855 | static struct clk l3_main_3_ick = { |
| 1856 | .name = "l3_main_3_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1857 | .ops = &clkops_omap2_dflt, |
| 1858 | .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, |
| 1859 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 1860 | .clkdm_name = "l3_instr_clkdm", |
Santosh Shilimkar | 60a0e5d | 2010-12-21 22:37:29 -0700 | [diff] [blame] | 1861 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1862 | .parent = &l3_div_ck, |
| 1863 | .recalc = &followparent_recalc, |
| 1864 | }; |
| 1865 | |
| 1866 | static struct clk mcasp_sync_mux_ck = { |
| 1867 | .name = "mcasp_sync_mux_ck", |
| 1868 | .parent = &abe_24m_fclk, |
| 1869 | .clksel = dmic_sync_mux_sel, |
| 1870 | .init = &omap2_init_clksel_parent, |
| 1871 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
| 1872 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1873 | .ops = &clkops_null, |
| 1874 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1875 | }; |
| 1876 | |
| 1877 | static const struct clksel func_mcasp_abe_gfclk_sel[] = { |
| 1878 | { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates }, |
| 1879 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1880 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1881 | { .parent = NULL }, |
| 1882 | }; |
| 1883 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1884 | /* Merged func_mcasp_abe_gfclk into mcasp */ |
| 1885 | static struct clk mcasp_fck = { |
| 1886 | .name = "mcasp_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1887 | .parent = &mcasp_sync_mux_ck, |
| 1888 | .clksel = func_mcasp_abe_gfclk_sel, |
| 1889 | .init = &omap2_init_clksel_parent, |
| 1890 | .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
| 1891 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1892 | .ops = &clkops_omap2_dflt, |
| 1893 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1894 | .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL, |
| 1895 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1896 | .clkdm_name = "abe_clkdm", |
| 1897 | }; |
| 1898 | |
| 1899 | static struct clk mcbsp1_sync_mux_ck = { |
| 1900 | .name = "mcbsp1_sync_mux_ck", |
| 1901 | .parent = &abe_24m_fclk, |
| 1902 | .clksel = dmic_sync_mux_sel, |
| 1903 | .init = &omap2_init_clksel_parent, |
| 1904 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
| 1905 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1906 | .ops = &clkops_null, |
| 1907 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1908 | }; |
| 1909 | |
| 1910 | static const struct clksel func_mcbsp1_gfclk_sel[] = { |
| 1911 | { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates }, |
| 1912 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1913 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1914 | { .parent = NULL }, |
| 1915 | }; |
| 1916 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1917 | /* Merged func_mcbsp1_gfclk into mcbsp1 */ |
| 1918 | static struct clk mcbsp1_fck = { |
| 1919 | .name = "mcbsp1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1920 | .parent = &mcbsp1_sync_mux_ck, |
| 1921 | .clksel = func_mcbsp1_gfclk_sel, |
| 1922 | .init = &omap2_init_clksel_parent, |
| 1923 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
| 1924 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1925 | .ops = &clkops_omap2_dflt, |
| 1926 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1927 | .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL, |
| 1928 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1929 | .clkdm_name = "abe_clkdm", |
| 1930 | }; |
| 1931 | |
| 1932 | static struct clk mcbsp2_sync_mux_ck = { |
| 1933 | .name = "mcbsp2_sync_mux_ck", |
| 1934 | .parent = &abe_24m_fclk, |
| 1935 | .clksel = dmic_sync_mux_sel, |
| 1936 | .init = &omap2_init_clksel_parent, |
| 1937 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
| 1938 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1939 | .ops = &clkops_null, |
| 1940 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1941 | }; |
| 1942 | |
| 1943 | static const struct clksel func_mcbsp2_gfclk_sel[] = { |
| 1944 | { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates }, |
| 1945 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1946 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1947 | { .parent = NULL }, |
| 1948 | }; |
| 1949 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1950 | /* Merged func_mcbsp2_gfclk into mcbsp2 */ |
| 1951 | static struct clk mcbsp2_fck = { |
| 1952 | .name = "mcbsp2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1953 | .parent = &mcbsp2_sync_mux_ck, |
| 1954 | .clksel = func_mcbsp2_gfclk_sel, |
| 1955 | .init = &omap2_init_clksel_parent, |
| 1956 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
| 1957 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1958 | .ops = &clkops_omap2_dflt, |
| 1959 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1960 | .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL, |
| 1961 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1962 | .clkdm_name = "abe_clkdm", |
| 1963 | }; |
| 1964 | |
| 1965 | static struct clk mcbsp3_sync_mux_ck = { |
| 1966 | .name = "mcbsp3_sync_mux_ck", |
| 1967 | .parent = &abe_24m_fclk, |
| 1968 | .clksel = dmic_sync_mux_sel, |
| 1969 | .init = &omap2_init_clksel_parent, |
| 1970 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
| 1971 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 1972 | .ops = &clkops_null, |
| 1973 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1974 | }; |
| 1975 | |
| 1976 | static const struct clksel func_mcbsp3_gfclk_sel[] = { |
| 1977 | { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates }, |
| 1978 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 1979 | { .parent = &slimbus_clk, .rates = div_1_2_rates }, |
| 1980 | { .parent = NULL }, |
| 1981 | }; |
| 1982 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 1983 | /* Merged func_mcbsp3_gfclk into mcbsp3 */ |
| 1984 | static struct clk mcbsp3_fck = { |
| 1985 | .name = "mcbsp3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1986 | .parent = &mcbsp3_sync_mux_ck, |
| 1987 | .clksel = func_mcbsp3_gfclk_sel, |
| 1988 | .init = &omap2_init_clksel_parent, |
| 1989 | .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
| 1990 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK, |
| 1991 | .ops = &clkops_omap2_dflt, |
| 1992 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 1993 | .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL, |
| 1994 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 1995 | .clkdm_name = "abe_clkdm", |
| 1996 | }; |
| 1997 | |
| 1998 | static struct clk mcbsp4_sync_mux_ck = { |
| 1999 | .name = "mcbsp4_sync_mux_ck", |
| 2000 | .parent = &func_96m_fclk, |
| 2001 | .clksel = mcasp2_fclk_sel, |
| 2002 | .init = &omap2_init_clksel_parent, |
| 2003 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
| 2004 | .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK, |
| 2005 | .ops = &clkops_null, |
| 2006 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2007 | }; |
| 2008 | |
| 2009 | static const struct clksel per_mcbsp4_gfclk_sel[] = { |
| 2010 | { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates }, |
| 2011 | { .parent = &pad_clks_ck, .rates = div_1_1_rates }, |
| 2012 | { .parent = NULL }, |
| 2013 | }; |
| 2014 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2015 | /* Merged per_mcbsp4_gfclk into mcbsp4 */ |
| 2016 | static struct clk mcbsp4_fck = { |
| 2017 | .name = "mcbsp4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2018 | .parent = &mcbsp4_sync_mux_ck, |
| 2019 | .clksel = per_mcbsp4_gfclk_sel, |
| 2020 | .init = &omap2_init_clksel_parent, |
| 2021 | .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
| 2022 | .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK, |
| 2023 | .ops = &clkops_omap2_dflt, |
| 2024 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2025 | .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL, |
| 2026 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2027 | .clkdm_name = "l4_per_clkdm", |
| 2028 | }; |
| 2029 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2030 | static struct clk mcpdm_fck = { |
| 2031 | .name = "mcpdm_fck", |
| 2032 | .ops = &clkops_omap2_dflt, |
| 2033 | .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, |
| 2034 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2035 | .clkdm_name = "abe_clkdm", |
| 2036 | .parent = &pad_clks_ck, |
| 2037 | .recalc = &followparent_recalc, |
| 2038 | }; |
| 2039 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2040 | static struct clk mcspi1_fck = { |
| 2041 | .name = "mcspi1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2042 | .ops = &clkops_omap2_dflt, |
| 2043 | .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL, |
| 2044 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2045 | .clkdm_name = "l4_per_clkdm", |
| 2046 | .parent = &func_48m_fclk, |
| 2047 | .recalc = &followparent_recalc, |
| 2048 | }; |
| 2049 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2050 | static struct clk mcspi2_fck = { |
| 2051 | .name = "mcspi2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2052 | .ops = &clkops_omap2_dflt, |
| 2053 | .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL, |
| 2054 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2055 | .clkdm_name = "l4_per_clkdm", |
| 2056 | .parent = &func_48m_fclk, |
| 2057 | .recalc = &followparent_recalc, |
| 2058 | }; |
| 2059 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2060 | static struct clk mcspi3_fck = { |
| 2061 | .name = "mcspi3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2062 | .ops = &clkops_omap2_dflt, |
| 2063 | .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL, |
| 2064 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2065 | .clkdm_name = "l4_per_clkdm", |
| 2066 | .parent = &func_48m_fclk, |
| 2067 | .recalc = &followparent_recalc, |
| 2068 | }; |
| 2069 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2070 | static struct clk mcspi4_fck = { |
| 2071 | .name = "mcspi4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2072 | .ops = &clkops_omap2_dflt, |
| 2073 | .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL, |
| 2074 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2075 | .clkdm_name = "l4_per_clkdm", |
| 2076 | .parent = &func_48m_fclk, |
| 2077 | .recalc = &followparent_recalc, |
| 2078 | }; |
| 2079 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2080 | /* Merged hsmmc1_fclk into mmc1 */ |
| 2081 | static struct clk mmc1_fck = { |
| 2082 | .name = "mmc1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2083 | .parent = &func_64m_fclk, |
| 2084 | .clksel = hsmmc6_fclk_sel, |
| 2085 | .init = &omap2_init_clksel_parent, |
| 2086 | .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
| 2087 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2088 | .ops = &clkops_omap2_dflt, |
| 2089 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2090 | .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, |
| 2091 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2092 | .clkdm_name = "l3_init_clkdm", |
| 2093 | }; |
| 2094 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2095 | /* Merged hsmmc2_fclk into mmc2 */ |
| 2096 | static struct clk mmc2_fck = { |
| 2097 | .name = "mmc2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2098 | .parent = &func_64m_fclk, |
| 2099 | .clksel = hsmmc6_fclk_sel, |
| 2100 | .init = &omap2_init_clksel_parent, |
| 2101 | .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
| 2102 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2103 | .ops = &clkops_omap2_dflt, |
| 2104 | .recalc = &omap2_clksel_recalc, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2105 | .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL, |
| 2106 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2107 | .clkdm_name = "l3_init_clkdm", |
| 2108 | }; |
| 2109 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2110 | static struct clk mmc3_fck = { |
| 2111 | .name = "mmc3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2112 | .ops = &clkops_omap2_dflt, |
| 2113 | .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL, |
| 2114 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2115 | .clkdm_name = "l4_per_clkdm", |
| 2116 | .parent = &func_48m_fclk, |
| 2117 | .recalc = &followparent_recalc, |
| 2118 | }; |
| 2119 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2120 | static struct clk mmc4_fck = { |
| 2121 | .name = "mmc4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2122 | .ops = &clkops_omap2_dflt, |
| 2123 | .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL, |
| 2124 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2125 | .clkdm_name = "l4_per_clkdm", |
| 2126 | .parent = &func_48m_fclk, |
| 2127 | .recalc = &followparent_recalc, |
| 2128 | }; |
| 2129 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2130 | static struct clk mmc5_fck = { |
| 2131 | .name = "mmc5_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2132 | .ops = &clkops_omap2_dflt, |
| 2133 | .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL, |
| 2134 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2135 | .clkdm_name = "l4_per_clkdm", |
| 2136 | .parent = &func_48m_fclk, |
| 2137 | .recalc = &followparent_recalc, |
| 2138 | }; |
| 2139 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2140 | static struct clk ocp2scp_usb_phy_phy_48m = { |
| 2141 | .name = "ocp2scp_usb_phy_phy_48m", |
| 2142 | .ops = &clkops_omap2_dflt, |
| 2143 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
| 2144 | .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, |
| 2145 | .clkdm_name = "l3_init_clkdm", |
| 2146 | .parent = &func_48m_fclk, |
| 2147 | .recalc = &followparent_recalc, |
| 2148 | }; |
| 2149 | |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2150 | static struct clk ocp2scp_usb_phy_ick = { |
| 2151 | .name = "ocp2scp_usb_phy_ick", |
| 2152 | .ops = &clkops_omap2_dflt, |
| 2153 | .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, |
| 2154 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2155 | .clkdm_name = "l3_init_clkdm", |
| 2156 | .parent = &l4_div_ck, |
| 2157 | .recalc = &followparent_recalc, |
| 2158 | }; |
| 2159 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2160 | static struct clk ocp_wp_noc_ick = { |
| 2161 | .name = "ocp_wp_noc_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2162 | .ops = &clkops_omap2_dflt, |
| 2163 | .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, |
| 2164 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2165 | .clkdm_name = "l3_instr_clkdm", |
Santosh Shilimkar | 60a0e5d | 2010-12-21 22:37:29 -0700 | [diff] [blame] | 2166 | .flags = ENABLE_ON_INIT, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2167 | .parent = &l3_div_ck, |
| 2168 | .recalc = &followparent_recalc, |
| 2169 | }; |
| 2170 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2171 | static struct clk rng_ick = { |
| 2172 | .name = "rng_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2173 | .ops = &clkops_omap2_dflt, |
| 2174 | .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL, |
| 2175 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2176 | .clkdm_name = "l4_secure_clkdm", |
| 2177 | .parent = &l4_div_ck, |
| 2178 | .recalc = &followparent_recalc, |
| 2179 | }; |
| 2180 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2181 | static struct clk sha2md5_fck = { |
| 2182 | .name = "sha2md5_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2183 | .ops = &clkops_omap2_dflt, |
| 2184 | .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, |
| 2185 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2186 | .clkdm_name = "l4_secure_clkdm", |
| 2187 | .parent = &l3_div_ck, |
| 2188 | .recalc = &followparent_recalc, |
| 2189 | }; |
| 2190 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2191 | static struct clk sl2if_ick = { |
| 2192 | .name = "sl2if_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2193 | .ops = &clkops_omap2_dflt, |
| 2194 | .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, |
| 2195 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2196 | .clkdm_name = "ivahd_clkdm", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2197 | .parent = &dpll_iva_m5x2_ck, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2198 | .recalc = &followparent_recalc, |
| 2199 | }; |
| 2200 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2201 | static struct clk slimbus1_fclk_1 = { |
| 2202 | .name = "slimbus1_fclk_1", |
| 2203 | .ops = &clkops_omap2_dflt, |
| 2204 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2205 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT, |
| 2206 | .clkdm_name = "abe_clkdm", |
| 2207 | .parent = &func_24m_clk, |
| 2208 | .recalc = &followparent_recalc, |
| 2209 | }; |
| 2210 | |
| 2211 | static struct clk slimbus1_fclk_0 = { |
| 2212 | .name = "slimbus1_fclk_0", |
| 2213 | .ops = &clkops_omap2_dflt, |
| 2214 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2215 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT, |
| 2216 | .clkdm_name = "abe_clkdm", |
| 2217 | .parent = &abe_24m_fclk, |
| 2218 | .recalc = &followparent_recalc, |
| 2219 | }; |
| 2220 | |
| 2221 | static struct clk slimbus1_fclk_2 = { |
| 2222 | .name = "slimbus1_fclk_2", |
| 2223 | .ops = &clkops_omap2_dflt, |
| 2224 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2225 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT, |
| 2226 | .clkdm_name = "abe_clkdm", |
| 2227 | .parent = &pad_clks_ck, |
| 2228 | .recalc = &followparent_recalc, |
| 2229 | }; |
| 2230 | |
| 2231 | static struct clk slimbus1_slimbus_clk = { |
| 2232 | .name = "slimbus1_slimbus_clk", |
| 2233 | .ops = &clkops_omap2_dflt, |
| 2234 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2235 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, |
| 2236 | .clkdm_name = "abe_clkdm", |
| 2237 | .parent = &slimbus_clk, |
| 2238 | .recalc = &followparent_recalc, |
| 2239 | }; |
| 2240 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2241 | static struct clk slimbus1_fck = { |
| 2242 | .name = "slimbus1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2243 | .ops = &clkops_omap2_dflt, |
| 2244 | .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL, |
| 2245 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2246 | .clkdm_name = "abe_clkdm", |
| 2247 | .parent = &ocp_abe_iclk, |
| 2248 | .recalc = &followparent_recalc, |
| 2249 | }; |
| 2250 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2251 | static struct clk slimbus2_fclk_1 = { |
| 2252 | .name = "slimbus2_fclk_1", |
| 2253 | .ops = &clkops_omap2_dflt, |
| 2254 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2255 | .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, |
| 2256 | .clkdm_name = "l4_per_clkdm", |
| 2257 | .parent = &per_abe_24m_fclk, |
| 2258 | .recalc = &followparent_recalc, |
| 2259 | }; |
| 2260 | |
| 2261 | static struct clk slimbus2_fclk_0 = { |
| 2262 | .name = "slimbus2_fclk_0", |
| 2263 | .ops = &clkops_omap2_dflt, |
| 2264 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2265 | .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, |
| 2266 | .clkdm_name = "l4_per_clkdm", |
| 2267 | .parent = &func_24mc_fclk, |
| 2268 | .recalc = &followparent_recalc, |
| 2269 | }; |
| 2270 | |
| 2271 | static struct clk slimbus2_slimbus_clk = { |
| 2272 | .name = "slimbus2_slimbus_clk", |
| 2273 | .ops = &clkops_omap2_dflt, |
| 2274 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2275 | .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, |
| 2276 | .clkdm_name = "l4_per_clkdm", |
| 2277 | .parent = &pad_slimbus_core_clks_ck, |
| 2278 | .recalc = &followparent_recalc, |
| 2279 | }; |
| 2280 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2281 | static struct clk slimbus2_fck = { |
| 2282 | .name = "slimbus2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2283 | .ops = &clkops_omap2_dflt, |
| 2284 | .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL, |
| 2285 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2286 | .clkdm_name = "l4_per_clkdm", |
| 2287 | .parent = &l4_div_ck, |
| 2288 | .recalc = &followparent_recalc, |
| 2289 | }; |
| 2290 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2291 | static struct clk smartreflex_core_fck = { |
| 2292 | .name = "smartreflex_core_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2293 | .ops = &clkops_omap2_dflt, |
| 2294 | .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, |
| 2295 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2296 | .clkdm_name = "l4_ao_clkdm", |
| 2297 | .parent = &l4_wkup_clk_mux_ck, |
| 2298 | .recalc = &followparent_recalc, |
| 2299 | }; |
| 2300 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2301 | static struct clk smartreflex_iva_fck = { |
| 2302 | .name = "smartreflex_iva_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2303 | .ops = &clkops_omap2_dflt, |
| 2304 | .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, |
| 2305 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2306 | .clkdm_name = "l4_ao_clkdm", |
| 2307 | .parent = &l4_wkup_clk_mux_ck, |
| 2308 | .recalc = &followparent_recalc, |
| 2309 | }; |
| 2310 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2311 | static struct clk smartreflex_mpu_fck = { |
| 2312 | .name = "smartreflex_mpu_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2313 | .ops = &clkops_omap2_dflt, |
| 2314 | .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, |
| 2315 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2316 | .clkdm_name = "l4_ao_clkdm", |
| 2317 | .parent = &l4_wkup_clk_mux_ck, |
| 2318 | .recalc = &followparent_recalc, |
| 2319 | }; |
| 2320 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2321 | /* Merged dmt1_clk_mux into timer1 */ |
| 2322 | static struct clk timer1_fck = { |
| 2323 | .name = "timer1_fck", |
| 2324 | .parent = &sys_clkin_ck, |
| 2325 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2326 | .init = &omap2_init_clksel_parent, |
| 2327 | .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, |
| 2328 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2329 | .ops = &clkops_omap2_dflt, |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2330 | .recalc = &omap2_clksel_recalc, |
| 2331 | .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL, |
| 2332 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2333 | .clkdm_name = "l4_wkup_clkdm", |
| 2334 | }; |
| 2335 | |
| 2336 | /* Merged cm2_dm10_mux into timer10 */ |
| 2337 | static struct clk timer10_fck = { |
| 2338 | .name = "timer10_fck", |
| 2339 | .parent = &sys_clkin_ck, |
| 2340 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2341 | .init = &omap2_init_clksel_parent, |
| 2342 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, |
| 2343 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2344 | .ops = &clkops_omap2_dflt, |
| 2345 | .recalc = &omap2_clksel_recalc, |
| 2346 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, |
| 2347 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2348 | .clkdm_name = "l4_per_clkdm", |
| 2349 | }; |
| 2350 | |
| 2351 | /* Merged cm2_dm11_mux into timer11 */ |
| 2352 | static struct clk timer11_fck = { |
| 2353 | .name = "timer11_fck", |
| 2354 | .parent = &sys_clkin_ck, |
| 2355 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2356 | .init = &omap2_init_clksel_parent, |
| 2357 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, |
| 2358 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2359 | .ops = &clkops_omap2_dflt, |
| 2360 | .recalc = &omap2_clksel_recalc, |
| 2361 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, |
| 2362 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2363 | .clkdm_name = "l4_per_clkdm", |
| 2364 | }; |
| 2365 | |
| 2366 | /* Merged cm2_dm2_mux into timer2 */ |
| 2367 | static struct clk timer2_fck = { |
| 2368 | .name = "timer2_fck", |
| 2369 | .parent = &sys_clkin_ck, |
| 2370 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2371 | .init = &omap2_init_clksel_parent, |
| 2372 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, |
| 2373 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2374 | .ops = &clkops_omap2_dflt, |
| 2375 | .recalc = &omap2_clksel_recalc, |
| 2376 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, |
| 2377 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2378 | .clkdm_name = "l4_per_clkdm", |
| 2379 | }; |
| 2380 | |
| 2381 | /* Merged cm2_dm3_mux into timer3 */ |
| 2382 | static struct clk timer3_fck = { |
| 2383 | .name = "timer3_fck", |
| 2384 | .parent = &sys_clkin_ck, |
| 2385 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2386 | .init = &omap2_init_clksel_parent, |
| 2387 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, |
| 2388 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2389 | .ops = &clkops_omap2_dflt, |
| 2390 | .recalc = &omap2_clksel_recalc, |
| 2391 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, |
| 2392 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2393 | .clkdm_name = "l4_per_clkdm", |
| 2394 | }; |
| 2395 | |
| 2396 | /* Merged cm2_dm4_mux into timer4 */ |
| 2397 | static struct clk timer4_fck = { |
| 2398 | .name = "timer4_fck", |
| 2399 | .parent = &sys_clkin_ck, |
| 2400 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2401 | .init = &omap2_init_clksel_parent, |
| 2402 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, |
| 2403 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2404 | .ops = &clkops_omap2_dflt, |
| 2405 | .recalc = &omap2_clksel_recalc, |
| 2406 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, |
| 2407 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2408 | .clkdm_name = "l4_per_clkdm", |
| 2409 | }; |
| 2410 | |
| 2411 | static const struct clksel timer5_sync_mux_sel[] = { |
| 2412 | { .parent = &syc_clk_div_ck, .rates = div_1_0_rates }, |
| 2413 | { .parent = &sys_32k_ck, .rates = div_1_1_rates }, |
| 2414 | { .parent = NULL }, |
| 2415 | }; |
| 2416 | |
| 2417 | /* Merged timer5_sync_mux into timer5 */ |
| 2418 | static struct clk timer5_fck = { |
| 2419 | .name = "timer5_fck", |
| 2420 | .parent = &syc_clk_div_ck, |
| 2421 | .clksel = timer5_sync_mux_sel, |
| 2422 | .init = &omap2_init_clksel_parent, |
| 2423 | .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, |
| 2424 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2425 | .ops = &clkops_omap2_dflt, |
| 2426 | .recalc = &omap2_clksel_recalc, |
| 2427 | .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL, |
| 2428 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2429 | .clkdm_name = "abe_clkdm", |
| 2430 | }; |
| 2431 | |
| 2432 | /* Merged timer6_sync_mux into timer6 */ |
| 2433 | static struct clk timer6_fck = { |
| 2434 | .name = "timer6_fck", |
| 2435 | .parent = &syc_clk_div_ck, |
| 2436 | .clksel = timer5_sync_mux_sel, |
| 2437 | .init = &omap2_init_clksel_parent, |
| 2438 | .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, |
| 2439 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2440 | .ops = &clkops_omap2_dflt, |
| 2441 | .recalc = &omap2_clksel_recalc, |
| 2442 | .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL, |
| 2443 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2444 | .clkdm_name = "abe_clkdm", |
| 2445 | }; |
| 2446 | |
| 2447 | /* Merged timer7_sync_mux into timer7 */ |
| 2448 | static struct clk timer7_fck = { |
| 2449 | .name = "timer7_fck", |
| 2450 | .parent = &syc_clk_div_ck, |
| 2451 | .clksel = timer5_sync_mux_sel, |
| 2452 | .init = &omap2_init_clksel_parent, |
| 2453 | .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, |
| 2454 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2455 | .ops = &clkops_omap2_dflt, |
| 2456 | .recalc = &omap2_clksel_recalc, |
| 2457 | .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL, |
| 2458 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2459 | .clkdm_name = "abe_clkdm", |
| 2460 | }; |
| 2461 | |
| 2462 | /* Merged timer8_sync_mux into timer8 */ |
| 2463 | static struct clk timer8_fck = { |
| 2464 | .name = "timer8_fck", |
| 2465 | .parent = &syc_clk_div_ck, |
| 2466 | .clksel = timer5_sync_mux_sel, |
| 2467 | .init = &omap2_init_clksel_parent, |
| 2468 | .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, |
| 2469 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2470 | .ops = &clkops_omap2_dflt, |
| 2471 | .recalc = &omap2_clksel_recalc, |
| 2472 | .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL, |
| 2473 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2474 | .clkdm_name = "abe_clkdm", |
| 2475 | }; |
| 2476 | |
| 2477 | /* Merged cm2_dm9_mux into timer9 */ |
| 2478 | static struct clk timer9_fck = { |
| 2479 | .name = "timer9_fck", |
| 2480 | .parent = &sys_clkin_ck, |
| 2481 | .clksel = abe_dpll_bypass_clk_mux_sel, |
| 2482 | .init = &omap2_init_clksel_parent, |
| 2483 | .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, |
| 2484 | .clksel_mask = OMAP4430_CLKSEL_MASK, |
| 2485 | .ops = &clkops_omap2_dflt, |
| 2486 | .recalc = &omap2_clksel_recalc, |
| 2487 | .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, |
| 2488 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2489 | .clkdm_name = "l4_per_clkdm", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2490 | }; |
| 2491 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2492 | static struct clk uart1_fck = { |
| 2493 | .name = "uart1_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2494 | .ops = &clkops_omap2_dflt, |
| 2495 | .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL, |
| 2496 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2497 | .clkdm_name = "l4_per_clkdm", |
| 2498 | .parent = &func_48m_fclk, |
| 2499 | .recalc = &followparent_recalc, |
| 2500 | }; |
| 2501 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2502 | static struct clk uart2_fck = { |
| 2503 | .name = "uart2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2504 | .ops = &clkops_omap2_dflt, |
| 2505 | .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL, |
| 2506 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2507 | .clkdm_name = "l4_per_clkdm", |
| 2508 | .parent = &func_48m_fclk, |
| 2509 | .recalc = &followparent_recalc, |
| 2510 | }; |
| 2511 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2512 | static struct clk uart3_fck = { |
| 2513 | .name = "uart3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2514 | .ops = &clkops_omap2_dflt, |
| 2515 | .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL, |
| 2516 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2517 | .clkdm_name = "l4_per_clkdm", |
| 2518 | .parent = &func_48m_fclk, |
| 2519 | .recalc = &followparent_recalc, |
| 2520 | }; |
| 2521 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2522 | static struct clk uart4_fck = { |
| 2523 | .name = "uart4_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2524 | .ops = &clkops_omap2_dflt, |
| 2525 | .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL, |
| 2526 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2527 | .clkdm_name = "l4_per_clkdm", |
| 2528 | .parent = &func_48m_fclk, |
| 2529 | .recalc = &followparent_recalc, |
| 2530 | }; |
| 2531 | |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 2532 | static struct clk usb_host_fs_fck = { |
| 2533 | .name = "usb_host_fs_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2534 | .ops = &clkops_omap2_dflt, |
| 2535 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, |
| 2536 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2537 | .clkdm_name = "l3_init_clkdm", |
| 2538 | .parent = &func_48mc_fclk, |
| 2539 | .recalc = &followparent_recalc, |
| 2540 | }; |
| 2541 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2542 | static const struct clksel utmi_p1_gfclk_sel[] = { |
| 2543 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, |
| 2544 | { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, |
| 2545 | { .parent = NULL }, |
| 2546 | }; |
| 2547 | |
| 2548 | static struct clk utmi_p1_gfclk = { |
| 2549 | .name = "utmi_p1_gfclk", |
| 2550 | .parent = &init_60m_fclk, |
| 2551 | .clksel = utmi_p1_gfclk_sel, |
| 2552 | .init = &omap2_init_clksel_parent, |
| 2553 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2554 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK, |
| 2555 | .ops = &clkops_null, |
| 2556 | .recalc = &omap2_clksel_recalc, |
| 2557 | }; |
| 2558 | |
| 2559 | static struct clk usb_host_hs_utmi_p1_clk = { |
| 2560 | .name = "usb_host_hs_utmi_p1_clk", |
| 2561 | .ops = &clkops_omap2_dflt, |
| 2562 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2563 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, |
| 2564 | .clkdm_name = "l3_init_clkdm", |
| 2565 | .parent = &utmi_p1_gfclk, |
| 2566 | .recalc = &followparent_recalc, |
| 2567 | }; |
| 2568 | |
| 2569 | static const struct clksel utmi_p2_gfclk_sel[] = { |
| 2570 | { .parent = &init_60m_fclk, .rates = div_1_0_rates }, |
| 2571 | { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates }, |
| 2572 | { .parent = NULL }, |
| 2573 | }; |
| 2574 | |
| 2575 | static struct clk utmi_p2_gfclk = { |
| 2576 | .name = "utmi_p2_gfclk", |
| 2577 | .parent = &init_60m_fclk, |
| 2578 | .clksel = utmi_p2_gfclk_sel, |
| 2579 | .init = &omap2_init_clksel_parent, |
| 2580 | .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2581 | .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK, |
| 2582 | .ops = &clkops_null, |
| 2583 | .recalc = &omap2_clksel_recalc, |
| 2584 | }; |
| 2585 | |
| 2586 | static struct clk usb_host_hs_utmi_p2_clk = { |
| 2587 | .name = "usb_host_hs_utmi_p2_clk", |
| 2588 | .ops = &clkops_omap2_dflt, |
| 2589 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2590 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, |
| 2591 | .clkdm_name = "l3_init_clkdm", |
| 2592 | .parent = &utmi_p2_gfclk, |
| 2593 | .recalc = &followparent_recalc, |
| 2594 | }; |
| 2595 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2596 | static struct clk usb_host_hs_utmi_p3_clk = { |
| 2597 | .name = "usb_host_hs_utmi_p3_clk", |
| 2598 | .ops = &clkops_omap2_dflt, |
| 2599 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2600 | .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, |
| 2601 | .clkdm_name = "l3_init_clkdm", |
| 2602 | .parent = &init_60m_fclk, |
| 2603 | .recalc = &followparent_recalc, |
| 2604 | }; |
| 2605 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2606 | static struct clk usb_host_hs_hsic480m_p1_clk = { |
| 2607 | .name = "usb_host_hs_hsic480m_p1_clk", |
| 2608 | .ops = &clkops_omap2_dflt, |
| 2609 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2610 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, |
| 2611 | .clkdm_name = "l3_init_clkdm", |
| 2612 | .parent = &dpll_usb_m2_ck, |
| 2613 | .recalc = &followparent_recalc, |
| 2614 | }; |
| 2615 | |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2616 | static struct clk usb_host_hs_hsic60m_p1_clk = { |
| 2617 | .name = "usb_host_hs_hsic60m_p1_clk", |
| 2618 | .ops = &clkops_omap2_dflt, |
| 2619 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2620 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, |
| 2621 | .clkdm_name = "l3_init_clkdm", |
| 2622 | .parent = &init_60m_fclk, |
| 2623 | .recalc = &followparent_recalc, |
| 2624 | }; |
| 2625 | |
| 2626 | static struct clk usb_host_hs_hsic60m_p2_clk = { |
| 2627 | .name = "usb_host_hs_hsic60m_p2_clk", |
| 2628 | .ops = &clkops_omap2_dflt, |
| 2629 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2630 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, |
| 2631 | .clkdm_name = "l3_init_clkdm", |
| 2632 | .parent = &init_60m_fclk, |
| 2633 | .recalc = &followparent_recalc, |
| 2634 | }; |
| 2635 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2636 | static struct clk usb_host_hs_hsic480m_p2_clk = { |
| 2637 | .name = "usb_host_hs_hsic480m_p2_clk", |
| 2638 | .ops = &clkops_omap2_dflt, |
| 2639 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2640 | .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, |
| 2641 | .clkdm_name = "l3_init_clkdm", |
| 2642 | .parent = &dpll_usb_m2_ck, |
| 2643 | .recalc = &followparent_recalc, |
| 2644 | }; |
| 2645 | |
| 2646 | static struct clk usb_host_hs_func48mclk = { |
| 2647 | .name = "usb_host_hs_func48mclk", |
| 2648 | .ops = &clkops_omap2_dflt, |
| 2649 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2650 | .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, |
| 2651 | .clkdm_name = "l3_init_clkdm", |
| 2652 | .parent = &func_48mc_fclk, |
| 2653 | .recalc = &followparent_recalc, |
| 2654 | }; |
| 2655 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2656 | static struct clk usb_host_hs_fck = { |
| 2657 | .name = "usb_host_hs_fck", |
| 2658 | .ops = &clkops_omap2_dflt, |
| 2659 | .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, |
| 2660 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2661 | .clkdm_name = "l3_init_clkdm", |
| 2662 | .parent = &init_60m_fclk, |
| 2663 | .recalc = &followparent_recalc, |
| 2664 | }; |
| 2665 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2666 | static const struct clksel otg_60m_gfclk_sel[] = { |
| 2667 | { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, |
| 2668 | { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, |
| 2669 | { .parent = NULL }, |
| 2670 | }; |
| 2671 | |
| 2672 | static struct clk otg_60m_gfclk = { |
| 2673 | .name = "otg_60m_gfclk", |
| 2674 | .parent = &utmi_phy_clkout_ck, |
| 2675 | .clksel = otg_60m_gfclk_sel, |
| 2676 | .init = &omap2_init_clksel_parent, |
| 2677 | .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
| 2678 | .clksel_mask = OMAP4430_CLKSEL_60M_MASK, |
| 2679 | .ops = &clkops_null, |
| 2680 | .recalc = &omap2_clksel_recalc, |
| 2681 | }; |
| 2682 | |
| 2683 | static struct clk usb_otg_hs_xclk = { |
| 2684 | .name = "usb_otg_hs_xclk", |
| 2685 | .ops = &clkops_omap2_dflt, |
| 2686 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
| 2687 | .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT, |
| 2688 | .clkdm_name = "l3_init_clkdm", |
| 2689 | .parent = &otg_60m_gfclk, |
| 2690 | .recalc = &followparent_recalc, |
| 2691 | }; |
| 2692 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2693 | static struct clk usb_otg_hs_ick = { |
| 2694 | .name = "usb_otg_hs_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2695 | .ops = &clkops_omap2_dflt, |
| 2696 | .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, |
| 2697 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2698 | .clkdm_name = "l3_init_clkdm", |
| 2699 | .parent = &l3_div_ck, |
| 2700 | .recalc = &followparent_recalc, |
| 2701 | }; |
| 2702 | |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2703 | static struct clk usb_phy_cm_clk32k = { |
| 2704 | .name = "usb_phy_cm_clk32k", |
| 2705 | .ops = &clkops_omap2_dflt, |
| 2706 | .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL, |
| 2707 | .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT, |
| 2708 | .clkdm_name = "l4_ao_clkdm", |
| 2709 | .parent = &sys_32k_ck, |
| 2710 | .recalc = &followparent_recalc, |
| 2711 | }; |
| 2712 | |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 2713 | static struct clk usb_tll_hs_usb_ch2_clk = { |
| 2714 | .name = "usb_tll_hs_usb_ch2_clk", |
| 2715 | .ops = &clkops_omap2_dflt, |
| 2716 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2717 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, |
| 2718 | .clkdm_name = "l3_init_clkdm", |
| 2719 | .parent = &init_60m_fclk, |
| 2720 | .recalc = &followparent_recalc, |
| 2721 | }; |
| 2722 | |
| 2723 | static struct clk usb_tll_hs_usb_ch0_clk = { |
| 2724 | .name = "usb_tll_hs_usb_ch0_clk", |
| 2725 | .ops = &clkops_omap2_dflt, |
| 2726 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2727 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, |
| 2728 | .clkdm_name = "l3_init_clkdm", |
| 2729 | .parent = &init_60m_fclk, |
| 2730 | .recalc = &followparent_recalc, |
| 2731 | }; |
| 2732 | |
| 2733 | static struct clk usb_tll_hs_usb_ch1_clk = { |
| 2734 | .name = "usb_tll_hs_usb_ch1_clk", |
| 2735 | .ops = &clkops_omap2_dflt, |
| 2736 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2737 | .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, |
| 2738 | .clkdm_name = "l3_init_clkdm", |
| 2739 | .parent = &init_60m_fclk, |
| 2740 | .recalc = &followparent_recalc, |
| 2741 | }; |
| 2742 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2743 | static struct clk usb_tll_hs_ick = { |
| 2744 | .name = "usb_tll_hs_ick", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2745 | .ops = &clkops_omap2_dflt, |
| 2746 | .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, |
| 2747 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
| 2748 | .clkdm_name = "l3_init_clkdm", |
| 2749 | .parent = &l4_div_ck, |
| 2750 | .recalc = &followparent_recalc, |
| 2751 | }; |
| 2752 | |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2753 | static const struct clksel_rate div2_14to18_rates[] = { |
| 2754 | { .div = 14, .val = 0, .flags = RATE_IN_4430 }, |
| 2755 | { .div = 18, .val = 1, .flags = RATE_IN_4430 }, |
| 2756 | { .div = 0 }, |
| 2757 | }; |
| 2758 | |
| 2759 | static const struct clksel usim_fclk_div[] = { |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2760 | { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates }, |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2761 | { .parent = NULL }, |
| 2762 | }; |
| 2763 | |
| 2764 | static struct clk usim_ck = { |
| 2765 | .name = "usim_ck", |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 2766 | .parent = &dpll_per_m4x2_ck, |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 2767 | .clksel = usim_fclk_div, |
| 2768 | .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
| 2769 | .clksel_mask = OMAP4430_CLKSEL_DIV_MASK, |
| 2770 | .ops = &clkops_null, |
| 2771 | .recalc = &omap2_clksel_recalc, |
| 2772 | .round_rate = &omap2_clksel_round_rate, |
| 2773 | .set_rate = &omap2_clksel_set_rate, |
| 2774 | }; |
| 2775 | |
| 2776 | static struct clk usim_fclk = { |
| 2777 | .name = "usim_fclk", |
| 2778 | .ops = &clkops_omap2_dflt, |
| 2779 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
| 2780 | .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT, |
| 2781 | .clkdm_name = "l4_wkup_clkdm", |
| 2782 | .parent = &usim_ck, |
| 2783 | .recalc = &followparent_recalc, |
| 2784 | }; |
| 2785 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2786 | static struct clk usim_fck = { |
| 2787 | .name = "usim_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2788 | .ops = &clkops_omap2_dflt, |
| 2789 | .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2790 | .enable_bit = OMAP4430_MODULEMODE_HWCTRL, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2791 | .clkdm_name = "l4_wkup_clkdm", |
| 2792 | .parent = &sys_32k_ck, |
| 2793 | .recalc = &followparent_recalc, |
| 2794 | }; |
| 2795 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2796 | static struct clk wd_timer2_fck = { |
| 2797 | .name = "wd_timer2_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2798 | .ops = &clkops_omap2_dflt, |
| 2799 | .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, |
| 2800 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2801 | .clkdm_name = "l4_wkup_clkdm", |
| 2802 | .parent = &sys_32k_ck, |
| 2803 | .recalc = &followparent_recalc, |
| 2804 | }; |
| 2805 | |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 2806 | static struct clk wd_timer3_fck = { |
| 2807 | .name = "wd_timer3_fck", |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2808 | .ops = &clkops_omap2_dflt, |
| 2809 | .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, |
| 2810 | .enable_bit = OMAP4430_MODULEMODE_SWCTRL, |
| 2811 | .clkdm_name = "abe_clkdm", |
| 2812 | .parent = &sys_32k_ck, |
| 2813 | .recalc = &followparent_recalc, |
| 2814 | }; |
| 2815 | |
| 2816 | /* Remaining optional clocks */ |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2817 | static const struct clksel stm_clk_div_div[] = { |
| 2818 | { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, |
| 2819 | { .parent = NULL }, |
| 2820 | }; |
| 2821 | |
| 2822 | static struct clk stm_clk_div_ck = { |
| 2823 | .name = "stm_clk_div_ck", |
| 2824 | .parent = &pmd_stm_clock_mux_ck, |
| 2825 | .clksel = stm_clk_div_div, |
| 2826 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, |
| 2827 | .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, |
| 2828 | .ops = &clkops_null, |
| 2829 | .recalc = &omap2_clksel_recalc, |
| 2830 | .round_rate = &omap2_clksel_round_rate, |
| 2831 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2832 | }; |
| 2833 | |
| 2834 | static const struct clksel trace_clk_div_div[] = { |
| 2835 | { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, |
| 2836 | { .parent = NULL }, |
| 2837 | }; |
| 2838 | |
| 2839 | static struct clk trace_clk_div_ck = { |
| 2840 | .name = "trace_clk_div_ck", |
| 2841 | .parent = &pmd_trace_clk_mux_ck, |
| 2842 | .clksel = trace_clk_div_div, |
| 2843 | .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, |
| 2844 | .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, |
| 2845 | .ops = &clkops_null, |
| 2846 | .recalc = &omap2_clksel_recalc, |
| 2847 | .round_rate = &omap2_clksel_round_rate, |
| 2848 | .set_rate = &omap2_clksel_set_rate, |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 2849 | }; |
| 2850 | |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 2851 | /* SCRM aux clk nodes */ |
| 2852 | |
| 2853 | static const struct clksel auxclk_sel[] = { |
| 2854 | { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, |
| 2855 | { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates }, |
| 2856 | { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates }, |
| 2857 | { .parent = NULL }, |
| 2858 | }; |
| 2859 | |
| 2860 | static struct clk auxclk0_ck = { |
| 2861 | .name = "auxclk0_ck", |
| 2862 | .parent = &sys_clkin_ck, |
| 2863 | .init = &omap2_init_clksel_parent, |
| 2864 | .ops = &clkops_omap2_dflt, |
| 2865 | .clksel = auxclk_sel, |
| 2866 | .clksel_reg = OMAP4_SCRM_AUXCLK0, |
| 2867 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2868 | .recalc = &omap2_clksel_recalc, |
| 2869 | .enable_reg = OMAP4_SCRM_AUXCLK0, |
| 2870 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2871 | }; |
| 2872 | |
| 2873 | static struct clk auxclk1_ck = { |
| 2874 | .name = "auxclk1_ck", |
| 2875 | .parent = &sys_clkin_ck, |
| 2876 | .init = &omap2_init_clksel_parent, |
| 2877 | .ops = &clkops_omap2_dflt, |
| 2878 | .clksel = auxclk_sel, |
| 2879 | .clksel_reg = OMAP4_SCRM_AUXCLK1, |
| 2880 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2881 | .recalc = &omap2_clksel_recalc, |
| 2882 | .enable_reg = OMAP4_SCRM_AUXCLK1, |
| 2883 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2884 | }; |
| 2885 | |
| 2886 | static struct clk auxclk2_ck = { |
| 2887 | .name = "auxclk2_ck", |
| 2888 | .parent = &sys_clkin_ck, |
| 2889 | .init = &omap2_init_clksel_parent, |
| 2890 | .ops = &clkops_omap2_dflt, |
| 2891 | .clksel = auxclk_sel, |
| 2892 | .clksel_reg = OMAP4_SCRM_AUXCLK2, |
| 2893 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2894 | .recalc = &omap2_clksel_recalc, |
| 2895 | .enable_reg = OMAP4_SCRM_AUXCLK2, |
| 2896 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2897 | }; |
| 2898 | static struct clk auxclk3_ck = { |
| 2899 | .name = "auxclk3_ck", |
| 2900 | .parent = &sys_clkin_ck, |
| 2901 | .init = &omap2_init_clksel_parent, |
| 2902 | .ops = &clkops_omap2_dflt, |
| 2903 | .clksel = auxclk_sel, |
| 2904 | .clksel_reg = OMAP4_SCRM_AUXCLK3, |
| 2905 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2906 | .recalc = &omap2_clksel_recalc, |
| 2907 | .enable_reg = OMAP4_SCRM_AUXCLK3, |
| 2908 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2909 | }; |
| 2910 | |
| 2911 | static struct clk auxclk4_ck = { |
| 2912 | .name = "auxclk4_ck", |
| 2913 | .parent = &sys_clkin_ck, |
| 2914 | .init = &omap2_init_clksel_parent, |
| 2915 | .ops = &clkops_omap2_dflt, |
| 2916 | .clksel = auxclk_sel, |
| 2917 | .clksel_reg = OMAP4_SCRM_AUXCLK4, |
| 2918 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2919 | .recalc = &omap2_clksel_recalc, |
| 2920 | .enable_reg = OMAP4_SCRM_AUXCLK4, |
| 2921 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2922 | }; |
| 2923 | |
| 2924 | static struct clk auxclk5_ck = { |
| 2925 | .name = "auxclk5_ck", |
| 2926 | .parent = &sys_clkin_ck, |
| 2927 | .init = &omap2_init_clksel_parent, |
| 2928 | .ops = &clkops_omap2_dflt, |
| 2929 | .clksel = auxclk_sel, |
| 2930 | .clksel_reg = OMAP4_SCRM_AUXCLK5, |
| 2931 | .clksel_mask = OMAP4_SRCSELECT_MASK, |
| 2932 | .recalc = &omap2_clksel_recalc, |
| 2933 | .enable_reg = OMAP4_SCRM_AUXCLK5, |
| 2934 | .enable_bit = OMAP4_ENABLE_SHIFT, |
| 2935 | }; |
| 2936 | |
| 2937 | static const struct clksel auxclkreq_sel[] = { |
| 2938 | { .parent = &auxclk0_ck, .rates = div_1_0_rates }, |
| 2939 | { .parent = &auxclk1_ck, .rates = div_1_1_rates }, |
| 2940 | { .parent = &auxclk2_ck, .rates = div_1_2_rates }, |
| 2941 | { .parent = &auxclk3_ck, .rates = div_1_3_rates }, |
| 2942 | { .parent = &auxclk4_ck, .rates = div_1_4_rates }, |
| 2943 | { .parent = &auxclk5_ck, .rates = div_1_5_rates }, |
| 2944 | { .parent = NULL }, |
| 2945 | }; |
| 2946 | |
| 2947 | static struct clk auxclkreq0_ck = { |
| 2948 | .name = "auxclkreq0_ck", |
| 2949 | .parent = &auxclk0_ck, |
| 2950 | .init = &omap2_init_clksel_parent, |
| 2951 | .ops = &clkops_null, |
| 2952 | .clksel = auxclkreq_sel, |
| 2953 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ0, |
| 2954 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 2955 | .recalc = &omap2_clksel_recalc, |
| 2956 | }; |
| 2957 | |
| 2958 | static struct clk auxclkreq1_ck = { |
| 2959 | .name = "auxclkreq1_ck", |
| 2960 | .parent = &auxclk1_ck, |
| 2961 | .init = &omap2_init_clksel_parent, |
| 2962 | .ops = &clkops_null, |
| 2963 | .clksel = auxclkreq_sel, |
| 2964 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ1, |
| 2965 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 2966 | .recalc = &omap2_clksel_recalc, |
| 2967 | }; |
| 2968 | |
| 2969 | static struct clk auxclkreq2_ck = { |
| 2970 | .name = "auxclkreq2_ck", |
| 2971 | .parent = &auxclk2_ck, |
| 2972 | .init = &omap2_init_clksel_parent, |
| 2973 | .ops = &clkops_null, |
| 2974 | .clksel = auxclkreq_sel, |
| 2975 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ2, |
| 2976 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 2977 | .recalc = &omap2_clksel_recalc, |
| 2978 | }; |
| 2979 | |
| 2980 | static struct clk auxclkreq3_ck = { |
| 2981 | .name = "auxclkreq3_ck", |
| 2982 | .parent = &auxclk3_ck, |
| 2983 | .init = &omap2_init_clksel_parent, |
| 2984 | .ops = &clkops_null, |
| 2985 | .clksel = auxclkreq_sel, |
| 2986 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ3, |
| 2987 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 2988 | .recalc = &omap2_clksel_recalc, |
| 2989 | }; |
| 2990 | |
| 2991 | static struct clk auxclkreq4_ck = { |
| 2992 | .name = "auxclkreq4_ck", |
| 2993 | .parent = &auxclk4_ck, |
| 2994 | .init = &omap2_init_clksel_parent, |
| 2995 | .ops = &clkops_null, |
| 2996 | .clksel = auxclkreq_sel, |
| 2997 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ4, |
| 2998 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 2999 | .recalc = &omap2_clksel_recalc, |
| 3000 | }; |
| 3001 | |
| 3002 | static struct clk auxclkreq5_ck = { |
| 3003 | .name = "auxclkreq5_ck", |
| 3004 | .parent = &auxclk5_ck, |
| 3005 | .init = &omap2_init_clksel_parent, |
| 3006 | .ops = &clkops_null, |
| 3007 | .clksel = auxclkreq_sel, |
| 3008 | .clksel_reg = OMAP4_SCRM_AUXCLKREQ5, |
| 3009 | .clksel_mask = OMAP4_MAPPING_MASK, |
| 3010 | .recalc = &omap2_clksel_recalc, |
| 3011 | }; |
| 3012 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3013 | /* |
| 3014 | * clkdev |
| 3015 | */ |
| 3016 | |
| 3017 | static struct omap_clk omap44xx_clks[] = { |
| 3018 | CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X), |
| 3019 | CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X), |
| 3020 | CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X), |
| 3021 | CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X), |
| 3022 | CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X), |
| 3023 | CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X), |
| 3024 | CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X), |
| 3025 | CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X), |
| 3026 | CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X), |
| 3027 | CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X), |
| 3028 | CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X), |
| 3029 | CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), |
| 3030 | CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), |
| 3031 | CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3032 | CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3033 | CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), |
| 3034 | CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), |
| 3035 | CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), |
| 3036 | CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), |
Rajendra Nayak | 76cf529 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3037 | CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3038 | CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), |
| 3039 | CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3040 | CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3041 | CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), |
| 3042 | CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X), |
| 3043 | CLK(NULL, "abe_clk", &abe_clk, CK_443X), |
| 3044 | CLK(NULL, "aess_fclk", &aess_fclk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3045 | CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3046 | CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X), |
| 3047 | CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3048 | CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X), |
| 3049 | CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3050 | CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X), |
| 3051 | CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X), |
| 3052 | CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3053 | CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3054 | CLK(NULL, "div_core_ck", &div_core_ck, CK_443X), |
| 3055 | CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X), |
| 3056 | CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3057 | CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3058 | CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X), |
| 3059 | CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3060 | CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X), |
| 3061 | CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3062 | CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X), |
| 3063 | CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3064 | CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X), |
| 3065 | CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X), |
| 3066 | CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3067 | CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X), |
| 3068 | CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X), |
| 3069 | CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X), |
| 3070 | CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X), |
| 3071 | CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X), |
| 3072 | CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3073 | CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3074 | CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3075 | CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X), |
| 3076 | CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X), |
| 3077 | CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X), |
| 3078 | CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X), |
| 3079 | CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3080 | CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3081 | CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3082 | CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X), |
| 3083 | CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X), |
| 3084 | CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X), |
| 3085 | CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X), |
| 3086 | CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X), |
| 3087 | CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X), |
| 3088 | CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X), |
| 3089 | CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X), |
| 3090 | CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X), |
| 3091 | CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X), |
| 3092 | CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X), |
| 3093 | CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X), |
| 3094 | CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X), |
| 3095 | CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X), |
| 3096 | CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X), |
| 3097 | CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X), |
| 3098 | CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X), |
| 3099 | CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X), |
| 3100 | CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X), |
| 3101 | CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X), |
| 3102 | CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X), |
| 3103 | CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X), |
| 3104 | CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X), |
| 3105 | CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X), |
| 3106 | CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X), |
| 3107 | CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X), |
| 3108 | CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3109 | CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), |
| 3110 | CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), |
| 3111 | CLK(NULL, "aess_fck", &aess_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3112 | CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3113 | CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3114 | CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3115 | CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3116 | CLK(NULL, "dsp_fck", &dsp_fck, CK_443X), |
Sumit Semwal | 872462c | 2011-01-31 16:27:43 +0000 | [diff] [blame] | 3117 | CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X), |
| 3118 | CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X), |
| 3119 | CLK("omapdss_dss", "dss_clk", &dss_dss_clk, CK_443X), |
| 3120 | CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X), |
| 3121 | CLK("omapdss_dss", "fck", &dss_fck, CK_443X), |
Sumit Semwal | f38190d | 2011-01-31 16:27:46 +0000 | [diff] [blame] | 3122 | /* |
| 3123 | * On OMAP4, DSS ick is a dummy clock; this is needed for compatibility |
| 3124 | * with OMAP2/3. |
| 3125 | */ |
| 3126 | CLK("omapdss_dss", "ick", &dummy_ck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3127 | CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X), |
| 3128 | CLK(NULL, "emif1_fck", &emif1_fck, CK_443X), |
| 3129 | CLK(NULL, "emif2_fck", &emif2_fck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3130 | CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3131 | CLK(NULL, "fpka_fck", &fpka_fck, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3132 | CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3133 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3134 | CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3135 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3136 | CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3137 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3138 | CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3139 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3140 | CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3141 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 3142 | CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3143 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), |
| 3144 | CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3145 | CLK(NULL, "gpu_fck", &gpu_fck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3146 | CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3147 | CLK(NULL, "hsi_fck", &hsi_fck, CK_443X), |
Benoit Cousson | f7bb0d9 | 2010-12-09 14:24:16 +0000 | [diff] [blame] | 3148 | CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X), |
| 3149 | CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X), |
| 3150 | CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X), |
| 3151 | CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3152 | CLK(NULL, "ipu_fck", &ipu_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3153 | CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3154 | CLK(NULL, "iss_fck", &iss_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3155 | CLK(NULL, "iva_fck", &iva_fck, CK_443X), |
| 3156 | CLK(NULL, "kbd_fck", &kbd_fck, CK_443X), |
| 3157 | CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X), |
| 3158 | CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3159 | CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3160 | CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3161 | CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3162 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3163 | CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3164 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3165 | CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3166 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3167 | CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3168 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3169 | CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3170 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), |
| 3171 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), |
| 3172 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), |
| 3173 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 3174 | CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X), |
| 3175 | CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X), |
| 3176 | CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X), |
| 3177 | CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X), |
| 3178 | CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3179 | CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 3180 | CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3181 | CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3182 | CLK("omap_rng", "ick", &rng_ick, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3183 | CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X), |
| 3184 | CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3185 | CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X), |
| 3186 | CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X), |
| 3187 | CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X), |
| 3188 | CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3189 | CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3190 | CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X), |
| 3191 | CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X), |
| 3192 | CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3193 | CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3194 | CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), |
| 3195 | CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), |
| 3196 | CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), |
| 3197 | CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), |
| 3198 | CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), |
| 3199 | CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), |
| 3200 | CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), |
| 3201 | CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), |
| 3202 | CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), |
| 3203 | CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), |
| 3204 | CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), |
| 3205 | CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), |
| 3206 | CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), |
| 3207 | CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3208 | CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), |
| 3209 | CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), |
| 3210 | CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), |
| 3211 | CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), |
Rajendra Nayak | 5477605 | 2010-02-22 22:09:39 -0700 | [diff] [blame] | 3212 | CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), |
Keshava Munegowda | 53689ac | 2011-03-01 20:08:22 +0530 | [diff] [blame] | 3213 | CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3214 | CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X), |
| 3215 | CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X), |
| 3216 | CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X), |
| 3217 | CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3218 | CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3219 | CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X), |
Thara Gopinath | 032b5a7 | 2010-12-21 21:08:13 -0700 | [diff] [blame] | 3220 | CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X), |
| 3221 | CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3222 | CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X), |
| 3223 | CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3224 | CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X), |
Keshava Munegowda | 53689ac | 2011-03-01 20:08:22 +0530 | [diff] [blame] | 3225 | CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X), |
| 3226 | CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3227 | CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X), |
| 3228 | CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X), |
Felipe Balbi | 0349176 | 2010-12-02 09:57:08 +0200 | [diff] [blame] | 3229 | CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X), |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 3230 | CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X), |
Benoit Cousson | 1c03f42 | 2010-09-27 14:02:55 -0600 | [diff] [blame] | 3231 | CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X), |
| 3232 | CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X), |
| 3233 | CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3234 | CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X), |
Keshava Munegowda | 53689ac | 2011-03-01 20:08:22 +0530 | [diff] [blame] | 3235 | CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X), |
| 3236 | CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X), |
Benoit Cousson | 0edc9e8 | 2010-09-27 14:02:56 -0600 | [diff] [blame] | 3237 | CLK(NULL, "usim_ck", &usim_ck, CK_443X), |
| 3238 | CLK(NULL, "usim_fclk", &usim_fclk, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3239 | CLK(NULL, "usim_fck", &usim_fck, CK_443X), |
| 3240 | CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X), |
Hari Kanigeri | 0a01aa2 | 2010-12-21 21:18:56 -0700 | [diff] [blame] | 3241 | CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3242 | CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3243 | CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), |
| 3244 | CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 3245 | CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), |
| 3246 | CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), |
| 3247 | CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), |
| 3248 | CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X), |
| 3249 | CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X), |
| 3250 | CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X), |
| 3251 | CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X), |
| 3252 | CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X), |
| 3253 | CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X), |
| 3254 | CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X), |
| 3255 | CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X), |
| 3256 | CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X), |
Benoit Cousson | f7bb0d9 | 2010-12-09 14:24:16 +0000 | [diff] [blame] | 3257 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X), |
| 3258 | CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), |
| 3259 | CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), |
| 3260 | CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), |
Kishore Kadiyala | 0005ae7 | 2011-02-28 20:48:05 +0530 | [diff] [blame] | 3261 | CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X), |
| 3262 | CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X), |
| 3263 | CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X), |
| 3264 | CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X), |
| 3265 | CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X), |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 3266 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), |
| 3267 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), |
| 3268 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), |
| 3269 | CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), |
Benoit Cousson | 0e43327 | 2010-09-27 14:02:54 -0600 | [diff] [blame] | 3270 | CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), |
| 3271 | CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), |
| 3272 | CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), |
| 3273 | CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), |
Santosh Shilimkar | 7c43d54 | 2010-02-22 22:09:40 -0700 | [diff] [blame] | 3274 | CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), |
| 3275 | CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), |
| 3276 | CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), |
| 3277 | CLK(NULL, "uart4_ick", &dummy_ck, CK_443X), |
| 3278 | CLK("omap_wdt", "ick", &dummy_ck, CK_443X), |
Rajendra Nayak | e0cb70c | 2010-12-21 21:08:14 -0700 | [diff] [blame] | 3279 | CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X), |
| 3280 | CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X), |
| 3281 | CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X), |
| 3282 | CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X), |
| 3283 | CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X), |
| 3284 | CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X), |
| 3285 | CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X), |
| 3286 | CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X), |
| 3287 | CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X), |
| 3288 | CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X), |
| 3289 | CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X), |
| 3290 | CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X), |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3291 | }; |
| 3292 | |
Paul Walmsley | e80a972 | 2010-01-26 20:13:12 -0700 | [diff] [blame] | 3293 | int __init omap4xxx_clk_init(void) |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3294 | { |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3295 | struct omap_clk *c; |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3296 | u32 cpu_clkflg; |
| 3297 | |
| 3298 | if (cpu_is_omap44xx()) { |
| 3299 | cpu_mask = RATE_IN_4430; |
| 3300 | cpu_clkflg = CK_443X; |
| 3301 | } |
| 3302 | |
| 3303 | clk_init(&omap2_clk_functions); |
| 3304 | |
| 3305 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); |
| 3306 | c++) |
| 3307 | clk_preinit(c->lk.clk); |
| 3308 | |
| 3309 | for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks); |
| 3310 | c++) |
| 3311 | if (c->cpu & cpu_clkflg) { |
| 3312 | clkdev_add(&c->lk); |
| 3313 | clk_register(c->lk.clk); |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3314 | omap2_init_clk_clkdm(c->lk.clk); |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3315 | } |
| 3316 | |
Paul Walmsley | c6461f5 | 2011-02-25 15:49:53 -0700 | [diff] [blame] | 3317 | /* Disable autoidle on all clocks; let the PM code enable it later */ |
| 3318 | omap_clk_disable_autoidle_all(); |
| 3319 | |
Rajendra Nayak | 972c542 | 2009-12-08 18:46:28 -0700 | [diff] [blame] | 3320 | recalculate_root_clocks(); |
| 3321 | |
| 3322 | /* |
| 3323 | * Only enable those clocks we will need, let the drivers |
| 3324 | * enable other clocks as necessary |
| 3325 | */ |
| 3326 | clk_enable_init_clocks(); |
| 3327 | |
| 3328 | return 0; |
| 3329 | } |