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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 13765de8148f71fa795e0a6607de37c49ea5915a / . / arch / arm / mach-omap2 / prm44xx.h
blob: fc7d4ed0bd9b8296747dd2377ef1f7947fc6ce2b [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]2/*
3 * OMAP44xx PRM instance offset macros
4 *
Paul Walmsley26c98c52011-12-16 14:36:58 -0700[diff] [blame]5 * Copyright (C) 2009-2011 Texas Instruments, Inc.
Benoit Cousson79328702010-05-20 12:31:11 -0600[diff] [blame]6 * Copyright (C) 2009-2010 Nokia Corporation
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]7 *
8 * Paul Walmsley (paul@pwsan.com)
9 * Rajendra Nayak (rnayak@ti.com)
10 * Benoit Cousson (b-cousson@ti.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]18 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
19 * or "OMAP4430".
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
24
Santosh Shilimkar9920eca2013-05-29 12:38:01 -0400[diff] [blame]25#include "prm44xx_54xx.h"
Paul Walmsley59fb6592010-12-21 15:30:55 -0700[diff] [blame]26#include "prm.h"
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]27
28#define OMAP4430_PRM_BASE 0x4a306000
29
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]30#define OMAP44XX_PRM_REGADDR(inst, reg) \
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]32
33
34/* PRM instances */
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]35#define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36#define OMAP4430_PRM_CKGEN_INST 0x0100
37#define OMAP4430_PRM_MPU_INST 0x0300
38#define OMAP4430_PRM_TESLA_INST 0x0400
39#define OMAP4430_PRM_ABE_INST 0x0500
40#define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41#define OMAP4430_PRM_CORE_INST 0x0700
42#define OMAP4430_PRM_IVAHD_INST 0x0f00
43#define OMAP4430_PRM_CAM_INST 0x1000
44#define OMAP4430_PRM_DSS_INST 0x1100
45#define OMAP4430_PRM_GFX_INST 0x1200
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]46#define OMAP4430_PRM_L3INIT_INST 0x1300
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]47#define OMAP4430_PRM_L4PER_INST 0x1400
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]48#define OMAP4430_PRM_CEFUSE_INST 0x1600
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]49#define OMAP4430_PRM_WKUP_INST 0x1700
50#define OMAP4430_PRM_WKUP_CM_INST 0x1800
51#define OMAP4430_PRM_EMU_INST 0x1900
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]52#define OMAP4430_PRM_EMU_CM_INST 0x1a00
53#define OMAP4430_PRM_DEVICE_INST 0x1b00
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]54
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]55/* PRM clockdomain register offsets (from instance start) */
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]56#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
Paul Walmsleye4156ee2010-12-21 21:05:15 -0700[diff] [blame]57#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]58
59/* OMAP4 specific register offsets */
Nishanth Menon5f2596f2012-12-28 02:09:45 -0700[diff] [blame]60#define OMAP4_RM_RSTST 0x0004
Paul Walmsleyd198b512010-12-21 15:30:54 -0700[diff] [blame]61#define OMAP4_PM_PWSTCTRL 0x0000
62#define OMAP4_PM_PWSTST 0x0004
63
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]64/* PRM.OCP_SOCKET_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]65#define OMAP4_REVISION_PRM_OFFSET 0x0000
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]66#define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]67#define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010)
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]68#define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]69#define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018
Paul Walmsleycdb54c42010-12-21 15:30:55 -0700[diff] [blame]70#define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018)
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]71
72/* PRM.MPU_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]73#define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]74
75/* PRM.DEVICE_PRM register offsets */
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]76#define OMAP4_PRM_RSTCTRL_OFFSET 0x0000
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]77#define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]78#define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]79#define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]80#define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]81#define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]82#define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]83#define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]84#define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]85#define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]86#define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]87#define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]88#define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]89#define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]90#define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]91#define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]92#define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]93#define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]94#define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]95#define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]96#define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]97#define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]98#define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]99#define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]100#define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]101#define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]102#define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]103#define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]104#define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]105#define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]106#define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]107#define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]108#define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]109#define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]110#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
Benoit Coussonad98a182011-07-09 19:15:04 -0600[diff] [blame]111#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
Rajendra Nayak2339ea92010-05-20 12:31:12 -0600[diff] [blame]112#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]113
Rajendra Nayakc1294042009-12-08 18:24:51 -0700[diff] [blame]114#endif