Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 2 | #include "tegra20.dtsi" |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 3 | |
| 4 | / { |
| 5 | model = "Avionic Design Tamonten SOM"; |
| 6 | compatible = "ad,tamonten", "nvidia,tegra20"; |
| 7 | |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 8 | aliases { |
| 9 | rtc0 = "/i2c@7000d000/tps6586x@34"; |
| 10 | rtc1 = "/rtc@7000e000"; |
Olof Johansson | c4574aa | 2014-11-11 12:49:30 -0800 | [diff] [blame] | 11 | serial0 = &uartd; |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 12 | }; |
| 13 | |
Jon Hunter | f5bbb32 | 2016-02-09 13:51:59 +0000 | [diff] [blame] | 14 | chosen { |
| 15 | stdout-path = "serial0:115200n8"; |
| 16 | }; |
| 17 | |
Krzysztof Kozlowski | 4829976 | 2018-07-09 18:05:17 +0200 | [diff] [blame] | 18 | memory@0 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 19 | reg = <0x00000000 0x20000000>; |
| 20 | }; |
| 21 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 22 | host1x@50000000 { |
| 23 | hdmi@54280000 { |
Thierry Reding | e6f0979 | 2012-11-16 16:56:50 +0100 | [diff] [blame] | 24 | vdd-supply = <&hdmi_vdd_reg>; |
| 25 | pll-supply = <&hdmi_pll_reg>; |
| 26 | |
| 27 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 28 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 29 | GPIO_ACTIVE_HIGH>; |
Thierry Reding | e6f0979 | 2012-11-16 16:56:50 +0100 | [diff] [blame] | 30 | }; |
| 31 | }; |
| 32 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 33 | pinmux@70000014 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 34 | pinctrl-names = "default"; |
| 35 | pinctrl-0 = <&state_default>; |
| 36 | |
| 37 | state_default: pinmux { |
| 38 | ata { |
| 39 | nvidia,pins = "ata"; |
| 40 | nvidia,function = "ide"; |
| 41 | }; |
| 42 | atb { |
| 43 | nvidia,pins = "atb", "gma", "gme"; |
| 44 | nvidia,function = "sdio4"; |
| 45 | }; |
| 46 | atc { |
| 47 | nvidia,pins = "atc"; |
| 48 | nvidia,function = "nand"; |
| 49 | }; |
| 50 | atd { |
| 51 | nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", |
| 52 | "spia", "spib", "spic"; |
| 53 | nvidia,function = "gmi"; |
| 54 | }; |
| 55 | cdev1 { |
| 56 | nvidia,pins = "cdev1"; |
| 57 | nvidia,function = "plla_out"; |
| 58 | }; |
| 59 | cdev2 { |
| 60 | nvidia,pins = "cdev2"; |
| 61 | nvidia,function = "pllp_out4"; |
| 62 | }; |
| 63 | crtp { |
| 64 | nvidia,pins = "crtp"; |
| 65 | nvidia,function = "crt"; |
| 66 | }; |
| 67 | csus { |
| 68 | nvidia,pins = "csus"; |
| 69 | nvidia,function = "vi_sensor_clk"; |
| 70 | }; |
| 71 | dap1 { |
| 72 | nvidia,pins = "dap1"; |
| 73 | nvidia,function = "dap1"; |
| 74 | }; |
| 75 | dap2 { |
| 76 | nvidia,pins = "dap2"; |
| 77 | nvidia,function = "dap2"; |
| 78 | }; |
| 79 | dap3 { |
| 80 | nvidia,pins = "dap3"; |
| 81 | nvidia,function = "dap3"; |
| 82 | }; |
| 83 | dap4 { |
| 84 | nvidia,pins = "dap4"; |
| 85 | nvidia,function = "dap4"; |
| 86 | }; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 87 | dta { |
| 88 | nvidia,pins = "dta", "dtd"; |
| 89 | nvidia,function = "sdio2"; |
| 90 | }; |
| 91 | dtb { |
| 92 | nvidia,pins = "dtb", "dtc", "dte"; |
| 93 | nvidia,function = "rsvd1"; |
| 94 | }; |
| 95 | dtf { |
| 96 | nvidia,pins = "dtf"; |
| 97 | nvidia,function = "i2c3"; |
| 98 | }; |
| 99 | gmc { |
| 100 | nvidia,pins = "gmc"; |
| 101 | nvidia,function = "uartd"; |
| 102 | }; |
| 103 | gpu7 { |
| 104 | nvidia,pins = "gpu7"; |
| 105 | nvidia,function = "rtck"; |
| 106 | }; |
| 107 | gpv { |
| 108 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 109 | nvidia,function = "pcie"; |
| 110 | }; |
| 111 | hdint { |
Thierry Reding | ec31990 | 2012-11-09 14:04:50 +0100 | [diff] [blame] | 112 | nvidia,pins = "hdint"; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 113 | nvidia,function = "hdmi"; |
| 114 | }; |
| 115 | i2cp { |
| 116 | nvidia,pins = "i2cp"; |
| 117 | nvidia,function = "i2cp"; |
| 118 | }; |
| 119 | irrx { |
| 120 | nvidia,pins = "irrx", "irtx"; |
| 121 | nvidia,function = "uarta"; |
| 122 | }; |
| 123 | kbca { |
| 124 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 125 | "kbce", "kbcf"; |
| 126 | nvidia,function = "kbc"; |
| 127 | }; |
| 128 | lcsn { |
| 129 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", |
| 130 | "ld3", "ld4", "ld5", "ld6", "ld7", |
| 131 | "ld8", "ld9", "ld10", "ld11", "ld12", |
| 132 | "ld13", "ld14", "ld15", "ld16", "ld17", |
| 133 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", |
| 134 | "lhs", "lm0", "lm1", "lpp", "lpw0", |
| 135 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", |
| 136 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", |
| 137 | "lvs"; |
| 138 | nvidia,function = "displaya"; |
| 139 | }; |
| 140 | owc { |
| 141 | nvidia,pins = "owc", "spdi", "spdo", "uac"; |
| 142 | nvidia,function = "rsvd2"; |
| 143 | }; |
| 144 | pmc { |
| 145 | nvidia,pins = "pmc"; |
| 146 | nvidia,function = "pwr_on"; |
| 147 | }; |
| 148 | rm { |
| 149 | nvidia,pins = "rm"; |
| 150 | nvidia,function = "i2c1"; |
| 151 | }; |
| 152 | sdb { |
| 153 | nvidia,pins = "sdb", "sdc", "sdd"; |
| 154 | nvidia,function = "pwm"; |
| 155 | }; |
| 156 | sdio1 { |
| 157 | nvidia,pins = "sdio1"; |
| 158 | nvidia,function = "sdio1"; |
| 159 | }; |
| 160 | slxc { |
| 161 | nvidia,pins = "slxc", "slxd"; |
| 162 | nvidia,function = "spdif"; |
| 163 | }; |
| 164 | spid { |
| 165 | nvidia,pins = "spid", "spie", "spif"; |
| 166 | nvidia,function = "spi1"; |
| 167 | }; |
| 168 | spig { |
| 169 | nvidia,pins = "spig", "spih"; |
| 170 | nvidia,function = "spi2_alt"; |
| 171 | }; |
| 172 | uaa { |
| 173 | nvidia,pins = "uaa", "uab", "uda"; |
| 174 | nvidia,function = "ulpi"; |
| 175 | }; |
| 176 | uad { |
| 177 | nvidia,pins = "uad"; |
| 178 | nvidia,function = "irda"; |
| 179 | }; |
| 180 | uca { |
| 181 | nvidia,pins = "uca", "ucb"; |
| 182 | nvidia,function = "uartc"; |
| 183 | }; |
| 184 | conf_ata { |
| 185 | nvidia,pins = "ata", "atb", "atc", "atd", "ate", |
| 186 | "cdev1", "cdev2", "dap1", "dtb", "gma", |
| 187 | "gmb", "gmc", "gmd", "gme", "gpu7", |
Andreas Obergschwandtner | 2270ad2 | 2021-07-29 16:42:26 +0200 | [diff] [blame] | 188 | "gpv", "i2cp", "irrx", "irtx", "pta", |
| 189 | "rm", "slxa", "slxk", "spia", "spib", |
| 190 | "uac"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 191 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 192 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 193 | }; |
| 194 | conf_ck32 { |
| 195 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 196 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 197 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 198 | }; |
| 199 | conf_csus { |
| 200 | nvidia,pins = "csus", "spid", "spif"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 201 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 202 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 203 | }; |
| 204 | conf_crtp { |
| 205 | nvidia,pins = "crtp", "dap2", "dap3", "dap4", |
| 206 | "dtc", "dte", "dtf", "gpu", "sdio1", |
| 207 | "slxc", "slxd", "spdi", "spdo", "spig", |
| 208 | "uda"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 209 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 210 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 211 | }; |
| 212 | conf_ddc { |
| 213 | nvidia,pins = "ddc", "dta", "dtd", "kbca", |
| 214 | "kbcb", "kbcc", "kbcd", "kbce", "kbcf", |
Andreas Obergschwandtner | 2270ad2 | 2021-07-29 16:42:26 +0200 | [diff] [blame] | 215 | "sdc", "uad", "uca"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 216 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 217 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 218 | }; |
| 219 | conf_hdint { |
| 220 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 221 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
| 222 | "lvp0", "owc", "sdb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 223 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 224 | }; |
Andreas Obergschwandtner | 2270ad2 | 2021-07-29 16:42:26 +0200 | [diff] [blame] | 225 | conf_sdd { |
| 226 | nvidia,pins = "sdd", "spic", "spie", "spih", |
| 227 | "uaa", "uab", "ucb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 228 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 229 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 230 | }; |
| 231 | conf_lc { |
| 232 | nvidia,pins = "lc", "ls"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 233 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 234 | }; |
| 235 | conf_ld0 { |
| 236 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 237 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 238 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 239 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 240 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 241 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
| 242 | "lvs", "pmc"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 243 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 244 | }; |
| 245 | conf_ld17_0 { |
| 246 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 247 | "ld23_22"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 248 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 249 | }; |
| 250 | }; |
Thierry Reding | ec31990 | 2012-11-09 14:04:50 +0100 | [diff] [blame] | 251 | |
| 252 | state_i2cmux_ddc: pinmux_i2cmux_ddc { |
| 253 | ddc { |
| 254 | nvidia,pins = "ddc"; |
| 255 | nvidia,function = "i2c2"; |
| 256 | }; |
| 257 | pta { |
| 258 | nvidia,pins = "pta"; |
| 259 | nvidia,function = "rsvd4"; |
| 260 | }; |
| 261 | }; |
| 262 | |
| 263 | state_i2cmux_pta: pinmux_i2cmux_pta { |
| 264 | ddc { |
| 265 | nvidia,pins = "ddc"; |
| 266 | nvidia,function = "rsvd4"; |
| 267 | }; |
| 268 | pta { |
| 269 | nvidia,pins = "pta"; |
| 270 | nvidia,function = "i2c2"; |
| 271 | }; |
| 272 | }; |
| 273 | |
| 274 | state_i2cmux_idle: pinmux_i2cmux_idle { |
| 275 | ddc { |
| 276 | nvidia,pins = "ddc"; |
| 277 | nvidia,function = "rsvd4"; |
| 278 | }; |
| 279 | pta { |
| 280 | nvidia,pins = "pta"; |
| 281 | nvidia,function = "rsvd4"; |
| 282 | }; |
| 283 | }; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 284 | }; |
| 285 | |
| 286 | i2s@70002800 { |
| 287 | status = "okay"; |
| 288 | }; |
| 289 | |
| 290 | serial@70006300 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 291 | status = "okay"; |
| 292 | }; |
| 293 | |
| 294 | i2c@7000c000 { |
| 295 | clock-frequency = <400000>; |
| 296 | status = "okay"; |
| 297 | }; |
| 298 | |
Thierry Reding | ec31990 | 2012-11-09 14:04:50 +0100 | [diff] [blame] | 299 | i2c@7000c400 { |
| 300 | clock-frequency = <100000>; |
| 301 | status = "okay"; |
| 302 | }; |
| 303 | |
| 304 | i2cmux { |
| 305 | compatible = "i2c-mux-pinctrl"; |
| 306 | #address-cells = <1>; |
| 307 | #size-cells = <0>; |
| 308 | |
| 309 | i2c-parent = <&{/i2c@7000c400}>; |
| 310 | |
| 311 | pinctrl-names = "ddc", "pta", "idle"; |
| 312 | pinctrl-0 = <&state_i2cmux_ddc>; |
| 313 | pinctrl-1 = <&state_i2cmux_pta>; |
| 314 | pinctrl-2 = <&state_i2cmux_idle>; |
| 315 | |
Thierry Reding | e6f0979 | 2012-11-16 16:56:50 +0100 | [diff] [blame] | 316 | hdmi_ddc: i2c@0 { |
Thierry Reding | ec31990 | 2012-11-09 14:04:50 +0100 | [diff] [blame] | 317 | reg = <0>; |
| 318 | #address-cells = <1>; |
| 319 | #size-cells = <0>; |
| 320 | }; |
| 321 | |
| 322 | i2c@1 { |
| 323 | reg = <1>; |
| 324 | #address-cells = <1>; |
| 325 | #size-cells = <0>; |
| 326 | }; |
| 327 | }; |
| 328 | |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 329 | i2c@7000d000 { |
| 330 | clock-frequency = <400000>; |
| 331 | status = "okay"; |
| 332 | |
| 333 | pmic: tps6586x@34 { |
| 334 | compatible = "ti,tps6586x"; |
| 335 | reg = <0x34>; |
Stephen Warren | 6cecf91 | 2013-02-13 12:51:51 -0700 | [diff] [blame] | 336 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 337 | |
| 338 | ti,system-power-controller; |
| 339 | |
| 340 | #gpio-cells = <2>; |
| 341 | gpio-controller; |
| 342 | |
Alban Bedel | 23e6334 | 2014-06-19 15:25:49 +0200 | [diff] [blame] | 343 | /* vdd_5v0_reg must be provided by the base board */ |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 344 | sys-supply = <&vdd_5v0_reg>; |
| 345 | vin-sm0-supply = <&sys_reg>; |
| 346 | vin-sm1-supply = <&sys_reg>; |
| 347 | vin-sm2-supply = <&sys_reg>; |
| 348 | vinldo01-supply = <&sm2_reg>; |
| 349 | vinldo23-supply = <&sm2_reg>; |
| 350 | vinldo4-supply = <&sm2_reg>; |
| 351 | vinldo678-supply = <&sm2_reg>; |
| 352 | vinldo9-supply = <&sm2_reg>; |
| 353 | |
| 354 | regulators { |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 355 | sys_reg: sys { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 356 | regulator-name = "vdd_sys"; |
| 357 | regulator-always-on; |
| 358 | }; |
| 359 | |
Dmitry Osipenko | 83b7f0b | 2021-12-01 02:23:43 +0300 | [diff] [blame] | 360 | vdd_core: sm0 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 361 | regulator-name = "vdd_sys_sm0,vdd_core"; |
| 362 | regulator-min-microvolt = <1200000>; |
| 363 | regulator-max-microvolt = <1200000>; |
| 364 | regulator-always-on; |
| 365 | }; |
| 366 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 367 | sm1 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 368 | regulator-name = "vdd_sys_sm1,vdd_cpu"; |
| 369 | regulator-min-microvolt = <1000000>; |
| 370 | regulator-max-microvolt = <1000000>; |
| 371 | regulator-always-on; |
| 372 | }; |
| 373 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 374 | sm2_reg: sm2 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 375 | regulator-name = "vdd_sys_sm2,vin_ldo*"; |
| 376 | regulator-min-microvolt = <3700000>; |
| 377 | regulator-max-microvolt = <3700000>; |
| 378 | regulator-always-on; |
| 379 | }; |
| 380 | |
Thierry Reding | 1b2d6b8 | 2013-08-09 16:49:20 +0200 | [diff] [blame] | 381 | pci_clk_reg: ldo0 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 382 | regulator-name = "vdd_ldo0,vddio_pex_clk"; |
| 383 | regulator-min-microvolt = <3300000>; |
| 384 | regulator-max-microvolt = <3300000>; |
| 385 | }; |
| 386 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 387 | ldo1 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 388 | regulator-name = "vdd_ldo1,avdd_pll*"; |
| 389 | regulator-min-microvolt = <1100000>; |
| 390 | regulator-max-microvolt = <1100000>; |
| 391 | regulator-always-on; |
| 392 | }; |
| 393 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 394 | ldo2 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 395 | regulator-name = "vdd_ldo2,vdd_rtc"; |
| 396 | regulator-min-microvolt = <1200000>; |
| 397 | regulator-max-microvolt = <1200000>; |
| 398 | }; |
| 399 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 400 | ldo3 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 401 | regulator-name = "vdd_ldo3,avdd_usb*"; |
| 402 | regulator-min-microvolt = <3300000>; |
| 403 | regulator-max-microvolt = <3300000>; |
| 404 | regulator-always-on; |
| 405 | }; |
| 406 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 407 | ldo4 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 408 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
| 409 | regulator-min-microvolt = <1800000>; |
| 410 | regulator-max-microvolt = <1800000>; |
| 411 | regulator-always-on; |
| 412 | }; |
| 413 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 414 | ldo5 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 415 | regulator-name = "vdd_ldo5,vcore_mmc"; |
| 416 | regulator-min-microvolt = <2850000>; |
| 417 | regulator-max-microvolt = <2850000>; |
| 418 | }; |
| 419 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 420 | ldo6 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 421 | regulator-name = "vdd_ldo6,avdd_vdac"; |
| 422 | /* |
| 423 | * According to the Tegra 2 Automotive |
| 424 | * DataSheet, a typical value for this |
| 425 | * would be 2.8V, but the PMIC only |
| 426 | * supports 2.85V. |
| 427 | */ |
| 428 | regulator-min-microvolt = <2850000>; |
| 429 | regulator-max-microvolt = <2850000>; |
| 430 | }; |
| 431 | |
Thierry Reding | e6f0979 | 2012-11-16 16:56:50 +0100 | [diff] [blame] | 432 | hdmi_vdd_reg: ldo7 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 433 | regulator-name = "vdd_ldo7,avdd_hdmi"; |
| 434 | regulator-min-microvolt = <3300000>; |
| 435 | regulator-max-microvolt = <3300000>; |
| 436 | }; |
| 437 | |
Thierry Reding | e6f0979 | 2012-11-16 16:56:50 +0100 | [diff] [blame] | 438 | hdmi_pll_reg: ldo8 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 439 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
| 440 | regulator-min-microvolt = <1800000>; |
| 441 | regulator-max-microvolt = <1800000>; |
| 442 | }; |
| 443 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 444 | ldo9 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 445 | regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam"; |
| 446 | /* |
| 447 | * According to the Tegra 2 Automotive |
| 448 | * DataSheet, a typical value for this |
| 449 | * would be 2.8V, but the PMIC only |
| 450 | * supports 2.85V. |
| 451 | */ |
| 452 | regulator-min-microvolt = <2850000>; |
| 453 | regulator-max-microvolt = <2850000>; |
| 454 | regulator-always-on; |
| 455 | }; |
| 456 | |
Stephen Warren | b9c665d | 2012-09-20 17:04:06 -0600 | [diff] [blame] | 457 | ldo_rtc { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 458 | regulator-name = "vdd_rtc_out"; |
| 459 | regulator-min-microvolt = <3300000>; |
| 460 | regulator-max-microvolt = <3300000>; |
| 461 | regulator-always-on; |
| 462 | }; |
| 463 | }; |
| 464 | }; |
Thierry Reding | 840a408 | 2012-11-09 23:00:08 +0100 | [diff] [blame] | 465 | |
| 466 | temperature-sensor@4c { |
| 467 | compatible = "onnn,nct1008"; |
| 468 | reg = <0x4c>; |
| 469 | }; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 470 | }; |
| 471 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 472 | pmc@7000e400 { |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 473 | nvidia,invert-interrupt; |
Joseph Lo | 47d2d63 | 2013-08-12 17:40:07 +0800 | [diff] [blame] | 474 | nvidia,suspend-mode = <1>; |
Joseph Lo | a44a019 | 2013-04-03 19:31:52 +0800 | [diff] [blame] | 475 | nvidia,cpu-pwr-good-time = <5000>; |
| 476 | nvidia,cpu-pwr-off-time = <5000>; |
| 477 | nvidia,core-pwr-good-time = <3845 3845>; |
| 478 | nvidia,core-pwr-off-time = <3875>; |
| 479 | nvidia,sys-clock-req-active-high; |
Dmitry Osipenko | 83b7f0b | 2021-12-01 02:23:43 +0300 | [diff] [blame] | 480 | core-supply = <&vdd_core>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 481 | }; |
| 482 | |
Rob Herring | 508d690 | 2017-03-21 21:03:06 -0500 | [diff] [blame] | 483 | pcie@80003000 { |
Thierry Reding | cca8614 | 2014-05-28 16:49:12 +0200 | [diff] [blame] | 484 | avdd-pex-supply = <&pci_vdd_reg>; |
| 485 | vdd-pex-supply = <&pci_vdd_reg>; |
| 486 | avdd-pex-pll-supply = <&pci_vdd_reg>; |
| 487 | avdd-plle-supply = <&pci_vdd_reg>; |
| 488 | vddio-pex-clk-supply = <&pci_clk_reg>; |
Thierry Reding | 1b2d6b8 | 2013-08-09 16:49:20 +0200 | [diff] [blame] | 489 | }; |
| 490 | |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 491 | usb@c5008000 { |
| 492 | status = "okay"; |
| 493 | }; |
| 494 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 495 | usb-phy@c5008000 { |
| 496 | status = "okay"; |
| 497 | }; |
| 498 | |
Thierry Reding | 32c096c | 2020-06-11 19:21:17 +0200 | [diff] [blame] | 499 | mmc@c8000600 { |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 500 | cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>; |
| 501 | wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 502 | bus-width = <4>; |
| 503 | status = "okay"; |
| 504 | }; |
| 505 | |
David Heidelberg | 4f74ed8 | 2021-12-12 00:14:03 +0300 | [diff] [blame] | 506 | clk32k_in: clock-32k { |
Thierry Reding | 901c865 | 2020-06-11 19:00:14 +0200 | [diff] [blame] | 507 | compatible = "fixed-clock"; |
| 508 | clock-frequency = <32768>; |
| 509 | #clock-cells = <0>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 510 | }; |
| 511 | |
Dmitry Osipenko | c629196 | 2021-12-12 00:14:04 +0300 | [diff] [blame] | 512 | pci_vdd_reg: regulator-1v05 { |
Thierry Reding | 1cf17aa | 2020-06-11 19:01:32 +0200 | [diff] [blame] | 513 | compatible = "regulator-fixed"; |
| 514 | regulator-name = "vdd_1v05"; |
| 515 | regulator-min-microvolt = <1050000>; |
| 516 | regulator-max-microvolt = <1050000>; |
| 517 | gpio = <&pmic 2 0>; |
| 518 | enable-active-high; |
Thierry Reding | 307e28e | 2012-09-20 17:06:06 +0200 | [diff] [blame] | 519 | }; |
| 520 | }; |