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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 134179823b3ca9c8b98e0631906459dbb022ff9b / . / include / asm-arm / plat-s3c / regs-watchdog.h
blob: 4938492470f7bf6dd50b1c57961d73839bc5edb5 [file] [log] [blame]
Russell Kinga09e64f2008-08-05 16:14:15 +0100[diff] [blame]1/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Watchdog timer control
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]11*/
12
13
14#ifndef __ASM_ARCH_REGS_WATCHDOG_H
Adrian Bunk66bfa2f2008-08-10 15:25:55 +0100[diff] [blame]15#define __ASM_ARCH_REGS_WATCHDOG_H
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]16
Ben Dooks530ef3c2007-07-22 16:59:44 +0100[diff] [blame]17#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]18
Ben Dooks530ef3c2007-07-22 16:59:44 +0100[diff] [blame]19#define S3C2410_WTCON S3C_WDOGREG(0x00)
20#define S3C2410_WTDAT S3C_WDOGREG(0x04)
21#define S3C2410_WTCNT S3C_WDOGREG(0x08)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]22
23/* the watchdog can either generate a reset pulse, or an
24 * interrupt.
25 */
26
27#define S3C2410_WTCON_RSTEN (0x01)
28#define S3C2410_WTCON_INTEN (1<<2)
29#define S3C2410_WTCON_ENABLE (1<<5)
30
31#define S3C2410_WTCON_DIV16 (0<<3)
32#define S3C2410_WTCON_DIV32 (1<<3)
33#define S3C2410_WTCON_DIV64 (2<<3)
34#define S3C2410_WTCON_DIV128 (3<<3)
35
36#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
37#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
38
39#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
40
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