Thomas Gleixner | 1ccea77 | 2019-05-19 15:51:43 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 2 | /* |
Dinh Nguyen | 56c5c13 | 2013-04-11 10:55:26 -0500 | [diff] [blame] | 3 | * Copyright 2011-2012 Calxeda, Inc. |
| 4 | * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 5 | * |
Dinh Nguyen | 56c5c13 | 2013-04-11 10:55:26 -0500 | [diff] [blame] | 6 | * Based from clk-highbank.c |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 7 | */ |
Dinh Nguyen | 56c5c13 | 2013-04-11 10:55:26 -0500 | [diff] [blame] | 8 | #include <linux/of.h> |
Dinh Nguyen | 6631422 | 2012-07-18 16:07:18 -0600 | [diff] [blame] | 9 | |
Steffen Trumtrar | 97259e9 | 2014-01-06 10:27:37 -0600 | [diff] [blame] | 10 | #include "clk.h" |
Dinh Nguyen | 56c5c13 | 2013-04-11 10:55:26 -0500 | [diff] [blame] | 11 | |
Dinh Nguyen | a30d27e | 2014-04-14 07:59:32 -0500 | [diff] [blame] | 12 | CLK_OF_DECLARE(socfpga_pll_clk, "altr,socfpga-pll-clock", socfpga_pll_init); |
| 13 | CLK_OF_DECLARE(socfpga_perip_clk, "altr,socfpga-perip-clk", socfpga_periph_init); |
| 14 | CLK_OF_DECLARE(socfpga_gate_clk, "altr,socfpga-gate-clk", socfpga_gate_init); |
Dinh Nguyen | 5343325 | 2015-05-19 22:22:42 -0500 | [diff] [blame] | 15 | CLK_OF_DECLARE(socfpga_a10_pll_clk, "altr,socfpga-a10-pll-clock", |
| 16 | socfpga_a10_pll_init); |
| 17 | CLK_OF_DECLARE(socfpga_a10_perip_clk, "altr,socfpga-a10-perip-clk", |
| 18 | socfpga_a10_periph_init); |
| 19 | CLK_OF_DECLARE(socfpga_a10_gate_clk, "altr,socfpga-a10-gate-clk", |
| 20 | socfpga_a10_gate_init); |