Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 1 | config IRQCHIP |
2 | def_bool y | ||||
3 | depends on OF_IRQ | ||||
4 | |||||
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 5 | config ARM_GIC |
6 | bool | ||||
7 | select IRQ_DOMAIN | ||||
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 8 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 9 | select MULTI_IRQ_HANDLER |
Marc Zyngier | 0c9e498 | 2017-08-18 09:39:16 +0100 | [diff] [blame] | 10 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 11 | |
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 12 | config ARM_GIC_PM |
13 | bool | ||||
14 | depends on PM | ||||
15 | select ARM_GIC | ||||
16 | select PM_CLK | ||||
17 | |||||
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 18 | config ARM_GIC_MAX_NR |
19 | int | ||||
20 | default 2 if ARCH_REALVIEW | ||||
21 | default 1 | ||||
22 | |||||
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 23 | config ARM_GIC_V2M |
24 | bool | ||||
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 25 | depends on PCI |
26 | select ARM_GIC | ||||
27 | select PCI_MSI | ||||
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 28 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 29 | config GIC_NON_BANKED |
30 | bool | ||||
31 | |||||
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 32 | config ARM_GIC_V3 |
33 | bool | ||||
34 | select IRQ_DOMAIN | ||||
35 | select MULTI_IRQ_HANDLER | ||||
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 36 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 37 | select PARTITION_PERCPU |
Marc Zyngier | 956ae91 | 2017-08-18 09:39:17 +0100 | [diff] [blame] | 38 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 39 | |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 40 | config ARM_GIC_V3_ITS |
41 | bool | ||||
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 42 | depends on PCI |
43 | depends on PCI_MSI | ||||
Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 44 | |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 45 | config ARM_NVIC |
46 | bool | ||||
47 | select IRQ_DOMAIN | ||||
Stefan Agner | 2d9f59f | 2015-05-16 11:44:16 +0200 | [diff] [blame] | 48 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 49 | select GENERIC_IRQ_CHIP |
50 | |||||
51 | config ARM_VIC | ||||
52 | bool | ||||
53 | select IRQ_DOMAIN | ||||
54 | select MULTI_IRQ_HANDLER | ||||
55 | |||||
56 | config ARM_VIC_NR | ||||
57 | int | ||||
58 | default 4 if ARCH_S5PV210 | ||||
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 59 | default 2 |
60 | depends on ARM_VIC | ||||
61 | help | ||||
62 | The maximum number of VICs available in the system, for | ||||
63 | power management. | ||||
64 | |||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 65 | config ARMADA_370_XP_IRQ |
66 | bool | ||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 67 | select GENERIC_IRQ_CHIP |
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 68 | select PCI_MSI if PCI |
Marc Zyngier | e31793a | 2017-08-18 09:39:19 +0100 | [diff] [blame] | 69 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 70 | |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 71 | config ALPINE_MSI |
72 | bool | ||||
Arnd Bergmann | 3ee80364 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 73 | depends on PCI |
74 | select PCI_MSI | ||||
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 75 | select GENERIC_IRQ_CHIP |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 76 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 77 | config ATMEL_AIC_IRQ |
78 | bool | ||||
79 | select GENERIC_IRQ_CHIP | ||||
80 | select IRQ_DOMAIN | ||||
81 | select MULTI_IRQ_HANDLER | ||||
82 | select SPARSE_IRQ | ||||
83 | |||||
84 | config ATMEL_AIC5_IRQ | ||||
85 | bool | ||||
86 | select GENERIC_IRQ_CHIP | ||||
87 | select IRQ_DOMAIN | ||||
88 | select MULTI_IRQ_HANDLER | ||||
89 | select SPARSE_IRQ | ||||
90 | |||||
Ralf Baechle | 0509cfd | 2015-07-08 14:46:08 +0200 | [diff] [blame] | 91 | config I8259 |
92 | bool | ||||
93 | select IRQ_DOMAIN | ||||
94 | |||||
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 95 | config BCM6345_L1_IRQ |
96 | bool | ||||
97 | select GENERIC_IRQ_CHIP | ||||
98 | select IRQ_DOMAIN | ||||
Marc Zyngier | d0ed5e8 | 2017-08-18 09:39:20 +0100 | [diff] [blame] | 99 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 100 | |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 101 | config BCM7038_L1_IRQ |
102 | bool | ||||
103 | select GENERIC_IRQ_CHIP | ||||
104 | select IRQ_DOMAIN | ||||
Marc Zyngier | b8d9884 | 2017-08-18 09:39:21 +0100 | [diff] [blame] | 105 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 106 | |
Kevin Cernekee | a4fcbb8 | 2014-11-06 22:44:27 -0800 | [diff] [blame] | 107 | config BCM7120_L2_IRQ |
108 | bool | ||||
109 | select GENERIC_IRQ_CHIP | ||||
110 | select IRQ_DOMAIN | ||||
111 | |||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 112 | config BRCMSTB_L2_IRQ |
113 | bool | ||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 114 | select GENERIC_IRQ_CHIP |
115 | select IRQ_DOMAIN | ||||
116 | |||||
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 117 | config DW_APB_ICTL |
118 | bool | ||||
Jisheng Zhang | e158849 | 2014-10-22 20:59:10 +0800 | [diff] [blame] | 119 | select GENERIC_IRQ_CHIP |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 120 | select IRQ_DOMAIN |
121 | |||||
Linus Walleij | 6ee532e | 2017-03-18 17:53:24 +0100 | [diff] [blame] | 122 | config FARADAY_FTINTC010 |
123 | bool | ||||
124 | select IRQ_DOMAIN | ||||
125 | select MULTI_IRQ_HANDLER | ||||
126 | select SPARSE_IRQ | ||||
127 | |||||
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 128 | config HISILICON_IRQ_MBIGEN |
129 | bool | ||||
130 | select ARM_GIC_V3 | ||||
131 | select ARM_GIC_V3_ITS | ||||
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 132 | |
James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 133 | config IMGPDC_IRQ |
134 | bool | ||||
135 | select GENERIC_IRQ_CHIP | ||||
136 | select IRQ_DOMAIN | ||||
137 | |||||
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 138 | config IRQ_MIPS_CPU |
139 | bool | ||||
140 | select GENERIC_IRQ_CHIP | ||||
Paul Burton | 3838a54 | 2017-03-30 12:06:11 -0700 | [diff] [blame] | 141 | select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 142 | select IRQ_DOMAIN |
Paul Burton | 3838a54 | 2017-03-30 12:06:11 -0700 | [diff] [blame] | 143 | select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI |
Marc Zyngier | 18416e4 | 2017-08-18 09:39:24 +0100 | [diff] [blame] | 144 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 145 | |
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 146 | config CLPS711X_IRQCHIP |
147 | bool | ||||
148 | depends on ARCH_CLPS711X | ||||
149 | select IRQ_DOMAIN | ||||
150 | select MULTI_IRQ_HANDLER | ||||
151 | select SPARSE_IRQ | ||||
152 | default y | ||||
153 | |||||
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 154 | config OR1K_PIC |
155 | bool | ||||
156 | select IRQ_DOMAIN | ||||
157 | |||||
Felipe Balbi | 8598066 | 2014-09-15 16:15:02 -0500 | [diff] [blame] | 158 | config OMAP_IRQCHIP |
159 | bool | ||||
160 | select GENERIC_IRQ_CHIP | ||||
161 | select IRQ_DOMAIN | ||||
162 | |||||
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 163 | config ORION_IRQCHIP |
164 | bool | ||||
165 | select IRQ_DOMAIN | ||||
166 | select MULTI_IRQ_HANDLER | ||||
167 | |||||
Cristian Birsan | aaa8666 | 2016-01-13 18:15:35 -0700 | [diff] [blame] | 168 | config PIC32_EVIC |
169 | bool | ||||
170 | select GENERIC_IRQ_CHIP | ||||
171 | select IRQ_DOMAIN | ||||
172 | |||||
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 173 | config JCORE_AIC |
Rich Felker | 3602ffd | 2016-10-19 17:53:52 +0000 | [diff] [blame] | 174 | bool "J-Core integrated AIC" if COMPILE_TEST |
175 | depends on OF | ||||
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 176 | select IRQ_DOMAIN |
177 | help | ||||
178 | Support for the J-Core integrated AIC. | ||||
179 | |||||
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 180 | config RENESAS_INTC_IRQPIN |
181 | bool | ||||
182 | select IRQ_DOMAIN | ||||
183 | |||||
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 184 | config RENESAS_IRQC |
185 | bool | ||||
Magnus Damm | 99c221d | 2015-09-28 18:42:37 +0900 | [diff] [blame] | 186 | select GENERIC_IRQ_CHIP |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 187 | select IRQ_DOMAIN |
188 | |||||
Lee Jones | 0708848 | 2015-02-18 15:13:58 +0000 | [diff] [blame] | 189 | config ST_IRQCHIP |
190 | bool | ||||
191 | select REGMAP | ||||
192 | select MFD_SYSCON | ||||
193 | help | ||||
194 | Enables SysCfg Controlled IRQs on STi based platforms. | ||||
195 | |||||
Mans Rullgard | 4bba668 | 2016-01-20 18:07:17 +0000 | [diff] [blame] | 196 | config TANGO_IRQ |
197 | bool | ||||
198 | select IRQ_DOMAIN | ||||
199 | select GENERIC_IRQ_CHIP | ||||
200 | |||||
Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 201 | config TB10X_IRQC |
202 | bool | ||||
203 | select IRQ_DOMAIN | ||||
204 | select GENERIC_IRQ_CHIP | ||||
205 | |||||
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 206 | config TS4800_IRQ |
207 | tristate "TS-4800 IRQ controller" | ||||
208 | select IRQ_DOMAIN | ||||
Richard Weinberger | 0df337c | 2016-01-25 23:24:17 +0100 | [diff] [blame] | 209 | depends on HAS_IOMEM |
Jean Delvare | d2b383d | 2016-02-09 11:19:20 +0100 | [diff] [blame] | 210 | depends on SOC_IMX51 || COMPILE_TEST |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 211 | help |
212 | Support for the TS-4800 FPGA IRQ controller | ||||
213 | |||||
Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 214 | config VERSATILE_FPGA_IRQ |
215 | bool | ||||
216 | select IRQ_DOMAIN | ||||
217 | |||||
218 | config VERSATILE_FPGA_IRQ_NR | ||||
219 | int | ||||
220 | default 4 | ||||
221 | depends on VERSATILE_FPGA_IRQ | ||||
Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 222 | |
223 | config XTENSA_MX | ||||
224 | bool | ||||
225 | select IRQ_DOMAIN | ||||
Marc Zyngier | 5009121 | 2017-08-18 09:39:25 +0100 | [diff] [blame] | 226 | select GENERIC_IRQ_EFFECTIVE_AFF_MASK |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 227 | |
Zubair Lutfullah Kakakhel | 0547dc7 | 2016-11-14 12:13:45 +0000 | [diff] [blame] | 228 | config XILINX_INTC |
229 | bool | ||||
230 | select IRQ_DOMAIN | ||||
231 | |||||
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 232 | config IRQ_CROSSBAR |
233 | bool | ||||
234 | help | ||||
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 235 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 236 | The primary irqchip invokes the crossbar's callback which inturn allocates |
237 | a free irq and configures the IP. Thus the peripheral interrupts are | ||||
238 | routed to one of the free irqchip interrupt lines. | ||||
Grygorii Strashko | 89323f8 | 2014-07-23 17:40:30 +0300 | [diff] [blame] | 239 | |
240 | config KEYSTONE_IRQ | ||||
241 | tristate "Keystone 2 IRQ controller IP" | ||||
242 | depends on ARCH_KEYSTONE | ||||
243 | help | ||||
244 | Support for Texas Instruments Keystone 2 IRQ controller IP which | ||||
245 | is part of the Keystone 2 IPC mechanism | ||||
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 246 | |
247 | config MIPS_GIC | ||||
248 | bool | ||||
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 249 | select GENERIC_IRQ_IPI |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 250 | select IRQ_DOMAIN_HIERARCHY |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 251 | select MIPS_CM |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 252 | |
Paul Burton | 44e08e7 | 2015-05-24 16:11:31 +0100 | [diff] [blame] | 253 | config INGENIC_IRQ |
254 | bool | ||||
255 | depends on MACH_INGENIC | ||||
256 | default y | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 257 | |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 258 | config RENESAS_H8300H_INTC |
259 | bool | ||||
260 | select IRQ_DOMAIN | ||||
261 | |||||
262 | config RENESAS_H8S_INTC | ||||
263 | bool | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 264 | select IRQ_DOMAIN |
Shenwei Wang | e324c4d | 2015-08-24 14:04:15 -0500 | [diff] [blame] | 265 | |
266 | config IMX_GPCV2 | ||||
267 | bool | ||||
268 | select IRQ_DOMAIN | ||||
269 | help | ||||
270 | Enables the wakeup IRQs for IMX platforms with GPCv2 block | ||||
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 271 | |
272 | config IRQ_MXS | ||||
273 | def_bool y if MACH_ASM9260 || ARCH_MXS | ||||
274 | select IRQ_DOMAIN | ||||
275 | select STMP_DEVICE | ||||
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 276 | |
Thomas Petazzoni | a68a63c | 2017-06-21 15:29:14 +0200 | [diff] [blame] | 277 | config MVEBU_GICP |
278 | bool | ||||
279 | |||||
Thomas Petazzoni | e0de91a | 2017-06-21 15:29:15 +0200 | [diff] [blame] | 280 | config MVEBU_ICU |
281 | bool | ||||
282 | |||||
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 283 | config MVEBU_ODMI |
284 | bool | ||||
Arnd Bergmann | fa23b9d | 2017-03-14 13:54:12 +0100 | [diff] [blame] | 285 | select GENERIC_MSI_IRQ_DOMAIN |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 286 | |
Thomas Petazzoni | a109893 | 2016-08-05 16:55:19 +0200 | [diff] [blame] | 287 | config MVEBU_PIC |
288 | bool | ||||
289 | |||||
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 290 | config LS_SCFG_MSI |
291 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE | ||||
292 | depends on PCI && PCI_MSI | ||||
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 293 | |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 294 | config PARTITION_PERCPU |
295 | bool | ||||
Linus Torvalds | 0efacbb | 2016-05-19 09:46:18 -0700 | [diff] [blame] | 296 | |
Noam Camus | 44df427c | 2015-10-29 00:26:22 +0200 | [diff] [blame] | 297 | config EZNPS_GIC |
298 | bool "NPS400 Global Interrupt Manager (GIM)" | ||||
Arnd Bergmann | ffd565e | 2016-05-12 23:03:35 +0200 | [diff] [blame] | 299 | depends on ARC || (COMPILE_TEST && !64BIT) |
Noam Camus | 44df427c | 2015-10-29 00:26:22 +0200 | [diff] [blame] | 300 | select IRQ_DOMAIN |
301 | help | ||||
302 | Support the EZchip NPS400 global interrupt controller | ||||
Alexandre TORGUE | e0720416 | 2016-09-20 18:00:57 +0200 | [diff] [blame] | 303 | |
304 | config STM32_EXTI | ||||
305 | bool | ||||
306 | select IRQ_DOMAIN | ||||
Agustin Vega-Frias | f20cc9b | 2017-02-02 18:23:59 -0500 | [diff] [blame] | 307 | |
308 | config QCOM_IRQ_COMBINER | ||||
309 | bool "QCOM IRQ combiner support" | ||||
310 | depends on ARCH_QCOM && ACPI | ||||
311 | select IRQ_DOMAIN | ||||
312 | select IRQ_DOMAIN_HIERARCHY | ||||
313 | help | ||||
314 | Say yes here to add support for the IRQ combiner devices embedded | ||||
315 | in Qualcomm Technologies chips. | ||||
Masahiro Yamada | 5ed34d3a | 2017-08-23 10:31:47 +0900 | [diff] [blame] | 316 | |
317 | config IRQ_UNIPHIER_AIDET | ||||
318 | bool "UniPhier AIDET support" if COMPILE_TEST | ||||
319 | depends on ARCH_UNIPHIER || COMPILE_TEST | ||||
320 | default ARCH_UNIPHIER | ||||
321 | select IRQ_DOMAIN_HIERARCHY | ||||
322 | help | ||||
323 | Support for the UniPhier AIDET (ARM Interrupt Detector). |