blob: 9d8a1dd2e2c25a8f3bca727f795a8b1fc7de858d [file] [log] [blame]
Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
Marc Zyngier0c9e4982017-08-18 09:39:16 +010010 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Rob Herring81243e42012-11-20 21:21:40 -060011
Jon Hunter9c8eddd2016-06-07 16:12:34 +010012config ARM_GIC_PM
13 bool
14 depends on PM
15 select ARM_GIC
16 select PM_CLK
17
Linus Walleija27d21e2015-12-18 10:44:53 +010018config ARM_GIC_MAX_NR
19 int
20 default 2 if ARCH_REALVIEW
21 default 1
22
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000023config ARM_GIC_V2M
24 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -050025 depends on PCI
26 select ARM_GIC
27 select PCI_MSI
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000028
Rob Herring81243e42012-11-20 21:21:40 -060029config GIC_NON_BANKED
30 bool
31
Marc Zyngier021f6532014-06-30 16:01:31 +010032config ARM_GIC_V3
33 bool
34 select IRQ_DOMAIN
35 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000036 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +010037 select PARTITION_PERCPU
Marc Zyngier956ae912017-08-18 09:39:17 +010038 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Marc Zyngier021f6532014-06-30 16:01:31 +010039
Marc Zyngier19812722014-11-24 14:35:19 +000040config ARM_GIC_V3_ITS
41 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -050042 depends on PCI
43 depends on PCI_MSI
Uwe Kleine-König292ec082013-06-26 09:18:48 +020044
Rob Herring44430ec2012-10-27 17:25:26 -050045config ARM_NVIC
46 bool
47 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020048 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050049 select GENERIC_IRQ_CHIP
50
51config ARM_VIC
52 bool
53 select IRQ_DOMAIN
54 select MULTI_IRQ_HANDLER
55
56config ARM_VIC_NR
57 int
58 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050059 default 2
60 depends on ARM_VIC
61 help
62 The maximum number of VICs available in the system, for
63 power management.
64
Thomas Petazzonifed6d332016-02-10 15:46:56 +010065config ARMADA_370_XP_IRQ
66 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010067 select GENERIC_IRQ_CHIP
Arnd Bergmann3ee803642016-06-15 15:47:33 -050068 select PCI_MSI if PCI
Marc Zyngiere31793a2017-08-18 09:39:19 +010069 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Thomas Petazzonifed6d332016-02-10 15:46:56 +010070
Antoine Tenarte6b78f22016-02-19 16:22:44 +010071config ALPINE_MSI
72 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -050073 depends on PCI
74 select PCI_MSI
Antoine Tenarte6b78f22016-02-19 16:22:44 +010075 select GENERIC_IRQ_CHIP
Antoine Tenarte6b78f22016-02-19 16:22:44 +010076
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020077config ATMEL_AIC_IRQ
78 bool
79 select GENERIC_IRQ_CHIP
80 select IRQ_DOMAIN
81 select MULTI_IRQ_HANDLER
82 select SPARSE_IRQ
83
84config ATMEL_AIC5_IRQ
85 bool
86 select GENERIC_IRQ_CHIP
87 select IRQ_DOMAIN
88 select MULTI_IRQ_HANDLER
89 select SPARSE_IRQ
90
Ralf Baechle0509cfd2015-07-08 14:46:08 +020091config I8259
92 bool
93 select IRQ_DOMAIN
94
Simon Arlottc7c42ec2015-11-22 14:30:14 +000095config BCM6345_L1_IRQ
96 bool
97 select GENERIC_IRQ_CHIP
98 select IRQ_DOMAIN
Marc Zyngierd0ed5e82017-08-18 09:39:20 +010099 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000100
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800101config BCM7038_L1_IRQ
102 bool
103 select GENERIC_IRQ_CHIP
104 select IRQ_DOMAIN
Marc Zyngierb8d98842017-08-18 09:39:21 +0100105 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800106
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800107config BCM7120_L2_IRQ
108 bool
109 select GENERIC_IRQ_CHIP
110 select IRQ_DOMAIN
111
Florian Fainelli7f646e92014-05-23 17:40:53 -0700112config BRCMSTB_L2_IRQ
113 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700114 select GENERIC_IRQ_CHIP
115 select IRQ_DOMAIN
116
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200117config DW_APB_ICTL
118 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800119 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200120 select IRQ_DOMAIN
121
Linus Walleij6ee532e2017-03-18 17:53:24 +0100122config FARADAY_FTINTC010
123 bool
124 select IRQ_DOMAIN
125 select MULTI_IRQ_HANDLER
126 select SPARSE_IRQ
127
MaJun9a7c4ab2016-03-23 17:06:33 +0800128config HISILICON_IRQ_MBIGEN
129 bool
130 select ARM_GIC_V3
131 select ARM_GIC_V3_ITS
MaJun9a7c4ab2016-03-23 17:06:33 +0800132
James Hoganb6ef9162013-04-22 15:43:50 +0100133config IMGPDC_IRQ
134 bool
135 select GENERIC_IRQ_CHIP
136 select IRQ_DOMAIN
137
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200138config IRQ_MIPS_CPU
139 bool
140 select GENERIC_IRQ_CHIP
Paul Burton3838a542017-03-30 12:06:11 -0700141 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200142 select IRQ_DOMAIN
Paul Burton3838a542017-03-30 12:06:11 -0700143 select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
Marc Zyngier18416e42017-08-18 09:39:24 +0100144 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200145
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400146config CLPS711X_IRQCHIP
147 bool
148 depends on ARCH_CLPS711X
149 select IRQ_DOMAIN
150 select MULTI_IRQ_HANDLER
151 select SPARSE_IRQ
152 default y
153
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300154config OR1K_PIC
155 bool
156 select IRQ_DOMAIN
157
Felipe Balbi85980662014-09-15 16:15:02 -0500158config OMAP_IRQCHIP
159 bool
160 select GENERIC_IRQ_CHIP
161 select IRQ_DOMAIN
162
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200163config ORION_IRQCHIP
164 bool
165 select IRQ_DOMAIN
166 select MULTI_IRQ_HANDLER
167
Cristian Birsanaaa86662016-01-13 18:15:35 -0700168config PIC32_EVIC
169 bool
170 select GENERIC_IRQ_CHIP
171 select IRQ_DOMAIN
172
Rich Felker981b58f2016-08-04 04:30:37 +0000173config JCORE_AIC
Rich Felker3602ffd2016-10-19 17:53:52 +0000174 bool "J-Core integrated AIC" if COMPILE_TEST
175 depends on OF
Rich Felker981b58f2016-08-04 04:30:37 +0000176 select IRQ_DOMAIN
177 help
178 Support for the J-Core integrated AIC.
179
Magnus Damm44358042013-02-18 23:28:34 +0900180config RENESAS_INTC_IRQPIN
181 bool
182 select IRQ_DOMAIN
183
Magnus Dammfbc83b72013-02-27 17:15:01 +0900184config RENESAS_IRQC
185 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900186 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900187 select IRQ_DOMAIN
188
Lee Jones07088482015-02-18 15:13:58 +0000189config ST_IRQCHIP
190 bool
191 select REGMAP
192 select MFD_SYSCON
193 help
194 Enables SysCfg Controlled IRQs on STi based platforms.
195
Mans Rullgard4bba6682016-01-20 18:07:17 +0000196config TANGO_IRQ
197 bool
198 select IRQ_DOMAIN
199 select GENERIC_IRQ_CHIP
200
Christian Ruppertb06eb012013-06-25 18:29:57 +0200201config TB10X_IRQC
202 bool
203 select IRQ_DOMAIN
204 select GENERIC_IRQ_CHIP
205
Damien Riegeld01f8632015-12-21 15:11:23 -0500206config TS4800_IRQ
207 tristate "TS-4800 IRQ controller"
208 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100209 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100210 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500211 help
212 Support for the TS-4800 FPGA IRQ controller
213
Linus Walleij2389d502012-10-31 22:04:31 +0100214config VERSATILE_FPGA_IRQ
215 bool
216 select IRQ_DOMAIN
217
218config VERSATILE_FPGA_IRQ_NR
219 int
220 default 4
221 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400222
223config XTENSA_MX
224 bool
225 select IRQ_DOMAIN
Marc Zyngier50091212017-08-18 09:39:25 +0100226 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
Sricharan R96ca8482013-12-03 15:57:23 +0530227
Zubair Lutfullah Kakakhel0547dc72016-11-14 12:13:45 +0000228config XILINX_INTC
229 bool
230 select IRQ_DOMAIN
231
Sricharan R96ca8482013-12-03 15:57:23 +0530232config IRQ_CROSSBAR
233 bool
234 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900235 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530236 The primary irqchip invokes the crossbar's callback which inturn allocates
237 a free irq and configures the IP. Thus the peripheral interrupts are
238 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300239
240config KEYSTONE_IRQ
241 tristate "Keystone 2 IRQ controller IP"
242 depends on ARCH_KEYSTONE
243 help
244 Support for Texas Instruments Keystone 2 IRQ controller IP which
245 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700246
247config MIPS_GIC
248 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000249 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000250 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700251 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900252
Paul Burton44e08e72015-05-24 16:11:31 +0100253config INGENIC_IRQ
254 bool
255 depends on MACH_INGENIC
256 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700257
Yoshinori Sato8a764482015-05-10 02:30:47 +0900258config RENESAS_H8300H_INTC
259 bool
260 select IRQ_DOMAIN
261
262config RENESAS_H8S_INTC
263 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700264 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500265
266config IMX_GPCV2
267 bool
268 select IRQ_DOMAIN
269 help
270 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200271
272config IRQ_MXS
273 def_bool y if MACH_ASM9260 || ARCH_MXS
274 select IRQ_DOMAIN
275 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100276
Thomas Petazzonia68a63c2017-06-21 15:29:14 +0200277config MVEBU_GICP
278 bool
279
Thomas Petazzonie0de91a2017-06-21 15:29:15 +0200280config MVEBU_ICU
281 bool
282
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100283config MVEBU_ODMI
284 bool
Arnd Bergmannfa23b9d2017-03-14 13:54:12 +0100285 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100286
Thomas Petazzonia1098932016-08-05 16:55:19 +0200287config MVEBU_PIC
288 bool
289
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800290config LS_SCFG_MSI
291 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
292 depends on PCI && PCI_MSI
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800293
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100294config PARTITION_PERCPU
295 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700296
Noam Camus44df427c2015-10-29 00:26:22 +0200297config EZNPS_GIC
298 bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmannffd565e2016-05-12 23:03:35 +0200299 depends on ARC || (COMPILE_TEST && !64BIT)
Noam Camus44df427c2015-10-29 00:26:22 +0200300 select IRQ_DOMAIN
301 help
302 Support the EZchip NPS400 global interrupt controller
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200303
304config STM32_EXTI
305 bool
306 select IRQ_DOMAIN
Agustin Vega-Friasf20cc9b2017-02-02 18:23:59 -0500307
308config QCOM_IRQ_COMBINER
309 bool "QCOM IRQ combiner support"
310 depends on ARCH_QCOM && ACPI
311 select IRQ_DOMAIN
312 select IRQ_DOMAIN_HIERARCHY
313 help
314 Say yes here to add support for the IRQ combiner devices embedded
315 in Qualcomm Technologies chips.
Masahiro Yamada5ed34d3a2017-08-23 10:31:47 +0900316
317config IRQ_UNIPHIER_AIDET
318 bool "UniPhier AIDET support" if COMPILE_TEST
319 depends on ARCH_UNIPHIER || COMPILE_TEST
320 default ARCH_UNIPHIER
321 select IRQ_DOMAIN_HIERARCHY
322 help
323 Support for the UniPhier AIDET (ARM Interrupt Detector).