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Daniel Mackaff18a62012-07-25 17:56:48 +02001/* The pxa3xx skeleton simply augments the 2xx version */
Robert Jarzmikd96672e2015-02-07 13:13:24 +01002#include "pxa2xx.dtsi"
Daniel Mackaff18a62012-07-25 17:56:48 +02003
4/ {
5 model = "Marvell PXA3xx familiy SoC";
6 compatible = "marvell,pxa3xx";
7
8 pxabus {
Robert Jarzmik0cd49142015-06-20 10:17:26 +02009 pdma: dma-controller@40000000 {
10 compatible = "marvell,pdma-1.0";
11 reg = <0x40000000 0x10000>;
12 interrupts = <25>;
13 #dma-channels = <32>;
14 #dma-cells = <2>;
15 status = "okay";
16 };
17
Daniel Mackaff18a62012-07-25 17:56:48 +020018 pwri2c: i2c@40f500c0 {
19 compatible = "mrvl,pwri2c";
20 reg = <0x40f500c0 0x30>;
21 interrupts = <6>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010022 clocks = <&clks CLK_PWRI2C>;
Daniel Mackaff18a62012-07-25 17:56:48 +020023 #address-cells = <0x1>;
24 #size-cells = <0>;
25 status = "disabled";
26 };
27
28 nand0: nand@43100000 {
29 compatible = "marvell,pxa3xx-nand";
30 reg = <0x43100000 90>;
31 interrupts = <45>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010032 clocks = <&clks CLK_NAND>;
Daniel Mackaff18a62012-07-25 17:56:48 +020033 #address-cells = <1>;
34 #size-cells = <1>;
35 status = "disabled";
36 };
37
38 pxairq: interrupt-controller@40d00000 {
39 marvell,intc-priority;
40 marvell,intc-nr-irqs = <56>;
41 };
Daniel Mack93c5a5b2013-07-11 17:17:57 +020042
43 gpio: gpio@40e00000 {
44 compatible = "intel,pxa3xx-gpio";
45 reg = <0x40e00000 0x10000>;
Robert Jarzmikd96672e2015-02-07 13:13:24 +010046 clocks = <&clks CLK_GPIO>;
Daniel Mack93c5a5b2013-07-11 17:17:57 +020047 interrupt-names = "gpio0", "gpio1", "gpio_mux";
48 interrupts = <8 9 10>;
49 gpio-controller;
50 #gpio-cells = <0x2>;
51 interrupt-controller;
52 #interrupt-cells = <0x2>;
53 };
Daniel Mackaff18a62012-07-25 17:56:48 +020054 };
Robert Jarzmikd96672e2015-02-07 13:13:24 +010055
56 clocks {
57 /*
58 * The muxing of external clocks/internal dividers for osc* clock
59 * sources has been hidden under the carpet by now.
60 */
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 clks: pxa3xx_clks@41300004 {
66 compatible = "marvell,pxa300-clocks";
67 #clock-cells = <1>;
68 status = "okay";
69 };
70 };
Robert Jarzmik8dd30752014-10-12 22:11:08 +020071
72 timer@40a00000 {
73 compatible = "marvell,pxa-timer";
74 reg = <0x40a00000 0x20>;
75 interrupts = <26>;
76 clocks = <&clks CLK_OSTIMER>;
77 status = "okay";
78 };
Daniel Mackaff18a62012-07-25 17:56:48 +020079};