| Dan Murphy | 5069185 | 2020-08-31 11:48:49 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ */ |
| 3 | |
| 4 | #ifndef BQ25980_CHARGER_H |
| 5 | #define BQ25980_CHARGER_H |
| 6 | |
| 7 | #define BQ25980_MANUFACTURER "Texas Instruments" |
| 8 | |
| 9 | #define BQ25980_BATOVP 0x0 |
| 10 | #define BQ25980_BATOVP_ALM 0x1 |
| 11 | #define BQ25980_BATOCP 0x2 |
| 12 | #define BQ25980_BATOCP_ALM 0x3 |
| 13 | #define BQ25980_BATUCP_ALM 0x4 |
| 14 | #define BQ25980_CHRGR_CTRL_1 0x5 |
| 15 | #define BQ25980_BUSOVP 0x6 |
| 16 | #define BQ25980_BUSOVP_ALM 0x7 |
| 17 | #define BQ25980_BUSOCP 0x8 |
| 18 | #define BQ25980_BUSOCP_ALM 0x9 |
| 19 | #define BQ25980_TEMP_CONTROL 0xA |
| 20 | #define BQ25980_TDIE_ALM 0xB |
| 21 | #define BQ25980_TSBUS_FLT 0xC |
| 22 | #define BQ25980_TSBAT_FLG 0xD |
| 23 | #define BQ25980_VAC_CONTROL 0xE |
| 24 | #define BQ25980_CHRGR_CTRL_2 0xF |
| 25 | #define BQ25980_CHRGR_CTRL_3 0x10 |
| 26 | #define BQ25980_CHRGR_CTRL_4 0x11 |
| 27 | #define BQ25980_CHRGR_CTRL_5 0x12 |
| 28 | #define BQ25980_STAT1 0x13 |
| 29 | #define BQ25980_STAT2 0x14 |
| 30 | #define BQ25980_STAT3 0x15 |
| 31 | #define BQ25980_STAT4 0x16 |
| 32 | #define BQ25980_STAT5 0x17 |
| 33 | #define BQ25980_FLAG1 0x18 |
| 34 | #define BQ25980_FLAG2 0x19 |
| 35 | #define BQ25980_FLAG3 0x1A |
| 36 | #define BQ25980_FLAG4 0x1B |
| 37 | #define BQ25980_FLAG5 0x1C |
| 38 | #define BQ25980_MASK1 0x1D |
| 39 | #define BQ25980_MASK2 0x1E |
| 40 | #define BQ25980_MASK3 0x1F |
| 41 | #define BQ25980_MASK4 0x20 |
| 42 | #define BQ25980_MASK5 0x21 |
| 43 | #define BQ25980_DEVICE_INFO 0x22 |
| 44 | #define BQ25980_ADC_CONTROL1 0x23 |
| 45 | #define BQ25980_ADC_CONTROL2 0x24 |
| 46 | #define BQ25980_IBUS_ADC_MSB 0x25 |
| 47 | #define BQ25980_IBUS_ADC_LSB 0x26 |
| 48 | #define BQ25980_VBUS_ADC_MSB 0x27 |
| 49 | #define BQ25980_VBUS_ADC_LSB 0x28 |
| 50 | #define BQ25980_VAC1_ADC_MSB 0x29 |
| 51 | #define BQ25980_VAC1_ADC_LSB 0x2A |
| 52 | #define BQ25980_VAC2_ADC_MSB 0x2B |
| 53 | #define BQ25980_VAC2_ADC_LSB 0x2C |
| 54 | #define BQ25980_VOUT_ADC_MSB 0x2D |
| 55 | #define BQ25980_VOUT_ADC_LSB 0x2E |
| 56 | #define BQ25980_VBAT_ADC_MSB 0x2F |
| 57 | #define BQ25980_VBAT_ADC_LSB 0x30 |
| 58 | #define BQ25980_IBAT_ADC_MSB 0x31 |
| 59 | #define BQ25980_IBAT_ADC_LSB 0x32 |
| 60 | #define BQ25980_TSBUS_ADC_MSB 0x33 |
| 61 | #define BQ25980_TSBUS_ADC_LSB 0x34 |
| 62 | #define BQ25980_TSBAT_ADC_MSB 0x35 |
| 63 | #define BQ25980_TSBAT_ADC_LSB 0x36 |
| 64 | #define BQ25980_TDIE_ADC_MSB 0x37 |
| 65 | #define BQ25980_TDIE_ADC_LSB 0x38 |
| 66 | #define BQ25980_DEGLITCH_TIME 0x39 |
| 67 | #define BQ25980_CHRGR_CTRL_6 0x3A |
| 68 | |
| 69 | #define BQ25980_BUSOCP_STEP_uA 250000 |
| 70 | #define BQ25980_BUSOCP_OFFSET_uA 1000000 |
| 71 | |
| 72 | #define BQ25980_BUSOCP_DFLT_uA 4250000 |
| 73 | #define BQ25975_BUSOCP_DFLT_uA 4250000 |
| 74 | #define BQ25960_BUSOCP_DFLT_uA 3250000 |
| 75 | |
| 76 | #define BQ25980_BUSOCP_MIN_uA 1000000 |
| 77 | |
| 78 | #define BQ25980_BUSOCP_SC_MAX_uA 5750000 |
| 79 | #define BQ25975_BUSOCP_SC_MAX_uA 5750000 |
| 80 | #define BQ25960_BUSOCP_SC_MAX_uA 3750000 |
| 81 | |
| 82 | #define BQ25980_BUSOCP_BYP_MAX_uA 8500000 |
| 83 | #define BQ25975_BUSOCP_BYP_MAX_uA 8500000 |
| 84 | #define BQ25960_BUSOCP_BYP_MAX_uA 5750000 |
| 85 | |
| 86 | #define BQ25980_BUSOVP_SC_STEP_uV 100000 |
| 87 | #define BQ25975_BUSOVP_SC_STEP_uV 50000 |
| 88 | #define BQ25960_BUSOVP_SC_STEP_uV 50000 |
| 89 | #define BQ25980_BUSOVP_SC_OFFSET_uV 14000000 |
| 90 | #define BQ25975_BUSOVP_SC_OFFSET_uV 7000000 |
| 91 | #define BQ25960_BUSOVP_SC_OFFSET_uV 7000000 |
| 92 | |
| 93 | #define BQ25980_BUSOVP_BYP_STEP_uV 50000 |
| 94 | #define BQ25975_BUSOVP_BYP_STEP_uV 25000 |
| 95 | #define BQ25960_BUSOVP_BYP_STEP_uV 25000 |
| 96 | #define BQ25980_BUSOVP_BYP_OFFSET_uV 7000000 |
| 97 | #define BQ25975_BUSOVP_BYP_OFFSET_uV 3500000 |
| 98 | #define BQ25960_BUSOVP_BYP_OFFSET_uV 3500000 |
| 99 | |
| 100 | #define BQ25980_BUSOVP_DFLT_uV 17800000 |
| 101 | #define BQ25980_BUSOVP_BYPASS_DFLT_uV 8900000 |
| 102 | #define BQ25975_BUSOVP_DFLT_uV 8900000 |
| 103 | #define BQ25975_BUSOVP_BYPASS_DFLT_uV 4450000 |
| 104 | #define BQ25960_BUSOVP_DFLT_uV 8900000 |
| 105 | |
| 106 | #define BQ25980_BUSOVP_SC_MIN_uV 14000000 |
| 107 | #define BQ25975_BUSOVP_SC_MIN_uV 7000000 |
| 108 | #define BQ25960_BUSOVP_SC_MIN_uV 7000000 |
| 109 | #define BQ25980_BUSOVP_BYP_MIN_uV 7000000 |
| 110 | #define BQ25975_BUSOVP_BYP_MIN_uV 3500000 |
| 111 | #define BQ25960_BUSOVP_BYP_MIN_uV 3500000 |
| 112 | |
| 113 | #define BQ25980_BUSOVP_SC_MAX_uV 22000000 |
| 114 | #define BQ25975_BUSOVP_SC_MAX_uV 12750000 |
| 115 | #define BQ25960_BUSOVP_SC_MAX_uV 12750000 |
| 116 | |
| 117 | #define BQ25980_BUSOVP_BYP_MAX_uV 12750000 |
| 118 | #define BQ25975_BUSOVP_BYP_MAX_uV 6500000 |
| 119 | #define BQ25960_BUSOVP_BYP_MAX_uV 6500000 |
| 120 | |
| 121 | #define BQ25980_BATOVP_STEP_uV 20000 |
| 122 | #define BQ25975_BATOVP_STEP_uV 10000 |
| 123 | #define BQ25960_BATOVP_STEP_uV 10000 |
| 124 | |
| 125 | #define BQ25980_BATOVP_OFFSET_uV 7000000 |
| 126 | #define BQ25975_BATOVP_OFFSET_uV 3500000 |
| 127 | #define BQ25960_BATOVP_OFFSET_uV 3500000 |
| 128 | |
| 129 | #define BQ25980_BATOVP_DFLT_uV 14000000 |
| 130 | #define BQ25975_BATOVP_DFLT_uV 8900000 |
| 131 | #define BQ25960_BATOVP_DFLT_uV 8900000 |
| 132 | |
| 133 | #define BQ25980_BATOVP_MIN_uV 7000000 |
| 134 | #define BQ25975_BATOVP_MIN_uV 3500000 |
| 135 | #define BQ25960_BATOVP_MIN_uV 3500000 |
| 136 | |
| 137 | #define BQ25980_BATOVP_MAX_uV 9540000 |
| 138 | #define BQ25975_BATOVP_MAX_uV 4770000 |
| 139 | #define BQ25960_BATOVP_MAX_uV 4770000 |
| 140 | |
| 141 | #define BQ25980_BATOCP_STEP_uA 100000 |
| 142 | |
| 143 | #define BQ25980_BATOCP_MASK GENMASK(6, 0) |
| 144 | |
| 145 | #define BQ25980_BATOCP_DFLT_uA 8100000 |
| 146 | #define BQ25960_BATOCP_DFLT_uA 6100000 |
| 147 | |
| 148 | #define BQ25980_BATOCP_MIN_uA 2000000 |
| 149 | |
| 150 | #define BQ25980_BATOCP_MAX_uA 11000000 |
| 151 | #define BQ25975_BATOCP_MAX_uA 11000000 |
| 152 | #define BQ25960_BATOCP_MAX_uA 7000000 |
| 153 | |
| 154 | #define BQ25980_ENABLE_HIZ 0xff |
| 155 | #define BQ25980_DISABLE_HIZ 0x0 |
| 156 | #define BQ25980_EN_BYPASS BIT(3) |
| 157 | #define BQ25980_STAT1_OVP_MASK (BIT(6) | BIT(5) | BIT(0)) |
| 158 | #define BQ25980_STAT3_OVP_MASK (BIT(7) | BIT(6)) |
| 159 | #define BQ25980_STAT1_OCP_MASK BIT(3) |
| 160 | #define BQ25980_STAT2_OCP_MASK (BIT(6) | BIT(1)) |
| 161 | #define BQ25980_STAT4_TFLT_MASK GENMASK(5, 1) |
| 162 | #define BQ25980_WD_STAT BIT(0) |
| 163 | #define BQ25980_PRESENT_MASK GENMASK(4, 2) |
| 164 | #define BQ25980_CHG_EN BIT(4) |
| 165 | #define BQ25980_EN_HIZ BIT(6) |
| 166 | #define BQ25980_ADC_EN BIT(7) |
| 167 | |
| 168 | #define BQ25980_ADC_VOLT_STEP_uV 1000 |
| 169 | #define BQ25980_ADC_CURR_STEP_uA 1000 |
| 170 | #define BQ25980_ADC_POLARITY_BIT BIT(7) |
| 171 | |
| 172 | #define BQ25980_WATCHDOG_MASK GENMASK(4, 3) |
| 173 | #define BQ25980_WATCHDOG_DIS BIT(2) |
| 174 | #define BQ25980_WATCHDOG_MAX 300000 |
| 175 | #define BQ25980_WATCHDOG_MIN 0 |
| 176 | #define BQ25980_NUM_WD_VAL 4 |
| 177 | |
| 178 | #endif /* BQ25980_CHARGER_H */ |