Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 2 | |
Christoph Hellwig | d824e66 | 2006-04-10 22:54:04 -0700 | [diff] [blame] | 3 | #include <linux/irq.h> |
Yinghai Lu | 57b150c | 2009-04-27 17:59:53 -0700 | [diff] [blame] | 4 | #include <linux/interrupt.h> |
| 5 | |
| 6 | #include "internals.h" |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 7 | |
Thomas Gleixner | cdd1636 | 2017-06-20 01:37:19 +0200 | [diff] [blame] | 8 | /** |
| 9 | * irq_fixup_move_pending - Cleanup irq move pending from a dying CPU |
Krzysztof Kozlowski | 5c982c5 | 2021-03-16 11:02:05 +0100 | [diff] [blame] | 10 | * @desc: Interrupt descriptor to clean up |
Thomas Gleixner | cdd1636 | 2017-06-20 01:37:19 +0200 | [diff] [blame] | 11 | * @force_clear: If set clear the move pending bit unconditionally. |
| 12 | * If not set, clear it only when the dying CPU is the |
| 13 | * last one in the pending mask. |
| 14 | * |
| 15 | * Returns true if the pending bit was set and the pending mask contains an |
| 16 | * online CPU other than the dying CPU. |
| 17 | */ |
| 18 | bool irq_fixup_move_pending(struct irq_desc *desc, bool force_clear) |
| 19 | { |
| 20 | struct irq_data *data = irq_desc_get_irq_data(desc); |
| 21 | |
| 22 | if (!irqd_is_setaffinity_pending(data)) |
| 23 | return false; |
| 24 | |
| 25 | /* |
| 26 | * The outgoing CPU might be the last online target in a pending |
| 27 | * interrupt move. If that's the case clear the pending move bit. |
| 28 | */ |
| 29 | if (cpumask_any_and(desc->pending_mask, cpu_online_mask) >= nr_cpu_ids) { |
| 30 | irqd_clr_move_pending(data); |
| 31 | return false; |
| 32 | } |
| 33 | if (force_clear) |
| 34 | irqd_clr_move_pending(data); |
| 35 | return true; |
| 36 | } |
| 37 | |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 38 | void irq_move_masked_irq(struct irq_data *idata) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 39 | { |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 40 | struct irq_desc *desc = irq_data_to_desc(idata); |
Thomas Gleixner | a33a5d2 | 2018-06-04 17:33:54 +0200 | [diff] [blame] | 41 | struct irq_data *data = &desc->irq_data; |
| 42 | struct irq_chip *chip = data->chip; |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 43 | |
Thomas Gleixner | a33a5d2 | 2018-06-04 17:33:54 +0200 | [diff] [blame] | 44 | if (likely(!irqd_is_setaffinity_pending(data))) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 45 | return; |
| 46 | |
Thomas Gleixner | a33a5d2 | 2018-06-04 17:33:54 +0200 | [diff] [blame] | 47 | irqd_clr_move_pending(data); |
Thomas Gleixner | a614a610a | 2015-06-20 12:05:40 +0200 | [diff] [blame] | 48 | |
Bryan Holty | 501f249 | 2006-03-25 03:07:37 -0800 | [diff] [blame] | 49 | /* |
| 50 | * Paranoia: cpu-local interrupts shouldn't be calling in here anyway. |
| 51 | */ |
Thomas Gleixner | a33a5d2 | 2018-06-04 17:33:54 +0200 | [diff] [blame] | 52 | if (irqd_is_per_cpu(data)) { |
Bryan Holty | 501f249 | 2006-03-25 03:07:37 -0800 | [diff] [blame] | 53 | WARN_ON(1); |
| 54 | return; |
| 55 | } |
| 56 | |
Mike Travis | 7f7ace0 | 2009-01-10 21:58:08 -0800 | [diff] [blame] | 57 | if (unlikely(cpumask_empty(desc->pending_mask))) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 58 | return; |
| 59 | |
Thomas Gleixner | c96b3b3 | 2010-09-27 12:45:41 +0000 | [diff] [blame] | 60 | if (!chip->irq_set_affinity) |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 61 | return; |
| 62 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 63 | assert_raw_spin_locked(&desc->lock); |
Bryan Holty | 501f249 | 2006-03-25 03:07:37 -0800 | [diff] [blame] | 64 | |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 65 | /* |
| 66 | * If there was a valid mask to work with, please |
| 67 | * do the disable, re-program, enable sequence. |
| 68 | * This is *not* particularly important for level triggered |
| 69 | * but in a edge trigger case, we might be setting rte |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 70 | * when an active trigger is coming in. This could |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 71 | * cause some ioapics to mal-function. |
| 72 | * Being paranoid i guess! |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 73 | * |
| 74 | * For correct operation this depends on the caller |
| 75 | * masking the irqs. |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 76 | */ |
Thomas Gleixner | a33a5d2 | 2018-06-04 17:33:54 +0200 | [diff] [blame] | 77 | if (cpumask_any_and(desc->pending_mask, cpu_online_mask) < nr_cpu_ids) { |
| 78 | int ret; |
Yinghai Lu | 57b150c | 2009-04-27 17:59:53 -0700 | [diff] [blame] | 79 | |
Thomas Gleixner | a33a5d2 | 2018-06-04 17:33:54 +0200 | [diff] [blame] | 80 | ret = irq_do_set_affinity(data, desc->pending_mask, false); |
| 81 | /* |
| 82 | * If the there is a cleanup pending in the underlying |
| 83 | * vector management, reschedule the move for the next |
| 84 | * interrupt. Leave desc->pending_mask intact. |
| 85 | */ |
| 86 | if (ret == -EBUSY) { |
| 87 | irqd_set_move_pending(data); |
| 88 | return; |
| 89 | } |
| 90 | } |
Mike Travis | 7f7ace0 | 2009-01-10 21:58:08 -0800 | [diff] [blame] | 91 | cpumask_clear(desc->pending_mask); |
Andrew Morton | c777ac5 | 2006-03-25 03:07:36 -0800 | [diff] [blame] | 92 | } |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 93 | |
Thomas Gleixner | d340ebd | 2018-06-06 14:46:59 +0200 | [diff] [blame] | 94 | void __irq_move_irq(struct irq_data *idata) |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 95 | { |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 96 | bool masked; |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 97 | |
Jiang Liu | 77ed42f | 2015-06-01 16:05:11 +0800 | [diff] [blame] | 98 | /* |
| 99 | * Get top level irq_data when CONFIG_IRQ_DOMAIN_HIERARCHY is enabled, |
| 100 | * and it should be optimized away when CONFIG_IRQ_DOMAIN_HIERARCHY is |
| 101 | * disabled. So we avoid an "#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY" here. |
| 102 | */ |
| 103 | idata = irq_desc_get_irq_data(irq_data_to_desc(idata)); |
| 104 | |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 105 | if (unlikely(irqd_irq_disabled(idata))) |
Eric W. Biederman | 2a786b4 | 2007-02-23 04:46:20 -0700 | [diff] [blame] | 106 | return; |
Eric W. Biederman | e7b946e | 2006-10-04 02:16:29 -0700 | [diff] [blame] | 107 | |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 108 | /* |
| 109 | * Be careful vs. already masked interrupts. If this is a |
| 110 | * threaded interrupt with ONESHOT set, we can end up with an |
| 111 | * interrupt storm. |
| 112 | */ |
Thomas Gleixner | 32f4125 | 2011-03-28 14:10:52 +0200 | [diff] [blame] | 113 | masked = irqd_irq_masked(idata); |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 114 | if (!masked) |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 115 | idata->chip->irq_mask(idata); |
| 116 | irq_move_masked_irq(idata); |
Thomas Gleixner | f1a0639 | 2011-01-28 08:47:15 +0100 | [diff] [blame] | 117 | if (!masked) |
Thomas Gleixner | a439520 | 2011-02-04 18:46:16 +0100 | [diff] [blame] | 118 | idata->chip->irq_unmask(idata); |
| 119 | } |