blob: 89c9f36dc94d264482a61bd750bb19830cf81910 [file] [log] [blame]
Thomas Gleixner457c8992019-05-19 13:08:55 +01001// SPDX-License-Identifier: GPL-2.0-only
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
3 * pci.c - Low-Level PCI Access in IA-64
4 *
5 * Derived from bios32.c of i386 tree.
6 *
7 * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
8 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Bjorn Helgaas <bjorn.helgaas@hp.com>
10 * Copyright (C) 2004 Silicon Graphics, Inc.
11 *
12 * Note: Above list of copyright holders is incomplete...
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014
15#include <linux/acpi.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
Jiang Liub02a4a12013-04-12 05:44:22 +000019#include <linux/pci-acpi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/spinlock.h>
Mike Rapoport57c8a662018-10-30 15:09:49 -070024#include <linux/memblock.h>
Paul Gortmakerbd3ff192011-07-31 18:33:21 -040025#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026
27#include <asm/machvec.h>
28#include <asm/page.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070029#include <asm/io.h>
30#include <asm/sal.h>
31#include <asm/smp.h>
32#include <asm/irq.h>
33#include <asm/hw_irq.h>
34
Linus Torvalds1da177e2005-04-16 15:20:36 -070035/*
36 * Low-level SAL-based PCI configuration access functions. Note that SAL
37 * calls are already serialized (via sal_lock), so we don't need another
38 * synchronization mechanism here.
39 */
40
41#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
42 (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
43
44/* SAL 3.2 adds support for extended config space. */
45
46#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
47 (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
48
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -050049int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
Linus Torvalds1da177e2005-04-16 15:20:36 -070050 int reg, int len, u32 *value)
51{
52 u64 addr, data = 0;
53 int mode, result;
54
55 if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
56 return -EINVAL;
57
58 if ((seg | reg) <= 255) {
59 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
60 mode = 0;
Matthew Wilcoxadcd7402009-10-12 08:24:30 -060061 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070062 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
63 mode = 1;
Matthew Wilcoxadcd7402009-10-12 08:24:30 -060064 } else {
65 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 }
Matthew Wilcoxadcd7402009-10-12 08:24:30 -060067
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 result = ia64_sal_pci_config_read(addr, mode, len, &data);
69 if (result != 0)
70 return -EINVAL;
71
72 *value = (u32) data;
73 return 0;
74}
75
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -050076int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
Linus Torvalds1da177e2005-04-16 15:20:36 -070077 int reg, int len, u32 value)
78{
79 u64 addr;
80 int mode, result;
81
82 if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
83 return -EINVAL;
84
85 if ((seg | reg) <= 255) {
86 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
87 mode = 0;
Matthew Wilcoxadcd7402009-10-12 08:24:30 -060088 } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
90 mode = 1;
Matthew Wilcoxadcd7402009-10-12 08:24:30 -060091 } else {
92 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 }
94 result = ia64_sal_pci_config_write(addr, mode, len, value);
95 if (result != 0)
96 return -EINVAL;
97 return 0;
98}
99
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500100static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
101 int size, u32 *value)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102{
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500103 return raw_pci_read(pci_domain_nr(bus), bus->number,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 devfn, where, size, value);
105}
106
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500107static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
108 int size, u32 value)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109{
Matthew Wilcoxb6ce0682008-02-10 09:45:28 -0500110 return raw_pci_write(pci_domain_nr(bus), bus->number,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 devfn, where, size, value);
112}
113
114struct pci_ops pci_root_ops = {
115 .read = pci_read,
116 .write = pci_write,
117};
118
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700119struct pci_root_info {
Jiang Liu02715e82015-10-14 14:29:42 +0800120 struct acpi_pci_root_info common;
Jiang Liu3772aea2015-10-14 14:29:37 +0800121 struct pci_controller controller;
Jiang Liuc9e391c2013-06-06 15:34:50 +0800122 struct list_head io_resources;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700123};
124
Jiang Liu02715e82015-10-14 14:29:42 +0800125static unsigned int new_space(u64 phys_base, int sparse)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126{
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700127 u64 mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 int i;
129
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700130 if (phys_base == 0)
131 return 0; /* legacy I/O port space */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700133 mmio_base = (u64) ioremap(phys_base, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134 for (i = 0; i < num_io_spaces; i++)
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700135 if (io_space[i].mmio_base == mmio_base &&
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 io_space[i].sparse == sparse)
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700137 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138
139 if (num_io_spaces == MAX_IO_SPACES) {
Yijing Wangc4cbf6b2013-06-06 15:34:53 +0800140 pr_err("PCI: Too many IO port spaces "
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700141 "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 return ~0;
143 }
144
145 i = num_io_spaces++;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700146 io_space[i].mmio_base = mmio_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 io_space[i].sparse = sparse;
148
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700149 return i;
150}
151
Jiang Liu3772aea2015-10-14 14:29:37 +0800152static int add_io_space(struct device *dev, struct pci_root_info *info,
153 struct resource_entry *entry)
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700154{
Jiang Liu3f7abde2015-10-14 14:29:38 +0800155 struct resource_entry *iospace;
Jiang Liu3772aea2015-10-14 14:29:37 +0800156 struct resource *resource, *res = entry->res;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700157 char *name;
Matthew Wilcoxe088a4a2009-05-22 13:49:49 -0700158 unsigned long base, min, max, base_port;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700159 unsigned int sparse = 0, space_nr, len;
160
Jiang Liu02715e82015-10-14 14:29:42 +0800161 len = strlen(info->common.name) + 32;
Jiang Liu3f7abde2015-10-14 14:29:38 +0800162 iospace = resource_list_create_entry(NULL, len);
Jiang Liuc9e391c2013-06-06 15:34:50 +0800163 if (!iospace) {
Jiang Liu3772aea2015-10-14 14:29:37 +0800164 dev_err(dev, "PCI: No memory for %s I/O port space\n",
Jiang Liu02715e82015-10-14 14:29:42 +0800165 info->common.name);
Jiang Liu3772aea2015-10-14 14:29:37 +0800166 return -ENOMEM;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700167 }
168
Jiang Liu3772aea2015-10-14 14:29:37 +0800169 if (res->flags & IORESOURCE_IO_SPARSE)
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700170 sparse = 1;
Jiang Liu3772aea2015-10-14 14:29:37 +0800171 space_nr = new_space(entry->offset, sparse);
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700172 if (space_nr == ~0)
Jiang Liuc9e391c2013-06-06 15:34:50 +0800173 goto free_resource;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700174
Jiang Liu3772aea2015-10-14 14:29:37 +0800175 name = (char *)(iospace + 1);
176 min = res->start - entry->offset;
177 max = res->end - entry->offset;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700178 base = __pa(io_space[space_nr].mmio_base);
179 base_port = IO_SPACE_BASE(space_nr);
Jiang Liu02715e82015-10-14 14:29:42 +0800180 snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->common.name,
Jiang Liu3772aea2015-10-14 14:29:37 +0800181 base_port + min, base_port + max);
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700182
183 /*
184 * The SDM guarantees the legacy 0-64K space is sparse, but if the
185 * mapping is done by the processor (not the bridge), ACPI may not
186 * mark it as sparse.
187 */
188 if (space_nr == 0)
189 sparse = 1;
190
Jiang Liu3f7abde2015-10-14 14:29:38 +0800191 resource = iospace->res;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700192 resource->name = name;
193 resource->flags = IORESOURCE_MEM;
194 resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
195 resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
Jiang Liuc9e391c2013-06-06 15:34:50 +0800196 if (insert_resource(&iomem_resource, resource)) {
Jiang Liu3772aea2015-10-14 14:29:37 +0800197 dev_err(dev,
198 "can't allocate host bridge io space resource %pR\n",
199 resource);
Jiang Liuc9e391c2013-06-06 15:34:50 +0800200 goto free_resource;
201 }
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700202
Jiang Liu3772aea2015-10-14 14:29:37 +0800203 entry->offset = base_port;
204 res->start = min + base_port;
205 res->end = max + base_port;
Jiang Liu3f7abde2015-10-14 14:29:38 +0800206 resource_list_add_tail(iospace, &info->io_resources);
Jiang Liu3772aea2015-10-14 14:29:37 +0800207
208 return 0;
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700209
Bjorn Helgaas4f41d5a2005-11-07 15:13:59 -0700210free_resource:
Jiang Liu3f7abde2015-10-14 14:29:38 +0800211 resource_list_free_entry(iospace);
Jiang Liu3772aea2015-10-14 14:29:37 +0800212 return -ENOSPC;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213}
214
Jiang Liu3772aea2015-10-14 14:29:37 +0800215/*
216 * An IO port or MMIO resource assigned to a PCI host bridge may be
217 * consumed by the host bridge itself or available to its child
218 * bus/devices. The ACPI specification defines a bit (Producer/Consumer)
219 * to tell whether the resource is consumed by the host bridge itself,
220 * but firmware hasn't used that bit consistently, so we can't rely on it.
221 *
222 * On x86 and IA64 platforms, all IO port and MMIO resources are assumed
223 * to be available to child bus/devices except one special case:
224 * IO port [0xCF8-0xCFF] is consumed by the host bridge itself
225 * to access PCI configuration space.
226 *
227 * So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
228 */
229static bool resource_is_pcicfg_ioport(struct resource *res)
Bjorn Helgaas463eb292005-09-23 11:39:07 -0600230{
Jiang Liu3772aea2015-10-14 14:29:37 +0800231 return (res->flags & IORESOURCE_IO) &&
232 res->start == 0xCF8 && res->end == 0xCFF;
Bjorn Helgaas463eb292005-09-23 11:39:07 -0600233}
234
Jiang Liu02715e82015-10-14 14:29:42 +0800235static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236{
Jiang Liu02715e82015-10-14 14:29:42 +0800237 struct device *dev = &ci->bridge->dev;
238 struct pci_root_info *info;
Jiang Liuc9e391c2013-06-06 15:34:50 +0800239 struct resource *res;
Jiang Liu02715e82015-10-14 14:29:42 +0800240 struct resource_entry *entry, *tmp;
241 int status;
Jiang Liuc9e391c2013-06-06 15:34:50 +0800242
Jiang Liu02715e82015-10-14 14:29:42 +0800243 status = acpi_pci_probe_root_resources(ci);
244 if (status > 0) {
245 info = container_of(ci, struct pci_root_info, common);
246 resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
247 res = entry->res;
248 if (res->flags & IORESOURCE_MEM) {
249 /*
250 * HP's firmware has a hack to work around a
251 * Windows bug. Ignore these tiny memory ranges.
252 */
253 if (resource_size(res) <= 16) {
254 resource_list_del(entry);
255 insert_resource(&iomem_resource,
256 entry->res);
257 resource_list_add_tail(entry,
258 &info->io_resources);
259 }
260 } else if (res->flags & IORESOURCE_IO) {
261 if (resource_is_pcicfg_ioport(entry->res))
262 resource_list_destroy_entry(entry);
263 else if (add_io_space(dev, info, entry))
264 resource_list_destroy_entry(entry);
265 }
266 }
267 }
268
269 return status;
270}
271
272static void pci_acpi_root_release_info(struct acpi_pci_root_info *ci)
273{
274 struct pci_root_info *info;
275 struct resource_entry *entry, *tmp;
276
277 info = container_of(ci, struct pci_root_info, common);
278 resource_list_for_each_entry_safe(entry, tmp, &info->io_resources) {
Jiang Liu3f7abde2015-10-14 14:29:38 +0800279 release_resource(entry->res);
280 resource_list_destroy_entry(entry);
Jiang Liuc9e391c2013-06-06 15:34:50 +0800281 }
Jiang Liuc9e391c2013-06-06 15:34:50 +0800282 kfree(info);
283}
284
Jiang Liu02715e82015-10-14 14:29:42 +0800285static struct acpi_pci_root_ops pci_acpi_root_ops = {
286 .pci_ops = &pci_root_ops,
287 .release_info = pci_acpi_root_release_info,
288 .prepare_resources = pci_acpi_root_prepare_resources,
289};
Yijing Wang29322392013-06-06 15:34:51 +0800290
Greg Kroah-Hartman5b5e76e2012-12-21 14:05:13 -0800291struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292{
Bjorn Helgaas57283772010-03-11 12:20:11 -0700293 struct acpi_device *device = root->device;
Jiang Liu3772aea2015-10-14 14:29:37 +0800294 struct pci_root_info *info;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295
Yijing Wang429ac092013-06-06 15:34:49 +0800296 info = kzalloc(sizeof(*info), GFP_KERNEL);
297 if (!info) {
Yijing Wangc4cbf6b2013-06-06 15:34:53 +0800298 dev_err(&device->dev,
Jiang Liu3772aea2015-10-14 14:29:37 +0800299 "pci_bus %04x:%02x: ignored (out of memory)\n",
Jiang Liu02715e82015-10-14 14:29:42 +0800300 root->segment, (int)root->secondary.start);
Yijing Wang3a72af02013-06-06 15:34:52 +0800301 return NULL;
Yijing Wang429ac092013-06-06 15:34:49 +0800302 }
Luck, Tony8a20fd52008-08-15 15:37:48 -0700303
Jiang Liu02715e82015-10-14 14:29:42 +0800304 info->controller.segment = root->segment;
Jiang Liu3772aea2015-10-14 14:29:37 +0800305 info->controller.companion = device;
306 info->controller.node = acpi_get_node(device->handle);
Jiang Liu3772aea2015-10-14 14:29:37 +0800307 INIT_LIST_HEAD(&info->io_resources);
Jiang Liu02715e82015-10-14 14:29:42 +0800308 return acpi_pci_root_create(root, &pci_acpi_root_ops,
309 &info->common, &info->controller);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310}
311
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +0100312int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
313{
Rafael J. Wysockidc4fdaf2015-05-28 01:39:53 +0200314 /*
315 * We pass NULL as parent to pci_create_root_bus(), so if it is not NULL
316 * here, pci_create_root_bus() has been called by someone else and
317 * sysdata is likely to be different from what we expect. Let it go in
318 * that case.
319 */
320 if (!bridge->dev.parent) {
321 struct pci_controller *controller = bridge->bus->sysdata;
322 ACPI_COMPANION_SET(&bridge->dev, controller->companion);
323 }
Rafael J. Wysocki6c0cc952013-01-09 22:33:37 +0100324 return 0;
325}
326
Greg Kroah-Hartman5b5e76e2012-12-21 14:05:13 -0800327void pcibios_fixup_device_resources(struct pci_dev *dev)
Kenji Kaneshige7b9c8ba2006-01-16 13:45:23 +0900328{
Yinghai Luce821ef2015-01-15 16:21:50 -0600329 int idx;
330
331 if (!dev->bus)
332 return;
333
334 for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) {
335 struct resource *r = &dev->resource[idx];
336
337 if (!r->flags || r->parent || !r->start)
338 continue;
339
340 pci_claim_resource(dev, idx);
341 }
Kenji Kaneshige7b9c8ba2006-01-16 13:45:23 +0900342}
John Keller8ea60912006-10-04 16:49:25 -0500343EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
Kenji Kaneshige7b9c8ba2006-01-16 13:45:23 +0900344
Greg Kroah-Hartman5b5e76e2012-12-21 14:05:13 -0800345static void pcibios_fixup_bridge_resources(struct pci_dev *dev)
Kenji Kaneshige7b9c8ba2006-01-16 13:45:23 +0900346{
Yinghai Luce821ef2015-01-15 16:21:50 -0600347 int idx;
348
349 if (!dev->bus)
350 return;
351
352 for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
353 struct resource *r = &dev->resource[idx];
354
355 if (!r->flags || r->parent || !r->start)
356 continue;
357
358 pci_claim_bridge_resource(dev, idx);
359 }
Kenji Kaneshige7b9c8ba2006-01-16 13:45:23 +0900360}
361
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362/*
363 * Called after each bus is probed, but before its children are examined.
364 */
Greg Kroah-Hartman5b5e76e2012-12-21 14:05:13 -0800365void pcibios_fixup_bus(struct pci_bus *b)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366{
367 struct pci_dev *dev;
368
Bjorn Helgaas237865f2015-09-15 13:18:04 -0500369 if (b->self) {
370 pci_read_bridge_bases(b);
Kenji Kaneshige7b9c8ba2006-01-16 13:45:23 +0900371 pcibios_fixup_bridge_resources(b->self);
Bjorn Helgaas237865f2015-09-15 13:18:04 -0500372 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700373 list_for_each_entry(dev, &b->devices, bus_list)
374 pcibios_fixup_device_resources(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375}
376
Jiang Liub02a4a12013-04-12 05:44:22 +0000377void pcibios_add_bus(struct pci_bus *bus)
378{
379 acpi_pci_add_bus(bus);
380}
381
382void pcibios_remove_bus(struct pci_bus *bus)
383{
384 acpi_pci_remove_bus(bus);
385}
386
Myron Stowe91e86df2011-10-28 15:47:49 -0600387void pcibios_set_master (struct pci_dev *dev)
388{
389 /* No special bus mastering setup handling */
390}
391
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392int
393pcibios_enable_device (struct pci_dev *dev, int mask)
394{
395 int ret;
396
Bjorn Helgaasd981f162008-03-04 11:56:52 -0700397 ret = pci_enable_resources(dev, mask);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 if (ret < 0)
399 return ret;
400
Bjorn Helgaas5a1e0ba2018-03-13 15:03:36 -0500401 if (!pci_dev_msi_enabled(dev))
Eric W. Biedermanbba6f6f2007-03-28 15:36:09 +0200402 return acpi_pci_irq_enable(dev);
403 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404}
405
Linus Torvalds1da177e2005-04-16 15:20:36 -0700406void
407pcibios_disable_device (struct pci_dev *dev)
408{
Peter Chubbc7f570a2006-12-05 12:25:31 +1100409 BUG_ON(atomic_read(&dev->enable_cnt));
Bjorn Helgaas5a1e0ba2018-03-13 15:03:36 -0500410 if (!pci_dev_msi_enabled(dev))
Eric W. Biedermanbba6f6f2007-03-28 15:36:09 +0200411 acpi_pci_irq_disable(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
Linus Torvalds1da177e2005-04-16 15:20:36 -0700414/**
Christoph Hellwig05933aa2019-08-13 09:25:02 +0200415 * pci_get_legacy_mem - generic legacy mem routine
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 * @bus: bus to get legacy memory base address for
417 *
418 * Find the base of legacy memory for @bus. This is typically the first
419 * megabyte of bus address space for @bus or is simply 0 on platforms whose
420 * chipsets support legacy I/O and memory routing. Returns the base address
421 * or an error pointer if an error occurred.
422 *
423 * This is the ia64 generic version of this routine. Other platforms
424 * are free to override it with a machine vector.
425 */
Christoph Hellwig05933aa2019-08-13 09:25:02 +0200426char *pci_get_legacy_mem(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427{
428 return (char *)__IA64_UNCACHED_OFFSET;
429}
430
431/**
432 * pci_mmap_legacy_page_range - map legacy memory space to userland
433 * @bus: bus whose legacy space we're mapping
434 * @vma: vma passed in by mmap
435 *
436 * Map legacy memory space for this device back to userspace using a machine
437 * vector to get the base address.
438 */
439int
Benjamin Herrenschmidtf19aeb12008-10-03 19:49:32 +1000440pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
441 enum pci_mmap_state mmap_state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442{
Bjorn Helgaas32e62c62006-05-05 17:19:50 -0600443 unsigned long size = vma->vm_end - vma->vm_start;
444 pgprot_t prot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 char *addr;
446
Benjamin Herrenschmidtf19aeb12008-10-03 19:49:32 +1000447 /* We only support mmap'ing of legacy memory space */
448 if (mmap_state != pci_mmap_mem)
449 return -ENOSYS;
450
Bjorn Helgaas32e62c62006-05-05 17:19:50 -0600451 /*
Mauro Carvalho Chehabdb9a0972019-04-18 10:10:33 -0300452 * Avoid attribute aliasing. See Documentation/ia64/aliasing.rst
Bjorn Helgaas32e62c62006-05-05 17:19:50 -0600453 * for more details.
454 */
Lennert Buytenhek06c67be2006-07-10 04:45:27 -0700455 if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
Bjorn Helgaas32e62c62006-05-05 17:19:50 -0600456 return -EINVAL;
457 prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
458 vma->vm_page_prot);
Bjorn Helgaas32e62c62006-05-05 17:19:50 -0600459
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 addr = pci_get_legacy_mem(bus);
461 if (IS_ERR(addr))
462 return PTR_ERR(addr);
463
464 vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
Bjorn Helgaas32e62c62006-05-05 17:19:50 -0600465 vma->vm_page_prot = prot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700466
467 if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
Bjorn Helgaas32e62c62006-05-05 17:19:50 -0600468 size, vma->vm_page_prot))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469 return -EAGAIN;
470
471 return 0;
472}
473
474/**
Christoph Hellwig05933aa2019-08-13 09:25:02 +0200475 * pci_legacy_read - read from legacy I/O space
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476 * @bus: bus to read
477 * @port: legacy port value
478 * @val: caller allocated storage for returned value
479 * @size: number of bytes to read
480 *
481 * Simply reads @size bytes from @port and puts the result in @val.
482 *
483 * Again, this (and the write routine) are generic versions that can be
484 * overridden by the platform. This is necessary on platforms that don't
485 * support legacy I/O routing or that hard fail on legacy I/O timeouts.
486 */
Christoph Hellwig05933aa2019-08-13 09:25:02 +0200487int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488{
489 int ret = size;
490
491 switch (size) {
492 case 1:
493 *val = inb(port);
494 break;
495 case 2:
496 *val = inw(port);
497 break;
498 case 4:
499 *val = inl(port);
500 break;
501 default:
502 ret = -EINVAL;
503 break;
504 }
505
506 return ret;
507}
508
509/**
Christoph Hellwig05933aa2019-08-13 09:25:02 +0200510 * pci_legacy_write - perform a legacy I/O write
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 * @bus: bus pointer
512 * @port: port to write
513 * @val: value to write
514 * @size: number of bytes to write from @val
515 *
516 * Simply writes @size bytes of @val to @port.
517 */
Christoph Hellwig05933aa2019-08-13 09:25:02 +0200518int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519{
Alex Williamson408045a2005-12-21 15:21:36 -0700520 int ret = size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521
522 switch (size) {
523 case 1:
524 outb(val, port);
525 break;
526 case 2:
527 outw(val, port);
528 break;
529 case 4:
530 outl(val, port);
531 break;
532 default:
533 ret = -EINVAL;
534 break;
535 }
536
537 return ret;
538}
539
540/**
Matthew Wilcox3efe2d82006-10-10 08:01:19 -0600541 * set_pci_cacheline_size - determine cacheline size for PCI devices
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542 *
543 * We want to use the line-size of the outer-most cache. We assume
544 * that this line-size is the same for all CPUs.
545 *
546 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547 */
Jesse Barnesac1aa472009-10-26 13:20:44 -0700548static void __init set_pci_dfl_cacheline_size(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700549{
Matthew Wilcoxe088a4a2009-05-22 13:49:49 -0700550 unsigned long levels, unique_caches;
551 long status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552 pal_cache_config_info_t cci;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700553
554 status = ia64_pal_cache_summary(&levels, &unique_caches);
555 if (status != 0) {
Yijing Wangc4cbf6b2013-06-06 15:34:53 +0800556 pr_err("%s: ia64_pal_cache_summary() failed "
Harvey Harrisond4ed8082008-03-04 15:15:00 -0800557 "(status=%ld)\n", __func__, status);
Matthew Wilcox3efe2d82006-10-10 08:01:19 -0600558 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700559 }
560
Matthew Wilcox3efe2d82006-10-10 08:01:19 -0600561 status = ia64_pal_cache_config_info(levels - 1,
562 /* cache_type (data_or_unified)= */ 2, &cci);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700563 if (status != 0) {
Yijing Wangc4cbf6b2013-06-06 15:34:53 +0800564 pr_err("%s: ia64_pal_cache_config_info() failed "
Harvey Harrisond4ed8082008-03-04 15:15:00 -0800565 "(status=%ld)\n", __func__, status);
Matthew Wilcox3efe2d82006-10-10 08:01:19 -0600566 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 }
Jesse Barnesac1aa472009-10-26 13:20:44 -0700568 pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700569}
570
Matthew Wilcox3efe2d82006-10-10 08:01:19 -0600571static int __init pcibios_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700572{
Jesse Barnesac1aa472009-10-26 13:20:44 -0700573 set_pci_dfl_cacheline_size();
Matthew Wilcox3efe2d82006-10-10 08:01:19 -0600574 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575}
Matthew Wilcox3efe2d82006-10-10 08:01:19 -0600576
577subsys_initcall(pcibios_init);