Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the MDIO interface of Marvell network interfaces. |
| 3 | * |
| 4 | * Since the MDIO interface of Marvell network interfaces is shared |
| 5 | * between all network interfaces, having a single driver allows to |
| 6 | * handle concurrent accesses properly (you may have four Ethernet |
Leigh Brown | d4a0acb | 2013-10-29 09:33:34 +0000 | [diff] [blame] | 7 | * ports, but they in fact share the same SMI interface to access |
| 8 | * the MDIO bus). This driver is currently used by the mvneta and |
| 9 | * mv643xx_eth drivers. |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 10 | * |
| 11 | * Copyright (C) 2012 Marvell |
| 12 | * |
| 13 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 14 | * |
| 15 | * This file is licensed under the terms of the GNU General Public |
| 16 | * License version 2. This program is licensed "as is" without any |
| 17 | * warranty of any kind, whether express or implied. |
| 18 | */ |
| 19 | |
Antoine Ténart | 14ef8b3 | 2017-06-15 16:43:16 +0200 | [diff] [blame] | 20 | #include <linux/clk.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/io.h> |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 24 | #include <linux/kernel.h> |
| 25 | #include <linux/module.h> |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 26 | #include <linux/of_device.h> |
Florian Fainelli | 7111b71 | 2013-03-22 03:39:25 +0000 | [diff] [blame] | 27 | #include <linux/of_mdio.h> |
Antoine Ténart | 14ef8b3 | 2017-06-15 16:43:16 +0200 | [diff] [blame] | 28 | #include <linux/phy.h> |
| 29 | #include <linux/platform_device.h> |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 30 | #include <linux/sched.h> |
| 31 | #include <linux/wait.h> |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 32 | |
Antoine Ténart | 2040ef2 | 2017-06-15 16:43:17 +0200 | [diff] [blame] | 33 | #define MVMDIO_SMI_DATA_SHIFT 0 |
| 34 | #define MVMDIO_SMI_PHY_ADDR_SHIFT 16 |
| 35 | #define MVMDIO_SMI_PHY_REG_SHIFT 21 |
| 36 | #define MVMDIO_SMI_READ_OPERATION BIT(26) |
| 37 | #define MVMDIO_SMI_WRITE_OPERATION 0 |
| 38 | #define MVMDIO_SMI_READ_VALID BIT(27) |
| 39 | #define MVMDIO_SMI_BUSY BIT(28) |
| 40 | #define MVMDIO_ERR_INT_CAUSE 0x007C |
| 41 | #define MVMDIO_ERR_INT_SMI_DONE 0x00000010 |
| 42 | #define MVMDIO_ERR_INT_MASK 0x0080 |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 43 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 44 | #define MVMDIO_XSMI_MGNT_REG 0x0 |
| 45 | #define MVMDIO_XSMI_PHYADDR_SHIFT 16 |
| 46 | #define MVMDIO_XSMI_DEVADDR_SHIFT 21 |
| 47 | #define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26) |
| 48 | #define MVMDIO_XSMI_READ_OPERATION (0x7 << 26) |
| 49 | #define MVMDIO_XSMI_READ_VALID BIT(29) |
| 50 | #define MVMDIO_XSMI_BUSY BIT(30) |
| 51 | #define MVMDIO_XSMI_ADDR_REG 0x8 |
| 52 | |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 53 | /* |
| 54 | * SMI Timeout measurements: |
| 55 | * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt) |
| 56 | * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled) |
| 57 | */ |
Antoine Ténart | 2040ef2 | 2017-06-15 16:43:17 +0200 | [diff] [blame] | 58 | #define MVMDIO_SMI_TIMEOUT 1000 /* 1000us = 1ms */ |
| 59 | #define MVMDIO_SMI_POLL_INTERVAL_MIN 45 |
| 60 | #define MVMDIO_SMI_POLL_INTERVAL_MAX 55 |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 61 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 62 | #define MVMDIO_XSMI_POLL_INTERVAL_MIN 150 |
| 63 | #define MVMDIO_XSMI_POLL_INTERVAL_MAX 160 |
| 64 | |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 65 | struct orion_mdio_dev { |
Florian Fainelli | 3712b71 | 2013-03-22 03:39:26 +0000 | [diff] [blame] | 66 | void __iomem *regs; |
Russell King | 96cb434 | 2017-04-10 16:28:31 +0100 | [diff] [blame] | 67 | struct clk *clk[3]; |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 68 | /* |
| 69 | * If we have access to the error interrupt pin (which is |
| 70 | * somewhat misnamed as it not only reflects internal errors |
| 71 | * but also reflects SMI completion), use that to wait for |
| 72 | * SMI access completion instead of polling the SMI busy bit. |
| 73 | */ |
| 74 | int err_interrupt; |
| 75 | wait_queue_head_t smi_busy_wait; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 76 | }; |
| 77 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 78 | enum orion_mdio_bus_type { |
| 79 | BUS_TYPE_SMI, |
| 80 | BUS_TYPE_XSMI |
| 81 | }; |
| 82 | |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 83 | struct orion_mdio_ops { |
| 84 | int (*is_done)(struct orion_mdio_dev *); |
Antoine Ténart | 1955796 | 2017-06-15 16:43:21 +0200 | [diff] [blame] | 85 | unsigned int poll_interval_min; |
| 86 | unsigned int poll_interval_max; |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 87 | }; |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 88 | |
Thomas Petazzoni | b07812f | 2012-11-19 11:40:15 +0100 | [diff] [blame] | 89 | /* Wait for the SMI unit to be ready for another operation |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 90 | */ |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 91 | static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops, |
| 92 | struct mii_bus *bus) |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 93 | { |
| 94 | struct orion_mdio_dev *dev = bus->priv; |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 95 | unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT); |
| 96 | unsigned long end = jiffies + timeout; |
| 97 | int timedout = 0; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 98 | |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 99 | while (1) { |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 100 | if (ops->is_done(dev)) |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 101 | return 0; |
| 102 | else if (timedout) |
| 103 | break; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 104 | |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 105 | if (dev->err_interrupt <= 0) { |
Antoine Ténart | 1955796 | 2017-06-15 16:43:21 +0200 | [diff] [blame] | 106 | usleep_range(ops->poll_interval_min, |
| 107 | ops->poll_interval_max); |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 108 | |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 109 | if (time_is_before_jiffies(end)) |
| 110 | ++timedout; |
| 111 | } else { |
Leigh Brown | 1a1f20b | 2013-12-19 13:09:48 +0000 | [diff] [blame] | 112 | /* wait_event_timeout does not guarantee a delay of at |
| 113 | * least one whole jiffie, so timeout must be no less |
| 114 | * than two. |
| 115 | */ |
| 116 | if (timeout < 2) |
| 117 | timeout = 2; |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 118 | wait_event_timeout(dev->smi_busy_wait, |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 119 | ops->is_done(dev), timeout); |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 120 | |
| 121 | ++timedout; |
| 122 | } |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 123 | } |
| 124 | |
Leigh Brown | b70cd1c | 2013-10-29 09:33:31 +0000 | [diff] [blame] | 125 | dev_err(bus->parent, "Timeout: SMI busy for too long\n"); |
| 126 | return -ETIMEDOUT; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 127 | } |
| 128 | |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 129 | static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev) |
| 130 | { |
| 131 | return !(readl(dev->regs) & MVMDIO_SMI_BUSY); |
| 132 | } |
| 133 | |
| 134 | static const struct orion_mdio_ops orion_mdio_smi_ops = { |
| 135 | .is_done = orion_mdio_smi_is_done, |
Antoine Ténart | 1955796 | 2017-06-15 16:43:21 +0200 | [diff] [blame] | 136 | .poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN, |
| 137 | .poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX, |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 138 | }; |
| 139 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 140 | static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id, |
| 141 | int regnum) |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 142 | { |
| 143 | struct orion_mdio_dev *dev = bus->priv; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 144 | u32 val; |
| 145 | int ret; |
| 146 | |
Antoine Ténart | 440ea77 | 2017-06-15 16:43:22 +0200 | [diff] [blame] | 147 | if (regnum & MII_ADDR_C45) |
| 148 | return -EOPNOTSUPP; |
| 149 | |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 150 | ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus); |
Leigh Brown | 839f46b | 2013-10-29 09:33:32 +0000 | [diff] [blame] | 151 | if (ret < 0) |
Antoine Ténart | 0268b51 | 2017-06-15 16:43:24 +0200 | [diff] [blame^] | 152 | return ret; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 153 | |
| 154 | writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) | |
| 155 | (regnum << MVMDIO_SMI_PHY_REG_SHIFT) | |
| 156 | MVMDIO_SMI_READ_OPERATION), |
Florian Fainelli | 3712b71 | 2013-03-22 03:39:26 +0000 | [diff] [blame] | 157 | dev->regs); |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 158 | |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 159 | ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus); |
Leigh Brown | 839f46b | 2013-10-29 09:33:32 +0000 | [diff] [blame] | 160 | if (ret < 0) |
Antoine Ténart | 0268b51 | 2017-06-15 16:43:24 +0200 | [diff] [blame^] | 161 | return ret; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 162 | |
Leigh Brown | 839f46b | 2013-10-29 09:33:32 +0000 | [diff] [blame] | 163 | val = readl(dev->regs); |
| 164 | if (!(val & MVMDIO_SMI_READ_VALID)) { |
| 165 | dev_err(bus->parent, "SMI bus read not valid\n"); |
Antoine Ténart | 0268b51 | 2017-06-15 16:43:24 +0200 | [diff] [blame^] | 166 | return -ENODEV; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 167 | } |
| 168 | |
Antoine Ténart | 0268b51 | 2017-06-15 16:43:24 +0200 | [diff] [blame^] | 169 | return val & GENMASK(15, 0); |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 170 | } |
| 171 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 172 | static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id, |
| 173 | int regnum, u16 value) |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 174 | { |
| 175 | struct orion_mdio_dev *dev = bus->priv; |
| 176 | int ret; |
| 177 | |
Antoine Ténart | 440ea77 | 2017-06-15 16:43:22 +0200 | [diff] [blame] | 178 | if (regnum & MII_ADDR_C45) |
| 179 | return -EOPNOTSUPP; |
| 180 | |
Antoine Ténart | b0b7fa4 | 2017-06-15 16:43:20 +0200 | [diff] [blame] | 181 | ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus); |
Leigh Brown | 526edcf | 2013-10-29 09:33:33 +0000 | [diff] [blame] | 182 | if (ret < 0) |
Antoine Ténart | 0268b51 | 2017-06-15 16:43:24 +0200 | [diff] [blame^] | 183 | return ret; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 184 | |
| 185 | writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) | |
| 186 | (regnum << MVMDIO_SMI_PHY_REG_SHIFT) | |
| 187 | MVMDIO_SMI_WRITE_OPERATION | |
| 188 | (value << MVMDIO_SMI_DATA_SHIFT)), |
Florian Fainelli | 3712b71 | 2013-03-22 03:39:26 +0000 | [diff] [blame] | 189 | dev->regs); |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 190 | |
Antoine Ténart | 0268b51 | 2017-06-15 16:43:24 +0200 | [diff] [blame^] | 191 | return 0; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 192 | } |
| 193 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 194 | static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev) |
| 195 | { |
| 196 | return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY); |
| 197 | } |
| 198 | |
| 199 | static const struct orion_mdio_ops orion_mdio_xsmi_ops = { |
| 200 | .is_done = orion_mdio_xsmi_is_done, |
| 201 | .poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN, |
| 202 | .poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX, |
| 203 | }; |
| 204 | |
| 205 | static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id, |
| 206 | int regnum) |
| 207 | { |
| 208 | struct orion_mdio_dev *dev = bus->priv; |
| 209 | u16 dev_addr = (regnum >> 16) & GENMASK(4, 0); |
| 210 | int ret; |
| 211 | |
| 212 | if (!(regnum & MII_ADDR_C45)) |
| 213 | return -EOPNOTSUPP; |
| 214 | |
| 215 | ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus); |
| 216 | if (ret < 0) |
| 217 | return ret; |
| 218 | |
| 219 | writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG); |
| 220 | writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) | |
| 221 | (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) | |
| 222 | MVMDIO_XSMI_READ_OPERATION, |
| 223 | dev->regs + MVMDIO_XSMI_MGNT_REG); |
| 224 | |
| 225 | ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus); |
| 226 | if (ret < 0) |
| 227 | return ret; |
| 228 | |
| 229 | if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & |
| 230 | MVMDIO_XSMI_READ_VALID)) { |
| 231 | dev_err(bus->parent, "XSMI bus read not valid\n"); |
| 232 | return -ENODEV; |
| 233 | } |
| 234 | |
| 235 | return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0); |
| 236 | } |
| 237 | |
| 238 | static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id, |
| 239 | int regnum, u16 value) |
| 240 | { |
| 241 | struct orion_mdio_dev *dev = bus->priv; |
| 242 | u16 dev_addr = (regnum >> 16) & GENMASK(4, 0); |
| 243 | int ret; |
| 244 | |
| 245 | if (!(regnum & MII_ADDR_C45)) |
| 246 | return -EOPNOTSUPP; |
| 247 | |
| 248 | ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus); |
| 249 | if (ret < 0) |
| 250 | return ret; |
| 251 | |
| 252 | writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG); |
| 253 | writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) | |
| 254 | (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) | |
| 255 | MVMDIO_XSMI_WRITE_OPERATION | value, |
| 256 | dev->regs + MVMDIO_XSMI_MGNT_REG); |
| 257 | |
| 258 | return 0; |
| 259 | } |
| 260 | |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 261 | static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id) |
| 262 | { |
| 263 | struct orion_mdio_dev *dev = dev_id; |
| 264 | |
| 265 | if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) & |
| 266 | MVMDIO_ERR_INT_SMI_DONE) { |
| 267 | writel(~MVMDIO_ERR_INT_SMI_DONE, |
| 268 | dev->regs + MVMDIO_ERR_INT_CAUSE); |
| 269 | wake_up(&dev->smi_busy_wait); |
| 270 | return IRQ_HANDLED; |
| 271 | } |
| 272 | |
| 273 | return IRQ_NONE; |
| 274 | } |
| 275 | |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 276 | static int orion_mdio_probe(struct platform_device *pdev) |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 277 | { |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 278 | enum orion_mdio_bus_type type; |
Florian Fainelli | 7111b71 | 2013-03-22 03:39:25 +0000 | [diff] [blame] | 279 | struct resource *r; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 280 | struct mii_bus *bus; |
| 281 | struct orion_mdio_dev *dev; |
Russell King | 96cb434 | 2017-04-10 16:28:31 +0100 | [diff] [blame] | 282 | int i, ret; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 283 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 284 | type = (enum orion_mdio_bus_type)of_device_get_match_data(&pdev->dev); |
| 285 | |
Florian Fainelli | 7111b71 | 2013-03-22 03:39:25 +0000 | [diff] [blame] | 286 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 287 | if (!r) { |
| 288 | dev_err(&pdev->dev, "No SMI register address given\n"); |
| 289 | return -ENODEV; |
| 290 | } |
| 291 | |
Ezequiel Garcia | 56ecd2c | 2014-05-22 20:07:02 -0300 | [diff] [blame] | 292 | bus = devm_mdiobus_alloc_size(&pdev->dev, |
| 293 | sizeof(struct orion_mdio_dev)); |
| 294 | if (!bus) |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 295 | return -ENOMEM; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 296 | |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 297 | switch (type) { |
| 298 | case BUS_TYPE_SMI: |
| 299 | bus->read = orion_mdio_smi_read; |
| 300 | bus->write = orion_mdio_smi_write; |
| 301 | break; |
| 302 | case BUS_TYPE_XSMI: |
| 303 | bus->read = orion_mdio_xsmi_read; |
| 304 | bus->write = orion_mdio_xsmi_write; |
| 305 | break; |
| 306 | } |
| 307 | |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 308 | bus->name = "orion_mdio_bus"; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 309 | snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", |
| 310 | dev_name(&pdev->dev)); |
| 311 | bus->parent = &pdev->dev; |
| 312 | |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 313 | dev = bus->priv; |
Florian Fainelli | 3712b71 | 2013-03-22 03:39:26 +0000 | [diff] [blame] | 314 | dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r)); |
| 315 | if (!dev->regs) { |
Florian Fainelli | 7111b71 | 2013-03-22 03:39:25 +0000 | [diff] [blame] | 316 | dev_err(&pdev->dev, "Unable to remap SMI register\n"); |
Alexey Khoroshilov | f814bfd | 2016-10-01 00:56:37 +0300 | [diff] [blame] | 317 | return -ENODEV; |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 318 | } |
| 319 | |
| 320 | init_waitqueue_head(&dev->smi_busy_wait); |
| 321 | |
Russell King | 96cb434 | 2017-04-10 16:28:31 +0100 | [diff] [blame] | 322 | for (i = 0; i < ARRAY_SIZE(dev->clk); i++) { |
| 323 | dev->clk[i] = of_clk_get(pdev->dev.of_node, i); |
| 324 | if (IS_ERR(dev->clk[i])) |
| 325 | break; |
| 326 | clk_prepare_enable(dev->clk[i]); |
| 327 | } |
Sebastian Hesselbarth | 3d604da | 2013-04-07 01:09:47 +0000 | [diff] [blame] | 328 | |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 329 | dev->err_interrupt = platform_get_irq(pdev, 0); |
Russell King | a51e2c9 | 2017-04-10 16:28:20 +0100 | [diff] [blame] | 330 | if (dev->err_interrupt > 0 && |
| 331 | resource_size(r) < MVMDIO_ERR_INT_MASK + 4) { |
| 332 | dev_err(&pdev->dev, |
| 333 | "disabling interrupt, resource size is too small\n"); |
| 334 | dev->err_interrupt = 0; |
| 335 | } |
Ezequiel Garcia | 39076b0 | 2014-04-30 13:28:51 -0300 | [diff] [blame] | 336 | if (dev->err_interrupt > 0) { |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 337 | ret = devm_request_irq(&pdev->dev, dev->err_interrupt, |
| 338 | orion_mdio_err_irq, |
| 339 | IRQF_SHARED, pdev->name, dev); |
| 340 | if (ret) |
| 341 | goto out_mdio; |
| 342 | |
| 343 | writel(MVMDIO_ERR_INT_SMI_DONE, |
| 344 | dev->regs + MVMDIO_ERR_INT_MASK); |
Ezequiel Garcia | 39076b0 | 2014-04-30 13:28:51 -0300 | [diff] [blame] | 345 | |
| 346 | } else if (dev->err_interrupt == -EPROBE_DEFER) { |
| 347 | return -EPROBE_DEFER; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 348 | } |
| 349 | |
Florian Fainelli | 7111b71 | 2013-03-22 03:39:25 +0000 | [diff] [blame] | 350 | if (pdev->dev.of_node) |
| 351 | ret = of_mdiobus_register(bus, pdev->dev.of_node); |
| 352 | else |
| 353 | ret = mdiobus_register(bus); |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 354 | if (ret < 0) { |
| 355 | dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret); |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 356 | goto out_mdio; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 357 | } |
| 358 | |
| 359 | platform_set_drvdata(pdev, bus); |
| 360 | |
| 361 | return 0; |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 362 | |
| 363 | out_mdio: |
Russell King | 3728248 | 2017-04-10 16:28:04 +0100 | [diff] [blame] | 364 | if (dev->err_interrupt > 0) |
| 365 | writel(0, dev->regs + MVMDIO_ERR_INT_MASK); |
Russell King | 96cb434 | 2017-04-10 16:28:31 +0100 | [diff] [blame] | 366 | |
| 367 | for (i = 0; i < ARRAY_SIZE(dev->clk); i++) { |
| 368 | if (IS_ERR(dev->clk[i])) |
| 369 | break; |
| 370 | clk_disable_unprepare(dev->clk[i]); |
| 371 | clk_put(dev->clk[i]); |
| 372 | } |
| 373 | |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 374 | return ret; |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 375 | } |
| 376 | |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 377 | static int orion_mdio_remove(struct platform_device *pdev) |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 378 | { |
| 379 | struct mii_bus *bus = platform_get_drvdata(pdev); |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 380 | struct orion_mdio_dev *dev = bus->priv; |
Russell King | 96cb434 | 2017-04-10 16:28:31 +0100 | [diff] [blame] | 381 | int i; |
Florian Fainelli | 2ec9852 | 2013-03-22 03:39:27 +0000 | [diff] [blame] | 382 | |
Russell King | 7093a97 | 2017-04-10 16:28:09 +0100 | [diff] [blame] | 383 | if (dev->err_interrupt > 0) |
| 384 | writel(0, dev->regs + MVMDIO_ERR_INT_MASK); |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 385 | mdiobus_unregister(bus); |
Russell King | 96cb434 | 2017-04-10 16:28:31 +0100 | [diff] [blame] | 386 | |
| 387 | for (i = 0; i < ARRAY_SIZE(dev->clk); i++) { |
| 388 | if (IS_ERR(dev->clk[i])) |
| 389 | break; |
| 390 | clk_disable_unprepare(dev->clk[i]); |
| 391 | clk_put(dev->clk[i]); |
| 392 | } |
Sebastian Hesselbarth | 3d604da | 2013-04-07 01:09:47 +0000 | [diff] [blame] | 393 | |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 394 | return 0; |
| 395 | } |
| 396 | |
| 397 | static const struct of_device_id orion_mdio_match[] = { |
Antoine Ténart | c0ac08f | 2017-06-15 16:43:23 +0200 | [diff] [blame] | 398 | { .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI }, |
| 399 | { .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI }, |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 400 | { } |
| 401 | }; |
| 402 | MODULE_DEVICE_TABLE(of, orion_mdio_match); |
| 403 | |
| 404 | static struct platform_driver orion_mdio_driver = { |
| 405 | .probe = orion_mdio_probe, |
Greg KH | 03ce758 | 2012-12-21 13:42:15 +0000 | [diff] [blame] | 406 | .remove = orion_mdio_remove, |
Thomas Petazzoni | fc8f5ad | 2012-11-12 17:03:47 +0100 | [diff] [blame] | 407 | .driver = { |
| 408 | .name = "orion-mdio", |
| 409 | .of_match_table = orion_mdio_match, |
| 410 | }, |
| 411 | }; |
| 412 | |
| 413 | module_platform_driver(orion_mdio_driver); |
| 414 | |
| 415 | MODULE_DESCRIPTION("Marvell MDIO interface driver"); |
| 416 | MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); |
| 417 | MODULE_LICENSE("GPL"); |
Simon Baatz | 404b8be | 2013-03-24 10:33:59 +0000 | [diff] [blame] | 418 | MODULE_ALIAS("platform:orion-mdio"); |