blob: c9798210fa0f6cef39aec36ed5c64fe6e805d7dc [file] [log] [blame]
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +01001/*
2 * Driver for the MDIO interface of Marvell network interfaces.
3 *
4 * Since the MDIO interface of Marvell network interfaces is shared
5 * between all network interfaces, having a single driver allows to
6 * handle concurrent accesses properly (you may have four Ethernet
Leigh Brownd4a0acb2013-10-29 09:33:34 +00007 * ports, but they in fact share the same SMI interface to access
8 * the MDIO bus). This driver is currently used by the mvneta and
9 * mv643xx_eth drivers.
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010010 *
11 * Copyright (C) 2012 Marvell
12 *
13 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 *
15 * This file is licensed under the terms of the GNU General Public
16 * License version 2. This program is licensed "as is" without any
17 * warranty of any kind, whether express or implied.
18 */
19
Antoine Ténart14ef8b32017-06-15 16:43:16 +020020#include <linux/clk.h>
21#include <linux/delay.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010024#include <linux/kernel.h>
25#include <linux/module.h>
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020026#include <linux/of_device.h>
Florian Fainelli7111b712013-03-22 03:39:25 +000027#include <linux/of_mdio.h>
Antoine Ténart14ef8b32017-06-15 16:43:16 +020028#include <linux/phy.h>
29#include <linux/platform_device.h>
Florian Fainelli2ec98522013-03-22 03:39:27 +000030#include <linux/sched.h>
31#include <linux/wait.h>
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010032
Antoine Ténart2040ef22017-06-15 16:43:17 +020033#define MVMDIO_SMI_DATA_SHIFT 0
34#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
35#define MVMDIO_SMI_PHY_REG_SHIFT 21
36#define MVMDIO_SMI_READ_OPERATION BIT(26)
37#define MVMDIO_SMI_WRITE_OPERATION 0
38#define MVMDIO_SMI_READ_VALID BIT(27)
39#define MVMDIO_SMI_BUSY BIT(28)
40#define MVMDIO_ERR_INT_CAUSE 0x007C
41#define MVMDIO_ERR_INT_SMI_DONE 0x00000010
42#define MVMDIO_ERR_INT_MASK 0x0080
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010043
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020044#define MVMDIO_XSMI_MGNT_REG 0x0
45#define MVMDIO_XSMI_PHYADDR_SHIFT 16
46#define MVMDIO_XSMI_DEVADDR_SHIFT 21
47#define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
48#define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
49#define MVMDIO_XSMI_READ_VALID BIT(29)
50#define MVMDIO_XSMI_BUSY BIT(30)
51#define MVMDIO_XSMI_ADDR_REG 0x8
52
Leigh Brownb70cd1c2013-10-29 09:33:31 +000053/*
54 * SMI Timeout measurements:
55 * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
56 * - Armada 370 (Globalscale Mirabox): 41us to 43us (Polled)
57 */
Antoine Ténart2040ef22017-06-15 16:43:17 +020058#define MVMDIO_SMI_TIMEOUT 1000 /* 1000us = 1ms */
59#define MVMDIO_SMI_POLL_INTERVAL_MIN 45
60#define MVMDIO_SMI_POLL_INTERVAL_MAX 55
Leigh Brownb70cd1c2013-10-29 09:33:31 +000061
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020062#define MVMDIO_XSMI_POLL_INTERVAL_MIN 150
63#define MVMDIO_XSMI_POLL_INTERVAL_MAX 160
64
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010065struct orion_mdio_dev {
Florian Fainelli3712b712013-03-22 03:39:26 +000066 void __iomem *regs;
Russell King96cb4342017-04-10 16:28:31 +010067 struct clk *clk[3];
Florian Fainelli2ec98522013-03-22 03:39:27 +000068 /*
69 * If we have access to the error interrupt pin (which is
70 * somewhat misnamed as it not only reflects internal errors
71 * but also reflects SMI completion), use that to wait for
72 * SMI access completion instead of polling the SMI busy bit.
73 */
74 int err_interrupt;
75 wait_queue_head_t smi_busy_wait;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010076};
77
Antoine Ténartc0ac08f2017-06-15 16:43:23 +020078enum orion_mdio_bus_type {
79 BUS_TYPE_SMI,
80 BUS_TYPE_XSMI
81};
82
Antoine Ténartb0b7fa42017-06-15 16:43:20 +020083struct orion_mdio_ops {
84 int (*is_done)(struct orion_mdio_dev *);
Antoine Ténart19557962017-06-15 16:43:21 +020085 unsigned int poll_interval_min;
86 unsigned int poll_interval_max;
Antoine Ténartb0b7fa42017-06-15 16:43:20 +020087};
Florian Fainelli2ec98522013-03-22 03:39:27 +000088
Thomas Petazzonib07812f2012-11-19 11:40:15 +010089/* Wait for the SMI unit to be ready for another operation
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010090 */
Antoine Ténartb0b7fa42017-06-15 16:43:20 +020091static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,
92 struct mii_bus *bus)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010093{
94 struct orion_mdio_dev *dev = bus->priv;
Leigh Brownb70cd1c2013-10-29 09:33:31 +000095 unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT);
96 unsigned long end = jiffies + timeout;
97 int timedout = 0;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +010098
Leigh Brownb70cd1c2013-10-29 09:33:31 +000099 while (1) {
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200100 if (ops->is_done(dev))
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000101 return 0;
102 else if (timedout)
103 break;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100104
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000105 if (dev->err_interrupt <= 0) {
Antoine Ténart19557962017-06-15 16:43:21 +0200106 usleep_range(ops->poll_interval_min,
107 ops->poll_interval_max);
Florian Fainelli2ec98522013-03-22 03:39:27 +0000108
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000109 if (time_is_before_jiffies(end))
110 ++timedout;
111 } else {
Leigh Brown1a1f20b2013-12-19 13:09:48 +0000112 /* wait_event_timeout does not guarantee a delay of at
113 * least one whole jiffie, so timeout must be no less
114 * than two.
115 */
116 if (timeout < 2)
117 timeout = 2;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000118 wait_event_timeout(dev->smi_busy_wait,
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200119 ops->is_done(dev), timeout);
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000120
121 ++timedout;
122 }
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100123 }
124
Leigh Brownb70cd1c2013-10-29 09:33:31 +0000125 dev_err(bus->parent, "Timeout: SMI busy for too long\n");
126 return -ETIMEDOUT;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100127}
128
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200129static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
130{
131 return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
132}
133
134static const struct orion_mdio_ops orion_mdio_smi_ops = {
135 .is_done = orion_mdio_smi_is_done,
Antoine Ténart19557962017-06-15 16:43:21 +0200136 .poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN,
137 .poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX,
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200138};
139
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200140static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
141 int regnum)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100142{
143 struct orion_mdio_dev *dev = bus->priv;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100144 u32 val;
145 int ret;
146
Antoine Ténart440ea772017-06-15 16:43:22 +0200147 if (regnum & MII_ADDR_C45)
148 return -EOPNOTSUPP;
149
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200150 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
Leigh Brown839f46b2013-10-29 09:33:32 +0000151 if (ret < 0)
Antoine Ténart0268b512017-06-15 16:43:24 +0200152 return ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100153
154 writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
155 (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
156 MVMDIO_SMI_READ_OPERATION),
Florian Fainelli3712b712013-03-22 03:39:26 +0000157 dev->regs);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100158
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200159 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
Leigh Brown839f46b2013-10-29 09:33:32 +0000160 if (ret < 0)
Antoine Ténart0268b512017-06-15 16:43:24 +0200161 return ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100162
Leigh Brown839f46b2013-10-29 09:33:32 +0000163 val = readl(dev->regs);
164 if (!(val & MVMDIO_SMI_READ_VALID)) {
165 dev_err(bus->parent, "SMI bus read not valid\n");
Antoine Ténart0268b512017-06-15 16:43:24 +0200166 return -ENODEV;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100167 }
168
Antoine Ténart0268b512017-06-15 16:43:24 +0200169 return val & GENMASK(15, 0);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100170}
171
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200172static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
173 int regnum, u16 value)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100174{
175 struct orion_mdio_dev *dev = bus->priv;
176 int ret;
177
Antoine Ténart440ea772017-06-15 16:43:22 +0200178 if (regnum & MII_ADDR_C45)
179 return -EOPNOTSUPP;
180
Antoine Ténartb0b7fa42017-06-15 16:43:20 +0200181 ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
Leigh Brown526edcf2013-10-29 09:33:33 +0000182 if (ret < 0)
Antoine Ténart0268b512017-06-15 16:43:24 +0200183 return ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100184
185 writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
186 (regnum << MVMDIO_SMI_PHY_REG_SHIFT) |
187 MVMDIO_SMI_WRITE_OPERATION |
188 (value << MVMDIO_SMI_DATA_SHIFT)),
Florian Fainelli3712b712013-03-22 03:39:26 +0000189 dev->regs);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100190
Antoine Ténart0268b512017-06-15 16:43:24 +0200191 return 0;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100192}
193
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200194static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)
195{
196 return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY);
197}
198
199static const struct orion_mdio_ops orion_mdio_xsmi_ops = {
200 .is_done = orion_mdio_xsmi_is_done,
201 .poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN,
202 .poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX,
203};
204
205static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id,
206 int regnum)
207{
208 struct orion_mdio_dev *dev = bus->priv;
209 u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
210 int ret;
211
212 if (!(regnum & MII_ADDR_C45))
213 return -EOPNOTSUPP;
214
215 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
216 if (ret < 0)
217 return ret;
218
219 writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
220 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
221 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
222 MVMDIO_XSMI_READ_OPERATION,
223 dev->regs + MVMDIO_XSMI_MGNT_REG);
224
225 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
226 if (ret < 0)
227 return ret;
228
229 if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) &
230 MVMDIO_XSMI_READ_VALID)) {
231 dev_err(bus->parent, "XSMI bus read not valid\n");
232 return -ENODEV;
233 }
234
235 return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
236}
237
238static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id,
239 int regnum, u16 value)
240{
241 struct orion_mdio_dev *dev = bus->priv;
242 u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
243 int ret;
244
245 if (!(regnum & MII_ADDR_C45))
246 return -EOPNOTSUPP;
247
248 ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
249 if (ret < 0)
250 return ret;
251
252 writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
253 writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
254 (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
255 MVMDIO_XSMI_WRITE_OPERATION | value,
256 dev->regs + MVMDIO_XSMI_MGNT_REG);
257
258 return 0;
259}
260
Florian Fainelli2ec98522013-03-22 03:39:27 +0000261static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
262{
263 struct orion_mdio_dev *dev = dev_id;
264
265 if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
266 MVMDIO_ERR_INT_SMI_DONE) {
267 writel(~MVMDIO_ERR_INT_SMI_DONE,
268 dev->regs + MVMDIO_ERR_INT_CAUSE);
269 wake_up(&dev->smi_busy_wait);
270 return IRQ_HANDLED;
271 }
272
273 return IRQ_NONE;
274}
275
Greg KH03ce7582012-12-21 13:42:15 +0000276static int orion_mdio_probe(struct platform_device *pdev)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100277{
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200278 enum orion_mdio_bus_type type;
Florian Fainelli7111b712013-03-22 03:39:25 +0000279 struct resource *r;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100280 struct mii_bus *bus;
281 struct orion_mdio_dev *dev;
Russell King96cb4342017-04-10 16:28:31 +0100282 int i, ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100283
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200284 type = (enum orion_mdio_bus_type)of_device_get_match_data(&pdev->dev);
285
Florian Fainelli7111b712013-03-22 03:39:25 +0000286 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
287 if (!r) {
288 dev_err(&pdev->dev, "No SMI register address given\n");
289 return -ENODEV;
290 }
291
Ezequiel Garcia56ecd2c2014-05-22 20:07:02 -0300292 bus = devm_mdiobus_alloc_size(&pdev->dev,
293 sizeof(struct orion_mdio_dev));
294 if (!bus)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100295 return -ENOMEM;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100296
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200297 switch (type) {
298 case BUS_TYPE_SMI:
299 bus->read = orion_mdio_smi_read;
300 bus->write = orion_mdio_smi_write;
301 break;
302 case BUS_TYPE_XSMI:
303 bus->read = orion_mdio_xsmi_read;
304 bus->write = orion_mdio_xsmi_write;
305 break;
306 }
307
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100308 bus->name = "orion_mdio_bus";
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100309 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
310 dev_name(&pdev->dev));
311 bus->parent = &pdev->dev;
312
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100313 dev = bus->priv;
Florian Fainelli3712b712013-03-22 03:39:26 +0000314 dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
315 if (!dev->regs) {
Florian Fainelli7111b712013-03-22 03:39:25 +0000316 dev_err(&pdev->dev, "Unable to remap SMI register\n");
Alexey Khoroshilovf814bfd2016-10-01 00:56:37 +0300317 return -ENODEV;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000318 }
319
320 init_waitqueue_head(&dev->smi_busy_wait);
321
Russell King96cb4342017-04-10 16:28:31 +0100322 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
323 dev->clk[i] = of_clk_get(pdev->dev.of_node, i);
324 if (IS_ERR(dev->clk[i]))
325 break;
326 clk_prepare_enable(dev->clk[i]);
327 }
Sebastian Hesselbarth3d604da2013-04-07 01:09:47 +0000328
Florian Fainelli2ec98522013-03-22 03:39:27 +0000329 dev->err_interrupt = platform_get_irq(pdev, 0);
Russell Kinga51e2c92017-04-10 16:28:20 +0100330 if (dev->err_interrupt > 0 &&
331 resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
332 dev_err(&pdev->dev,
333 "disabling interrupt, resource size is too small\n");
334 dev->err_interrupt = 0;
335 }
Ezequiel Garcia39076b02014-04-30 13:28:51 -0300336 if (dev->err_interrupt > 0) {
Florian Fainelli2ec98522013-03-22 03:39:27 +0000337 ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
338 orion_mdio_err_irq,
339 IRQF_SHARED, pdev->name, dev);
340 if (ret)
341 goto out_mdio;
342
343 writel(MVMDIO_ERR_INT_SMI_DONE,
344 dev->regs + MVMDIO_ERR_INT_MASK);
Ezequiel Garcia39076b02014-04-30 13:28:51 -0300345
346 } else if (dev->err_interrupt == -EPROBE_DEFER) {
347 return -EPROBE_DEFER;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100348 }
349
Florian Fainelli7111b712013-03-22 03:39:25 +0000350 if (pdev->dev.of_node)
351 ret = of_mdiobus_register(bus, pdev->dev.of_node);
352 else
353 ret = mdiobus_register(bus);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100354 if (ret < 0) {
355 dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
Florian Fainelli2ec98522013-03-22 03:39:27 +0000356 goto out_mdio;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100357 }
358
359 platform_set_drvdata(pdev, bus);
360
361 return 0;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000362
363out_mdio:
Russell King37282482017-04-10 16:28:04 +0100364 if (dev->err_interrupt > 0)
365 writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
Russell King96cb4342017-04-10 16:28:31 +0100366
367 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
368 if (IS_ERR(dev->clk[i]))
369 break;
370 clk_disable_unprepare(dev->clk[i]);
371 clk_put(dev->clk[i]);
372 }
373
Florian Fainelli2ec98522013-03-22 03:39:27 +0000374 return ret;
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100375}
376
Greg KH03ce7582012-12-21 13:42:15 +0000377static int orion_mdio_remove(struct platform_device *pdev)
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100378{
379 struct mii_bus *bus = platform_get_drvdata(pdev);
Florian Fainelli2ec98522013-03-22 03:39:27 +0000380 struct orion_mdio_dev *dev = bus->priv;
Russell King96cb4342017-04-10 16:28:31 +0100381 int i;
Florian Fainelli2ec98522013-03-22 03:39:27 +0000382
Russell King7093a972017-04-10 16:28:09 +0100383 if (dev->err_interrupt > 0)
384 writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100385 mdiobus_unregister(bus);
Russell King96cb4342017-04-10 16:28:31 +0100386
387 for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
388 if (IS_ERR(dev->clk[i]))
389 break;
390 clk_disable_unprepare(dev->clk[i]);
391 clk_put(dev->clk[i]);
392 }
Sebastian Hesselbarth3d604da2013-04-07 01:09:47 +0000393
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100394 return 0;
395}
396
397static const struct of_device_id orion_mdio_match[] = {
Antoine Ténartc0ac08f2017-06-15 16:43:23 +0200398 { .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI },
399 { .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI },
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100400 { }
401};
402MODULE_DEVICE_TABLE(of, orion_mdio_match);
403
404static struct platform_driver orion_mdio_driver = {
405 .probe = orion_mdio_probe,
Greg KH03ce7582012-12-21 13:42:15 +0000406 .remove = orion_mdio_remove,
Thomas Petazzonifc8f5ad2012-11-12 17:03:47 +0100407 .driver = {
408 .name = "orion-mdio",
409 .of_match_table = orion_mdio_match,
410 },
411};
412
413module_platform_driver(orion_mdio_driver);
414
415MODULE_DESCRIPTION("Marvell MDIO interface driver");
416MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
417MODULE_LICENSE("GPL");
Simon Baatz404b8be2013-03-24 10:33:59 +0000418MODULE_ALIAS("platform:orion-mdio");