arch/arm/boot/dts/bcm-hr2.dtsi - SHIFTPHONES/mainline/linux - Gitiles

 /*
  *  BSD LICENSE
  *
  *  Copyright(c) 2017 Broadcom.  All rights reserved.
  *
  *  Redistribution and use in source and binary forms, with or without
  *  modification, are permitted provided that the following conditions
  *  are met:
  *
  *    * Redistributions of source code must retain the above copyright
  *      notice, this list of conditions and the following disclaimer.
  *    * Redistributions in binary form must reproduce the above copyright
  *      notice, this list of conditions and the following disclaimer in
  *      the documentation and/or other materials provided with the
  *      distribution.
  *    * Neither the name of Broadcom Corporation nor the names of its
  *      contributors may be used to endorse or promote products derived
  *      from this software without specific prior written permission.
  *
  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>

 / {
 	compatible = "brcm,hr2";
 	model = "Broadcom Hurricane 2 SoC";
 	interrupt-parent = <&gic>;
 	#address-cells = <1>;
 	#size-cells = <1>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			next-level-cache = <&L2>;
 			reg = <0x0>;
 		};
 	};

 	pmu {
 		compatible = "arm,cortex-a9-pmu";
 		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
 			      GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-affinity = <&cpu0>;
 	};

 	mpcore@19000000 {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x19000000 0x00023000>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		a9pll: arm_clk@0 {
 			#clock-cells = <0>;
 			compatible = "brcm,hr2-armpll";
 			clocks = <&osc>;
 			reg = <0x0 0x1000>;
 		};

 		timer@20200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x20200 0x100>;
 			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&periph_clk>;
 		};

 		twd-timer@20600 {
 			compatible = "arm,cortex-a9-twd-timer";
 			reg = <0x20600 0x20>;
 			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
 						  IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&periph_clk>;
 		};

 		twd-watchdog@20620 {
 			compatible = "arm,cortex-a9-twd-wdt";
 			reg = <0x20620 0x20>;
 			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
 						  IRQ_TYPE_LEVEL_HIGH)>;
 			clocks = <&periph_clk>;
 		};

 		gic: interrupt-controller@21000 {
 			compatible = "arm,cortex-a9-gic";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
 			reg = <0x21000 0x1000>,
 			      <0x20100 0x100>;
 		};

 		L2: l2-cache@22000 {
 			compatible = "arm,pl310-cache";
 			reg = <0x22000 0x1000>;
 			cache-unified;
 			cache-level = <2>;
 		};
 	};

 	clocks {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;

 		osc: oscillator {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
 			clock-frequency = <25000000>;
 		};

 		periph_clk: periph_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-factor-clock";
 			clocks = <&a9pll>;
 			clock-div = <2>;
 			clock-mult = <1>;
 		};
 	};

 	axi@18000000 {
 		compatible = "simple-bus";
 		ranges = <0x00000000 0x18000000 0x0011c40c>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		uart0: serial@300 {
 			compatible = "ns16550a";
 			reg = <0x0300 0x100>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&osc>;
 			status = "disabled";
 		};

 		uart1: serial@400 {
 			compatible = "ns16550a";
 			reg = <0x0400 0x100>;
 			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&osc>;
 			status = "disabled";
 		};

 		dma@20000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x20000 0x1000>;
 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 			#dma-cells = <1>;
 			status = "disabled";
 		};

 		amac0: ethernet@22000 {
 			compatible = "brcm,nsp-amac";
 			reg = <0x22000 0x1000>,
 			      <0x110000 0x1000>;
 			reg-names = "amac_base", "idm_base";
 			interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
 			status = "disabled";
 		};

 		nand: nand@26000 {
 			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 			reg = <0x26000 0x600>,
 			      <0x11b408 0x600>,
 			      <0x026f00 0x20>;
 			reg-names = "nand", "iproc-idm", "iproc-ext";
 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

 			#address-cells = <1>;
 			#size-cells = <0>;

 			brcm,nand-has-wp;
 		};

 		gpiob: gpio@30000 {
 			compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
 			reg = <0x30000 0x50>;
 			#gpio-cells = <2>;
 			gpio-controller;
 			ngpios = <4>;
 			interrupt-controller;
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		pwm: pwm@31000 {
 			compatible = "brcm,iproc-pwm";
 			reg = <0x31000 0x28>;
 			clocks = <&osc>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};

 		rng: rng@33000 {
 			compatible = "brcm,bcm-nsp-rng";
 			reg = <0x33000 0x14>;
 		};

 		qspi: qspi@27200 {
 			compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
 			reg = <0x027200 0x184>,
 			      <0x027000 0x124>,
 			      <0x11c408 0x004>,
 			      <0x0273a0 0x01c>;
 			reg-names = "mspi", "bspi", "intr_regs",
 				    "intr_status_reg";
 			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "spi_lr_fullness_reached",
 					  "spi_lr_session_aborted",
 					  "spi_lr_impatient",
 					  "spi_lr_session_done",
 					  "spi_lr_overhead",
 					  "mspi_done",
 					  "mspi_halted";
 			num-cs = <2>;
 			#address-cells = <1>;
 			#size-cells = <0>;

 			/* partitions defined in board DTS */
 		};

 		ccbtimer0: timer@34000 {
 			compatible = "arm,sp804";
 			reg = <0x34000 0x1000>;
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		ccbtimer1: timer@35000 {
 			compatible = "arm,sp804";
 			reg = <0x35000 0x1000>;
 			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		i2c0: i2c@38000 {
 			compatible = "brcm,iproc-i2c";
 			reg = <0x38000 0x50>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 95 IRQ_TYPE_NONE>;
 			clock-frequency = <100000>;
 		};

 		watchdog@39000 {
 			compatible = "arm,sp805", "arm,primecell";
 			reg = <0x39000 0x1000>;
 			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
 		};

 		i2c1: i2c@3b000 {
 			compatible = "brcm,iproc-i2c";
 			reg = <0x3b000 0x50>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>;
 			clock-frequency = <100000>;
 		};
 	};

 	pflash: nor@20000000 {
 		compatible = "cfi-flash", "jedec-flash";
 		reg = <0x20000000 0x04000000>;
 		status = "disabled";
 		#address-cells = <1>;
 		#size-cells = <1>;

 		/* partitions defined in board DTS */
 	};

 	pcie0: pcie@18012000 {
 		compatible = "brcm,iproc-pcie";
 		reg = <0x18012000 0x1000>;

 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0>;
 		interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_NONE>;

 		linux,pci-domain = <0>;

 		bus-range = <0x00 0xff>;

 		#address-cells = <3>;
 		#size-cells = <2>;
 		device_type = "pci";

 		/* Note: The HW does not support I/O resources.  So,
 		 * only the memory resource range is being specified.
 		 */
 		ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;

 		status = "disabled";

 		msi-parent = <&msi0>;
 		msi0: msi-controller {
 			compatible = "brcm,iproc-msi";
 			msi-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 182 IRQ_TYPE_NONE>,
 				     <GIC_SPI 183 IRQ_TYPE_NONE>,
 				     <GIC_SPI 184 IRQ_TYPE_NONE>,
 				     <GIC_SPI 185 IRQ_TYPE_NONE>;
 			brcm,pcie-msi-inten;
 		};
 	};

 	pcie1: pcie@18013000 {
 		compatible = "brcm,iproc-pcie";
 		reg = <0x18013000 0x1000>;

 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 0>;
 		interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_NONE>;

 		linux,pci-domain = <1>;

 		bus-range = <0x00 0xff>;

 		#address-cells = <3>;
 		#size-cells = <2>;
 		device_type = "pci";

 		/* Note: The HW does not support I/O resources.  So,
 		 * only the memory resource range is being specified.
 		 */
 		ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;

 		status = "disabled";

 		msi-parent = <&msi1>;
 		msi1: msi-controller {
 			compatible = "brcm,iproc-msi";
 			msi-controller;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>,
 				     <GIC_SPI 189 IRQ_TYPE_NONE>,
 				     <GIC_SPI 190 IRQ_TYPE_NONE>,
 				     <GIC_SPI 191 IRQ_TYPE_NONE>;
 			brcm,pcie-msi-inten;
 		};
 	};
 };
	/*
	* BSD LICENSE
	*
	* Copyright(c) 2017 Broadcom. All rights reserved.
	*
	* Redistribution and use in source and binary forms, with or without
	* modification, are permitted provided that the following conditions
	* are met:
	*
	* * Redistributions of source code must retain the above copyright
	* notice, this list of conditions and the following disclaimer.
	* * Redistributions in binary form must reproduce the above copyright
	* notice, this list of conditions and the following disclaimer in
	* the documentation and/or other materials provided with the
	* distribution.
	* * Neither the name of Broadcom Corporation nor the names of its
	* contributors may be used to endorse or promote products derived
	* from this software without specific prior written permission.
	*
	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/interrupt-controller/irq.h>

	/ {
	compatible = "brcm,hr2";
	model = "Broadcom Hurricane 2 SoC";
	interrupt-parent = <&gic>;
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a9";
	next-level-cache = <&L2>;
	reg = <0x0>;
	};
	};

	pmu {
	compatible = "arm,cortex-a9-pmu";
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
	GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-affinity = <&cpu0>;
	};

	mpcore@19000000 {
	compatible = "simple-bus";
	ranges = <0x00000000 0x19000000 0x00023000>;
	#address-cells = <1>;
	#size-cells = <1>;

	a9pll: arm_clk@0 {
	#clock-cells = <0>;
	compatible = "brcm,hr2-armpll";
	clocks = <&osc>;
	reg = <0x0 0x1000>;
	};

	timer@20200 {
	compatible = "arm,cortex-a9-global-timer";
	reg = <0x20200 0x100>;
	interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&periph_clk>;
	};

	twd-timer@20600 {
	compatible = "arm,cortex-a9-twd-timer";
	reg = <0x20600 0x20>;
	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&periph_clk>;
	};

	twd-watchdog@20620 {
	compatible = "arm,cortex-a9-twd-wdt";
	reg = <0x20620 0x20>;
	interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) \|
	IRQ_TYPE_LEVEL_HIGH)>;
	clocks = <&periph_clk>;
	};

	gic: interrupt-controller@21000 {
	compatible = "arm,cortex-a9-gic";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x21000 0x1000>,
	<0x20100 0x100>;
	};

	L2: l2-cache@22000 {
	compatible = "arm,pl310-cache";
	reg = <0x22000 0x1000>;
	cache-unified;
	cache-level = <2>;
	};
	};

	clocks {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	osc: oscillator {
	#clock-cells = <0>;
	compatible = "fixed-clock";
	clock-frequency = <25000000>;
	};

	periph_clk: periph_clk {
	#clock-cells = <0>;
	compatible = "fixed-factor-clock";
	clocks = <&a9pll>;
	clock-div = <2>;
	clock-mult = <1>;
	};
	};

	axi@18000000 {
	compatible = "simple-bus";
	ranges = <0x00000000 0x18000000 0x0011c40c>;
	#address-cells = <1>;
	#size-cells = <1>;

	uart0: serial@300 {
	compatible = "ns16550a";
	reg = <0x0300 0x100>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc>;
	status = "disabled";
	};

	uart1: serial@400 {
	compatible = "ns16550a";
	reg = <0x0400 0x100>;
	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&osc>;
	status = "disabled";
	};

	dma@20000 {
	compatible = "arm,pl330", "arm,primecell";
	reg = <0x20000 0x1000>;
	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	#dma-cells = <1>;
	status = "disabled";
	};

	amac0: ethernet@22000 {
	compatible = "brcm,nsp-amac";
	reg = <0x22000 0x1000>,
	<0x110000 0x1000>;
	reg-names = "amac_base", "idm_base";
	interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
	status = "disabled";
	};

	nand: nand@26000 {
	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	reg = <0x26000 0x600>,
	<0x11b408 0x600>,
	<0x026f00 0x20>;
	reg-names = "nand", "iproc-idm", "iproc-ext";
	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;

	#address-cells = <1>;
	#size-cells = <0>;

	brcm,nand-has-wp;
	};

	gpiob: gpio@30000 {
	compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
	reg = <0x30000 0x50>;
	#gpio-cells = <2>;
	gpio-controller;
	ngpios = <4>;
	interrupt-controller;
	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	};

	pwm: pwm@31000 {
	compatible = "brcm,iproc-pwm";
	reg = <0x31000 0x28>;
	clocks = <&osc>;
	#pwm-cells = <3>;
	status = "disabled";
	};

	rng: rng@33000 {
	compatible = "brcm,bcm-nsp-rng";
	reg = <0x33000 0x14>;
	};

	qspi: qspi@27200 {
	compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
	reg = <0x027200 0x184>,
	<0x027000 0x124>,
	<0x11c408 0x004>,
	<0x0273a0 0x01c>;
	reg-names = "mspi", "bspi", "intr_regs",
	"intr_status_reg";
	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "spi_lr_fullness_reached",
	"spi_lr_session_aborted",
	"spi_lr_impatient",
	"spi_lr_session_done",
	"spi_lr_overhead",
	"mspi_done",
	"mspi_halted";
	num-cs = <2>;
	#address-cells = <1>;
	#size-cells = <0>;

	/* partitions defined in board DTS */
	};

	ccbtimer0: timer@34000 {
	compatible = "arm,sp804";
	reg = <0x34000 0x1000>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
	};

	ccbtimer1: timer@35000 {
	compatible = "arm,sp804";
	reg = <0x35000 0x1000>;
	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c0: i2c@38000 {
	compatible = "brcm,iproc-i2c";
	reg = <0x38000 0x50>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_NONE>;
	clock-frequency = <100000>;
	};

	watchdog@39000 {
	compatible = "arm,sp805", "arm,primecell";
	reg = <0x39000 0x1000>;
	interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c1: i2c@3b000 {
	compatible = "brcm,iproc-i2c";
	reg = <0x3b000 0x50>;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>;
	clock-frequency = <100000>;
	};
	};

	pflash: nor@20000000 {
	compatible = "cfi-flash", "jedec-flash";
	reg = <0x20000000 0x04000000>;
	status = "disabled";
	#address-cells = <1>;
	#size-cells = <1>;

	/* partitions defined in board DTS */
	};

	pcie0: pcie@18012000 {
	compatible = "brcm,iproc-pcie";
	reg = <0x18012000 0x1000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_NONE>;

	linux,pci-domain = <0>;

	bus-range = <0x00 0xff>;

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";

	/* Note: The HW does not support I/O resources. So,
	* only the memory resource range is being specified.
	*/
	ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;

	status = "disabled";

	msi-parent = <&msi0>;
	msi0: msi-controller {
	compatible = "brcm,iproc-msi";
	msi-controller;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 182 IRQ_TYPE_NONE>,
	<GIC_SPI 183 IRQ_TYPE_NONE>,
	<GIC_SPI 184 IRQ_TYPE_NONE>,
	<GIC_SPI 185 IRQ_TYPE_NONE>;
	brcm,pcie-msi-inten;
	};
	};

	pcie1: pcie@18013000 {
	compatible = "brcm,iproc-pcie";
	reg = <0x18013000 0x1000>;

	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0>;
	interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_NONE>;

	linux,pci-domain = <1>;

	bus-range = <0x00 0xff>;

	#address-cells = <3>;
	#size-cells = <2>;
	device_type = "pci";

	/* Note: The HW does not support I/O resources. So,
	* only the memory resource range is being specified.
	*/
	ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;

	status = "disabled";

	msi-parent = <&msi1>;
	msi1: msi-controller {
	compatible = "brcm,iproc-msi";
	msi-controller;
	interrupt-parent = <&gic>;
	interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>,
	<GIC_SPI 189 IRQ_TYPE_NONE>,
	<GIC_SPI 190 IRQ_TYPE_NONE>,
	<GIC_SPI 191 IRQ_TYPE_NONE>;
	brcm,pcie-msi-inten;
	};
	};
	};