| commit | cd4d6f357545bc03112265b19e5ed50592812986 | [log] [tgz] |
|---|---|---|
| author | Joseph Lo <josephl@nvidia.com> | Wed May 29 16:21:33 2019 +0800 |
| committer | Thierry Reding <treding@nvidia.com> | Tue May 12 22:48:41 2020 +0200 |
| tree | c5c1e23047f2282d4b60353255a367d6b040964b | |
| parent | 3dcbd36fa34ce9124ec51accd835130251f74213 [diff] |
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210 Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>