tree c5c1e23047f2282d4b60353255a367d6b040964b
parent 3dcbd36fa34ce9124ec51accd835130251f74213
author Joseph Lo <josephl@nvidia.com> 1559118093 +0800
committer Thierry Reding <treding@nvidia.com> 1589316521 +0200

clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210

Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>