| /* |
| * arch/arm/mach-pxa/include/mach/pxa-regs.h |
| * |
| * Author: Nicolas Pitre |
| * Created: Jun 15, 2001 |
| * Copyright: MontaVista Software Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #ifndef __PXA_REGS_H |
| #define __PXA_REGS_H |
| |
| #include <mach/hardware.h> |
| |
| /* |
| * PXA Chip selects |
| */ |
| |
| #define PXA_CS0_PHYS 0x00000000 |
| #define PXA_CS1_PHYS 0x04000000 |
| #define PXA_CS2_PHYS 0x08000000 |
| #define PXA_CS3_PHYS 0x0C000000 |
| #define PXA_CS4_PHYS 0x10000000 |
| #define PXA_CS5_PHYS 0x14000000 |
| |
| |
| /* |
| * Real Time Clock |
| */ |
| |
| #define RCNR __REG(0x40900000) /* RTC Count Register */ |
| #define RTAR __REG(0x40900004) /* RTC Alarm Register */ |
| #define RTSR __REG(0x40900008) /* RTC Status Register */ |
| #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ |
| #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ |
| |
| #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ |
| #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ |
| #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ |
| #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ |
| #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ |
| #define RTSR_AL (1 << 0) /* RTC alarm detected */ |
| |
| |
| /* |
| * OS Timer & Match Registers |
| */ |
| |
| #define OSMR0 __REG(0x40A00000) /* */ |
| #define OSMR1 __REG(0x40A00004) /* */ |
| #define OSMR2 __REG(0x40A00008) /* */ |
| #define OSMR3 __REG(0x40A0000C) /* */ |
| #define OSMR4 __REG(0x40A00080) /* */ |
| #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ |
| #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ |
| #define OMCR4 __REG(0x40A000C0) /* */ |
| #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ |
| #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ |
| #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ |
| |
| #define OSSR_M3 (1 << 3) /* Match status channel 3 */ |
| #define OSSR_M2 (1 << 2) /* Match status channel 2 */ |
| #define OSSR_M1 (1 << 1) /* Match status channel 1 */ |
| #define OSSR_M0 (1 << 0) /* Match status channel 0 */ |
| |
| #define OWER_WME (1 << 0) /* Watchdog Match Enable */ |
| |
| #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ |
| #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ |
| #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ |
| #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ |
| |
| |
| /* |
| * Interrupt Controller |
| */ |
| |
| #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ |
| #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ |
| #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ |
| #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ |
| #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ |
| #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ |
| |
| #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ |
| #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ |
| #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ |
| #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ |
| #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ |
| |
| #endif |