arch/arm/boot/dts/intel-ixp43x-gateworks-gw2358.dts

// SPDX-License-Identifier: ISC
/*
 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
 */

/dts-v1/;

#include "intel-ixp43x.dtsi"

/ {
	model = "Gateworks Cambria GW2358";
	compatible = "gateworks,gw2358", "intel,ixp43x";
	#address-cells = <1>;
	#size-cells = <1>;

	memory@0 {
		/* 128 MB SDRAM */
		device_type = "memory";
		reg = <0x00000000 0x8000000>;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
		stdout-path = "uart0:115200n8";
	};

	aliases {
		serial0 = &uart0;
	};

	leds {
		compatible = "gpio-leds";
		led-user {
			label = "gw2358:green:LED";
			gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
			default-state = "on";
			linux,default-trigger = "heartbeat";
		};
	};


	i2c {
		compatible = "i2c-gpio";
		sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
		#address-cells = <1>;
		#size-cells = <0>;

		hwmon@28 {
			compatible = "adi,ad7418";
			reg = <0x28>;
		};
		rtc: ds1672@68 {
			compatible = "dallas,ds1672";
			reg = <0x68>;
		};
		eeprom@51 {
			compatible = "atmel,24c08";
			reg = <0x51>;
			pagesize = <16>;
			size = <1024>;
			read-only;
		};
		pld0: pld@56 {
			compatible = "gateworks,pld-gpio";
			reg = <0x56>;
			gpio-controller;
			#gpio-cells = <2>;
		};
		/* This PLD just handles the LED and user button */
		pld1: pld@57 {
			compatible = "gateworks,pld-gpio";
			reg = <0x57>;
			gpio-controller;
			#gpio-cells = <2>;
		};
	};

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/*
				 * 32 MB of Flash in 0x20000 byte blocks
				 * mapped in at CS0 and CS1
				 */
				reg = <0 0x00000000 0x2000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x1fe0000 */
					fis-index-block = <0xff>;
				};
			};
			ide@3,0 {
				compatible = "intel,ixp4xx-compact-flash";
				/*
				 * Set up expansion bus config to a really slow timing.
				 * The CF driver will dynamically reconfigure these timings
				 * depending on selected PIO mode (0-4).
				 */
				intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
				intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
				intel,ixp4xx-eb-byte-access-on-halfword = <1>;
				intel,ixp4xx-eb-mux-address-and-data = <0>;
				intel,ixp4xx-eb-ahb-split-transfers = <0>;
				intel,ixp4xx-eb-write-enable = <1>;
				intel,ixp4xx-eb-byte-access = <1>;
				/* First register set is CMD second is CTL */
				reg = <3 0xe00000 0x40000>, <3 0xe40000 0x40000>;
				interrupt-parent = <&gpio0>;
				interrupts = <12 IRQ_TYPE_EDGE_RISING>;
			};
		};

		pci@c0000000 {
			status = "ok";

			/*
			 * In the boardfile for the Cambria from OpenWRT the interrupts
			 * are assigned one per IDSEL, so all 4 interrupts from IDSEL
			 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
			 * connected to IRQ 10 etc. I find this highly unlikely so I
			 * have instead assumed that they are rotated (swizzled) like
			 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
			 */
			interrupt-map =
			/* IDSEL 1 */
			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
			/* IDSEL 2 */
			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
			<0x1000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
			<0x1000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
			<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
			/* IDSEL 3 */
			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
			<0x1800 0 0 2 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
			<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
			<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
			/* IDSEL 4 */
			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
			<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
			<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
			<0x2000 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 9 */
			/* IDSEL 6 */
			<0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
			<0x3000 0 0 2 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 9 */
			<0x3000 0 0 3 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 8 */
			<0x3000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 11 */
			/* IDSEL 15 */
			<0x7800 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
			<0x7800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */
			<0x7800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */
			<0x7800 0 0 4 &gpio0 9  IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 9 */
		};

		ethernet@c800a000 {
			status = "ok";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy1: ethernet-phy@1 {
					reg = <1>;
				};

				phy2: ethernet-phy@2 {
					reg = <2>;
				};
			};
		};

		ethernet@c800c000 {
			status = "ok";
			queue-rx = <&qmgr 2>;
			queue-txready = <&qmgr 19>;
			phy-mode = "rgmii";
			phy-handle = <&phy2>;
			intel,npe-handle = <&npe 0>;
		};
	};
};