| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Google Veyron Jerry Rev 3+ board device tree source |
| * |
| * Copyright 2015 Google, Inc |
| */ |
| |
| /dts-v1/; |
| #include "rk3288-veyron-chromebook.dtsi" |
| #include "cros-ec-sbs.dtsi" |
| |
| / { |
| model = "Google Jerry"; |
| compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14", |
| "google,veyron-jerry-rev13", "google,veyron-jerry-rev12", |
| "google,veyron-jerry-rev11", "google,veyron-jerry-rev10", |
| "google,veyron-jerry-rev7", "google,veyron-jerry-rev6", |
| "google,veyron-jerry-rev5", "google,veyron-jerry-rev4", |
| "google,veyron-jerry-rev3", "google,veyron-jerry", |
| "google,veyron", "rockchip,rk3288"; |
| |
| panel_regulator: panel-regulator { |
| compatible = "regulator-fixed"; |
| enable-active-high; |
| gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&lcd_enable_h>; |
| regulator-name = "panel_regulator"; |
| startup-delay-us = <100000>; |
| vin-supply = <&vcc33_sys>; |
| }; |
| |
| vcc18_lcd: vcc18-lcd { |
| compatible = "regulator-fixed"; |
| enable-active-high; |
| gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&avdd_1v8_disp_en>; |
| regulator-name = "vcc18_lcd"; |
| regulator-always-on; |
| regulator-boot-on; |
| vin-supply = <&vcc18_wl>; |
| }; |
| |
| backlight_regulator: backlight-regulator { |
| compatible = "regulator-fixed"; |
| enable-active-high; |
| gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&bl_pwr_en>; |
| regulator-name = "backlight_regulator"; |
| vin-supply = <&vcc33_sys>; |
| startup-delay-us = <15000>; |
| }; |
| }; |
| |
| &backlight { |
| power-supply = <&backlight_regulator>; |
| }; |
| |
| &panel { |
| power-supply= <&panel_regulator>; |
| }; |
| |
| &rk808 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; |
| dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>, |
| <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>; |
| |
| regulators { |
| mic_vcc: LDO_REG2 { |
| regulator-name = "mic_vcc"; |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-state-mem { |
| regulator-off-in-suspend; |
| }; |
| }; |
| }; |
| }; |
| |
| &sdmmc { |
| disable-wp; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio |
| &sdmmc_bus4>; |
| }; |
| |
| &vcc_5v { |
| enable-active-high; |
| gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&drv_5v>; |
| }; |
| |
| &vcc50_hdmi { |
| enable-active-high; |
| gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&vcc50_hdmi_en>; |
| }; |
| |
| &gpio0 { |
| gpio-line-names = "PMIC_SLEEP_AP", |
| "DDRIO_PWROFF", |
| "DDRIO_RETEN", |
| "TS3A227E_INT_L", |
| "PMIC_INT_L", |
| "PWR_KEY_L", |
| "AP_LID_INT_L", |
| "EC_IN_RW", |
| |
| "AC_PRESENT_AP", |
| /* |
| * RECOVERY_SW_L is Chrome OS ABI. Schematics call |
| * it REC_MODE_L. |
| */ |
| "RECOVERY_SW_L", |
| "OTP_OUT", |
| "HOST1_PWR_EN", |
| "USBOTG_PWREN_H", |
| "AP_WARM_RESET_H", |
| "nFAULT2", |
| "I2C0_SDA_PMIC", |
| |
| "I2C0_SCL_PMIC", |
| "SUSPEND_L", |
| "USB_INT"; |
| }; |
| |
| &gpio2 { |
| gpio-line-names = "CONFIG0", |
| "CONFIG1", |
| "CONFIG2", |
| "", |
| "", |
| "", |
| "", |
| "CONFIG3", |
| |
| "", |
| "EMMC_RST_L", |
| "", |
| "", |
| "BL_PWR_EN", |
| "AVDD_1V8_DISP_EN"; |
| }; |
| |
| &gpio3 { |
| gpio-line-names = "FLASH0_D0", |
| "FLASH0_D1", |
| "FLASH0_D2", |
| "FLASH0_D3", |
| "FLASH0_D4", |
| "FLASH0_D5", |
| "FLASH0_D6", |
| "FLASH0_D7", |
| |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| |
| "FLASH0_CS2/EMMC_CMD", |
| "", |
| "FLASH0_DQS/EMMC_CLKO"; |
| }; |
| |
| &gpio4 { |
| gpio-line-names = "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| |
| "UART0_RXD", |
| "UART0_TXD", |
| "UART0_CTS", |
| "UART0_RTS", |
| "SDIO0_D0", |
| "SDIO0_D1", |
| "SDIO0_D2", |
| "SDIO0_D3", |
| |
| "SDIO0_CMD", |
| "SDIO0_CLK", |
| "BT_DEV_WAKE", |
| "", |
| "WIFI_ENABLE_H", |
| "BT_ENABLE_L", |
| "WIFI_HOST_WAKE", |
| "BT_HOST_WAKE"; |
| }; |
| |
| &gpio5 { |
| gpio-line-names = "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| "", |
| |
| "", |
| "", |
| "", |
| "", |
| "SPI0_CLK", |
| "SPI0_CS0", |
| "SPI0_TXD", |
| "SPI0_RXD", |
| |
| "", |
| "", |
| "", |
| "VCC50_HDMI_EN"; |
| }; |
| |
| &gpio6 { |
| gpio-line-names = "I2S0_SCLK", |
| "I2S0_LRCK_RX", |
| "I2S0_LRCK_TX", |
| "I2S0_SDI", |
| "I2S0_SDO0", |
| "HP_DET_H", |
| "", |
| "INT_CODEC", |
| |
| "I2S0_CLK", |
| "I2C2_SDA", |
| "I2C2_SCL", |
| "MICDET", |
| "", |
| "", |
| "", |
| "", |
| |
| "SDMMC_D0", |
| "SDMMC_D1", |
| "SDMMC_D2", |
| "SDMMC_D3", |
| "SDMMC_CLK", |
| "SDMMC_CMD"; |
| }; |
| |
| &gpio7 { |
| gpio-line-names = "LCDC_BL", |
| "PWM_LOG", |
| "BL_EN", |
| "TRACKPAD_INT", |
| "TPM_INT_H", |
| "SDMMC_DET_L", |
| /* |
| * AP_FLASH_WP_L is Chrome OS ABI. Schematics call |
| * it FW_WP_AP. |
| */ |
| "AP_FLASH_WP_L", |
| "EC_INT", |
| |
| "CPU_NMI", |
| "DVSOK", |
| "", |
| "EDP_HPD", |
| "DVS1", |
| "nFAULT1", |
| "LCD_EN", |
| "DVS2", |
| |
| "VCC5V_GOOD_H", |
| "I2C4_SDA_TP", |
| "I2C4_SCL_TP", |
| "I2C5_SDA_HDMI", |
| "I2C5_SCL_HDMI", |
| "5V_DRV", |
| "UART2_RXD", |
| "UART2_TXD"; |
| }; |
| |
| &gpio8 { |
| gpio-line-names = "RAM_ID0", |
| "RAM_ID1", |
| "RAM_ID2", |
| "RAM_ID3", |
| "I2C1_SDA_TPM", |
| "I2C1_SCL_TPM", |
| "SPI2_CLK", |
| "SPI2_CS0", |
| |
| "SPI2_RXD", |
| "SPI2_TXD"; |
| }; |
| |
| &pinctrl { |
| backlight { |
| bl_pwr_en: bl_pwr_en { |
| rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; |
| }; |
| }; |
| |
| buck-5v { |
| drv_5v: drv-5v { |
| rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; |
| }; |
| }; |
| |
| hdmi { |
| vcc50_hdmi_en: vcc50-hdmi-en { |
| rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; |
| }; |
| }; |
| |
| lcd { |
| lcd_enable_h: lcd-en { |
| rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; |
| }; |
| |
| avdd_1v8_disp_en: avdd-1v8-disp-en { |
| rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; |
| }; |
| }; |
| |
| pmic { |
| dvs_1: dvs-1 { |
| rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; |
| }; |
| |
| dvs_2: dvs-2 { |
| rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; |
| }; |
| }; |
| }; |
| |
| &i2c4 { |
| status = "okay"; |
| |
| /* |
| * Trackpad pin control is shared between Elan and Synaptics devices |
| * so we have to pull it up to the bus level. |
| */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c4_xfer &trackpad_int>; |
| |
| trackpad@15 { |
| /* |
| * Remove the inherited pinctrl settings to avoid clashing |
| * with bus-wide ones. |
| */ |
| /delete-property/pinctrl-names; |
| /delete-property/pinctrl-0; |
| }; |
| |
| trackpad@2c { |
| compatible = "hid-over-i2c"; |
| interrupt-parent = <&gpio7>; |
| interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>; |
| reg = <0x2c>; |
| hid-descr-addr = <0x0020>; |
| vcc-supply = <&vcc33_io>; |
| wakeup-source; |
| }; |
| }; |