| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "nvidia,tegra186"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| uarta: serial@3100000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03100000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp 55>; |
| clock-names = "serial"; |
| resets = <&bpmp 47>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartb: serial@3110000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03110000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp 56>; |
| clock-names = "serial"; |
| resets = <&bpmp 48>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartd: serial@3130000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03130000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp 77>; |
| clock-names = "serial"; |
| resets = <&bpmp 50>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uarte: serial@3140000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03140000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp 194>; |
| clock-names = "serial"; |
| resets = <&bpmp 132>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartf: serial@3150000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03150000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp 195>; |
| clock-names = "serial"; |
| resets = <&bpmp 111>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| gen1_i2c: i2c@3160000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x03160000 0x0 0x10000>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 47>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 19>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| cam_i2c: i2c@3180000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x03180000 0x0 0x10000>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 75>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 21>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* shares pads with dpaux1 */ |
| dp_aux_ch1_i2c: i2c@3190000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x03190000 0x0 0x10000>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 86>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 22>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* controlled by BPMP, should not be enabled */ |
| pwr_i2c: i2c@31a0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031a0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 48>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 23>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* shares pads with dpaux0 */ |
| dp_aux_ch0_i2c: i2c@31b0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031b0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 125>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 24>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| gen7_i2c: i2c@31c0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031c0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 182>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 81>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| gen9_i2c: i2c@31e0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031e0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 183>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 83>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@3881000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0x03881000 0x0 0x1000>, |
| <0x0 0x03882000 0x0 0x2000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| hsp_top0: hsp@3c00000 { |
| compatible = "nvidia,tegra186-hsp"; |
| reg = <0x0 0x03c00000 0x0 0xa0000>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "doorbell"; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gen2_i2c: i2c@c240000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x0c240000 0x0 0x10000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 218>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 20>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| gen8_i2c: i2c@c250000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x0c250000 0x0 0x10000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp 219>; |
| clock-names = "div-clk"; |
| resets = <&bpmp 82>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| uartc: serial@c280000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x0c280000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp 215>; |
| clock-names = "serial"; |
| resets = <&bpmp 49>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartg: serial@c290000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x0c290000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp 216>; |
| clock-names = "serial"; |
| resets = <&bpmp 112>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| sysram@30000000 { |
| compatible = "nvidia,tegra186-sysram", "mmio-sram"; |
| reg = <0x0 0x30000000 0x0 0x50000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; |
| |
| cpu_bpmp_tx: shmem@4e000 { |
| compatible = "nvidia,tegra186-bpmp-shmem"; |
| reg = <0x0 0x4e000 0x0 0x1000>; |
| label = "cpu-bpmp-tx"; |
| pool; |
| }; |
| |
| cpu_bpmp_rx: shmem@4f000 { |
| compatible = "nvidia,tegra186-bpmp-shmem"; |
| reg = <0x0 0x4f000 0x0 0x1000>; |
| label = "cpu-bpmp-rx"; |
| pool; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "nvidia,tegra186-denver", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x000>; |
| }; |
| |
| cpu@1 { |
| compatible = "nvidia,tegra186-denver", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x001>; |
| }; |
| |
| cpu@2 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x100>; |
| }; |
| |
| cpu@3 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x101>; |
| }; |
| |
| cpu@4 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x102>; |
| }; |
| |
| cpu@5 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x103>; |
| }; |
| }; |
| |
| bpmp: bpmp { |
| compatible = "nvidia,tegra186-bpmp"; |
| mboxes = <&hsp_top0 0 19>; |
| shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| |
| bpmp_i2c: i2c { |
| compatible = "nvidia,tegra186-bpmp-i2c"; |
| nvidia,bpmp-bus-id = <5>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| interrupt-parent = <&gic>; |
| }; |
| }; |