| // SPDX-License-Identifier: GPL-2.0 |
| |
| #include <dt-bindings/clock/tegra234-clock.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/mailbox/tegra186-hsp.h> |
| #include <dt-bindings/memory/tegra234-mc.h> |
| #include <dt-bindings/reset/tegra234-reset.h> |
| |
| / { |
| compatible = "nvidia,tegra234"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| bus@0 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ranges = <0x0 0x0 0x0 0x40000000>; |
| |
| misc@100000 { |
| compatible = "nvidia,tegra234-misc"; |
| reg = <0x00100000 0xf000>, |
| <0x0010f000 0x1000>; |
| status = "okay"; |
| }; |
| |
| gpio: gpio@2200000 { |
| compatible = "nvidia,tegra234-gpio"; |
| reg-names = "security", "gpio"; |
| reg = <0x02200000 0x10000>, |
| <0x02210000 0x10000>; |
| interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| mc: memory-controller@2c00000 { |
| compatible = "nvidia,tegra234-mc"; |
| reg = <0x02c00000 0x100000>, |
| <0x02b80000 0x040000>, |
| <0x01700000 0x100000>; |
| interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; |
| #interconnect-cells = <1>; |
| status = "okay"; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, |
| <0x02b80000 0x0 0x02b80000 0x0 0x040000>, |
| <0x02c00000 0x0 0x02c00000 0x0 0x100000>; |
| |
| /* |
| * Bit 39 of addresses passing through the memory |
| * controller selects the XBAR format used when memory |
| * is accessed. This is used to transparently access |
| * memory in the XBAR format used by the discrete GPU |
| * (bit 39 set) or Tegra (bit 39 clear). |
| * |
| * As a consequence, the operating system must ensure |
| * that bit 39 is never used implicitly, for example |
| * via an I/O virtual address mapping of an IOMMU. If |
| * devices require access to the XBAR switch, their |
| * drivers must set this bit explicitly. |
| * |
| * Limit the DMA range for memory clients to [38:0]. |
| */ |
| dma-ranges = <0x0 0x0 0x0 0x80 0x0>; |
| |
| emc: external-memory-controller@2c60000 { |
| compatible = "nvidia,tegra234-emc"; |
| reg = <0x0 0x02c60000 0x0 0x90000>, |
| <0x0 0x01780000 0x0 0x80000>; |
| interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA234_CLK_EMC>; |
| clock-names = "emc"; |
| status = "okay"; |
| |
| #interconnect-cells = <0>; |
| |
| nvidia,bpmp = <&bpmp>; |
| }; |
| }; |
| |
| uarta: serial@3100000 { |
| compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; |
| reg = <0x03100000 0x10000>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA234_CLK_UARTA>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA234_RESET_UARTA>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| mmc@3460000 { |
| compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; |
| reg = <0x03460000 0x20000>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA234_CLK_SDMMC4>, |
| <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; |
| clock-names = "sdhci", "tmclk"; |
| assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, |
| <&bpmp TEGRA234_CLK_PLLC4>; |
| assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; |
| resets = <&bpmp TEGRA234_RESET_SDMMC4>; |
| reset-names = "sdhci"; |
| interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, |
| <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; |
| interconnect-names = "dma-mem", "write"; |
| nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; |
| nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; |
| nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; |
| nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; |
| nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; |
| nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; |
| nvidia,default-tap = <0x8>; |
| nvidia,default-trim = <0x14>; |
| nvidia,dqs-trim = <40>; |
| supports-cqe; |
| status = "disabled"; |
| }; |
| |
| fuse@3810000 { |
| compatible = "nvidia,tegra234-efuse"; |
| reg = <0x03810000 0x10000>; |
| clocks = <&bpmp TEGRA234_CLK_FUSE>; |
| clock-names = "fuse"; |
| }; |
| |
| hsp_top0: hsp@3c00000 { |
| compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; |
| reg = <0x03c00000 0xa0000>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "doorbell", "shared0", "shared1", "shared2", |
| "shared3", "shared4", "shared5", "shared6", |
| "shared7"; |
| #mbox-cells = <2>; |
| }; |
| |
| hsp_aon: hsp@c150000 { |
| compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; |
| reg = <0x0c150000 0x90000>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| /* |
| * Shared interrupt 0 is routed only to AON/SPE, so |
| * we only have 4 shared interrupts for the CCPLEX. |
| */ |
| interrupt-names = "shared1", "shared2", "shared3", "shared4"; |
| #mbox-cells = <2>; |
| }; |
| |
| rtc@c2a0000 { |
| compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; |
| reg = <0x0c2a0000 0x10000>; |
| interrupt-parent = <&pmc>; |
| interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA234_CLK_CLK_32K>; |
| clock-names = "rtc"; |
| status = "disabled"; |
| }; |
| |
| gpio_aon: gpio@c2f0000 { |
| compatible = "nvidia,tegra234-gpio-aon"; |
| reg-names = "security", "gpio"; |
| reg = <0x0c2f0000 0x1000>, |
| <0x0c2f1000 0x1000>; |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| pmc: pmc@c360000 { |
| compatible = "nvidia,tegra234-pmc"; |
| reg = <0x0c360000 0x10000>, |
| <0x0c370000 0x10000>, |
| <0x0c380000 0x10000>, |
| <0x0c390000 0x10000>, |
| <0x0c3a0000 0x10000>; |
| reg-names = "pmc", "wake", "aotag", "scratch", "misc"; |
| |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| }; |
| |
| gic: interrupt-controller@f400000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0f400000 0x010000>, /* GICD */ |
| <0x0f440000 0x200000>; /* GICR */ |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| |
| #redistributor-regions = <1>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| }; |
| }; |
| |
| sram@40000000 { |
| compatible = "nvidia,tegra234-sysram", "mmio-sram"; |
| reg = <0x0 0x40000000 0x0 0x80000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x40000000 0x80000>; |
| |
| cpu_bpmp_tx: sram@70000 { |
| reg = <0x70000 0x1000>; |
| label = "cpu-bpmp-tx"; |
| pool; |
| }; |
| |
| cpu_bpmp_rx: sram@71000 { |
| reg = <0x71000 0x1000>; |
| label = "cpu-bpmp-rx"; |
| pool; |
| }; |
| }; |
| |
| bpmp: bpmp { |
| compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; |
| mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB |
| TEGRA_HSP_DB_MASTER_BPMP>; |
| shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, |
| <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, |
| <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, |
| <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; |
| interconnect-names = "read", "write", "dma-mem", "dma-write"; |
| |
| bpmp_i2c: i2c { |
| compatible = "nvidia,tegra186-bpmp-i2c"; |
| nvidia,bpmp-bus-id = <5>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0_0: cpu@0 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x00000>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c0_0>; |
| }; |
| |
| cpu0_1: cpu@100 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x00100>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c0_1>; |
| }; |
| |
| cpu0_2: cpu@200 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x00200>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c0_2>; |
| }; |
| |
| cpu0_3: cpu@300 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x00300>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c0_3>; |
| }; |
| |
| cpu1_0: cpu@10000 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x10000>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c1_0>; |
| }; |
| |
| cpu1_1: cpu@10100 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x10100>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c1_1>; |
| }; |
| |
| cpu1_2: cpu@10200 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x10200>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c1_2>; |
| }; |
| |
| cpu1_3: cpu@10300 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x10300>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c1_3>; |
| }; |
| |
| cpu2_0: cpu@20000 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x20000>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c2_0>; |
| }; |
| |
| cpu2_1: cpu@20100 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x20100>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c2_1>; |
| }; |
| |
| cpu2_2: cpu@20200 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x20200>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c2_2>; |
| }; |
| |
| cpu2_3: cpu@20300 { |
| compatible = "arm,cortex-a78"; |
| device_type = "cpu"; |
| reg = <0x20300>; |
| |
| enable-method = "psci"; |
| |
| i-cache-size = <65536>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <65536>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&l2c2_3>; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&cpu0_0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu0_1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu0_2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu0_3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&cpu1_0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu1_1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu1_2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu1_3>; |
| }; |
| }; |
| |
| cluster2 { |
| core0 { |
| cpu = <&cpu2_0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu2_1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu2_2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu2_3>; |
| }; |
| }; |
| }; |
| |
| l2c0_0: l2-cache00 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c0>; |
| }; |
| |
| l2c0_1: l2-cache01 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c0>; |
| }; |
| |
| l2c0_2: l2-cache02 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c0>; |
| }; |
| |
| l2c0_3: l2-cache03 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c0>; |
| }; |
| |
| l2c1_0: l2-cache10 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c1>; |
| }; |
| |
| l2c1_1: l2-cache11 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c1>; |
| }; |
| |
| l2c1_2: l2-cache12 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c1>; |
| }; |
| |
| l2c1_3: l2-cache13 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c1>; |
| }; |
| |
| l2c2_0: l2-cache20 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c2>; |
| }; |
| |
| l2c2_1: l2-cache21 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c2>; |
| }; |
| |
| l2c2_2: l2-cache22 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c2>; |
| }; |
| |
| l2c2_3: l2-cache23 { |
| cache-size = <262144>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-unified; |
| next-level-cache = <&l3c2>; |
| }; |
| |
| l3c0: l3-cache0 { |
| cache-size = <2097152>; |
| cache-line-size = <64>; |
| cache-sets = <2048>; |
| }; |
| |
| l3c1: l3-cache1 { |
| cache-size = <2097152>; |
| cache-line-size = <64>; |
| cache-sets = <2048>; |
| }; |
| |
| l3c2: l3-cache2 { |
| cache-size = <2097152>; |
| cache-line-size = <64>; |
| cache-sets = <2048>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a78-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| status = "okay"; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| status = "okay"; |
| method = "smc"; |
| }; |
| |
| tcu: serial { |
| compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; |
| mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, |
| <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; |
| mbox-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| interrupt-parent = <&gic>; |
| always-on; |
| }; |
| }; |