| Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 1 | /* |
| Andrew Victor | 9d04126 | 2007-02-05 11:42:07 +0100 | [diff] [blame] | 2 | * include/asm-arm/arch-at91/at91sam9261.h |
| Andrew Victor | 62c1660 | 2006-11-30 12:27:38 +0100 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) SAN People |
| 5 | * |
| 6 | * Common definitions. |
| 7 | * Based on AT91SAM9261 datasheet revision E. (Preliminary) |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | */ |
| 14 | |
| 15 | #ifndef AT91SAM9261_H |
| 16 | #define AT91SAM9261_H |
| 17 | |
| 18 | /* |
| 19 | * Peripheral identifiers/interrupts. |
| 20 | */ |
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
| 22 | #define AT91_ID_SYS 1 /* System Peripherals */ |
| 23 | #define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ |
| 24 | #define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ |
| 25 | #define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ |
| 26 | #define AT91SAM9261_ID_US0 6 /* USART 0 */ |
| 27 | #define AT91SAM9261_ID_US1 7 /* USART 1 */ |
| 28 | #define AT91SAM9261_ID_US2 8 /* USART 2 */ |
| 29 | #define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ |
| 30 | #define AT91SAM9261_ID_UDP 10 /* USB Device Port */ |
| 31 | #define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ |
| 32 | #define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ |
| 33 | #define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ |
| 34 | #define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
| 35 | #define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
| 36 | #define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ |
| 37 | #define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ |
| 38 | #define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ |
| 39 | #define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ |
| 40 | #define AT91SAM9261_ID_UHP 20 /* USB Host port */ |
| 41 | #define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ |
| 42 | #define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ |
| 43 | #define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ |
| 44 | #define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ |
| 45 | |
| 46 | |
| 47 | /* |
| 48 | * User Peripheral physical base addresses. |
| 49 | */ |
| 50 | #define AT91SAM9261_BASE_TCB0 0xfffa0000 |
| 51 | #define AT91SAM9261_BASE_TC0 0xfffa0000 |
| 52 | #define AT91SAM9261_BASE_TC1 0xfffa0040 |
| 53 | #define AT91SAM9261_BASE_TC2 0xfffa0080 |
| 54 | #define AT91SAM9261_BASE_UDP 0xfffa4000 |
| 55 | #define AT91SAM9261_BASE_MCI 0xfffa8000 |
| 56 | #define AT91SAM9261_BASE_TWI 0xfffac000 |
| 57 | #define AT91SAM9261_BASE_US0 0xfffb0000 |
| 58 | #define AT91SAM9261_BASE_US1 0xfffb4000 |
| 59 | #define AT91SAM9261_BASE_US2 0xfffb8000 |
| 60 | #define AT91SAM9261_BASE_SSC0 0xfffbc000 |
| 61 | #define AT91SAM9261_BASE_SSC1 0xfffc0000 |
| 62 | #define AT91SAM9261_BASE_SSC2 0xfffc4000 |
| 63 | #define AT91SAM9261_BASE_SPI0 0xfffc8000 |
| 64 | #define AT91SAM9261_BASE_SPI1 0xfffcc000 |
| 65 | #define AT91_BASE_SYS 0xffffea00 |
| 66 | |
| 67 | |
| 68 | /* |
| 69 | * System Peripherals (offset from AT91_BASE_SYS) |
| 70 | */ |
| 71 | #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) |
| 72 | #define AT91_SMC (0xffffec00 - AT91_BASE_SYS) |
| 73 | #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) |
| 74 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) |
| 75 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) |
| 76 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) |
| 77 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) |
| 78 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) |
| 79 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) |
| 80 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) |
| 81 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) |
| 82 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) |
| 83 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) |
| 84 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) |
| 85 | #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) |
| 86 | |
| 87 | |
| 88 | /* |
| 89 | * Internal Memory. |
| 90 | */ |
| 91 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
| 92 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ |
| 93 | |
| 94 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ |
| 95 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ |
| 96 | |
| 97 | #define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ |
| 98 | #define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ |
| 99 | |
| 100 | |
| 101 | #if 0 |
| 102 | /* |
| 103 | * PIO pin definitions (peripheral A/B multiplexing). |
| 104 | */ |
| 105 | #define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */ |
| 106 | #define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */ |
| 107 | #define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */ |
| 108 | #define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */ |
| 109 | #define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */ |
| 110 | #define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */ |
| 111 | #define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */ |
| 112 | #define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */ |
| 113 | #define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */ |
| 114 | #define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */ |
| 115 | #define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */ |
| 116 | #define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */ |
| 117 | #define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */ |
| 118 | #define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */ |
| 119 | #define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */ |
| 120 | #define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */ |
| 121 | #define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */ |
| 122 | #define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */ |
| 123 | #define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */ |
| 124 | #define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */ |
| 125 | #define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */ |
| 126 | #define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */ |
| 127 | #define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */ |
| 128 | #define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */ |
| 129 | #define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */ |
| 130 | #define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */ |
| 131 | #define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */ |
| 132 | #define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */ |
| 133 | #define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */ |
| 134 | #define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */ |
| 135 | #define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */ |
| 136 | #define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */ |
| 137 | #define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */ |
| 138 | #define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */ |
| 139 | #define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */ |
| 140 | #define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */ |
| 141 | #define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */ |
| 142 | #define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */ |
| 143 | #define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */ |
| 144 | #define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */ |
| 145 | #define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */ |
| 146 | #define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */ |
| 147 | #define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */ |
| 148 | #define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */ |
| 149 | #define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */ |
| 150 | #define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */ |
| 151 | #define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */ |
| 152 | #define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */ |
| 153 | #define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */ |
| 154 | #define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */ |
| 155 | #define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */ |
| 156 | #define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */ |
| 157 | #define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */ |
| 158 | #define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */ |
| 159 | #define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */ |
| 160 | #define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */ |
| 161 | #define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */ |
| 162 | #define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */ |
| 163 | #define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */ |
| 164 | #define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */ |
| 165 | #define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */ |
| 166 | #define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */ |
| 167 | #define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */ |
| 168 | |
| 169 | #define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */ |
| 170 | #define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */ |
| 171 | #define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */ |
| 172 | #define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */ |
| 173 | #define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */ |
| 174 | #define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */ |
| 175 | #define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */ |
| 176 | #define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */ |
| 177 | #define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */ |
| 178 | #define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */ |
| 179 | #define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */ |
| 180 | #define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */ |
| 181 | #define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */ |
| 182 | #define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */ |
| 183 | #define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */ |
| 184 | #define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */ |
| 185 | #define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */ |
| 186 | #define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */ |
| 187 | #define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */ |
| 188 | #define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */ |
| 189 | #define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */ |
| 190 | #define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */ |
| 191 | #define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */ |
| 192 | #define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */ |
| 193 | #define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */ |
| 194 | #define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */ |
| 195 | #define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */ |
| 196 | #define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */ |
| 197 | #define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */ |
| 198 | #define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */ |
| 199 | #define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */ |
| 200 | #define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */ |
| 201 | #define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */ |
| 202 | #define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */ |
| 203 | #define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */ |
| 204 | #define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */ |
| 205 | #define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */ |
| 206 | #define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */ |
| 207 | #define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */ |
| 208 | #define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */ |
| 209 | #define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */ |
| 210 | #define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */ |
| 211 | #define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */ |
| 212 | #define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */ |
| 213 | #define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */ |
| 214 | #define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */ |
| 215 | #define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */ |
| 216 | #define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */ |
| 217 | #define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */ |
| 218 | #define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */ |
| 219 | #define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */ |
| 220 | #define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */ |
| 221 | #define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */ |
| 222 | #define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */ |
| 223 | #define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */ |
| 224 | #define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */ |
| 225 | #define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */ |
| 226 | #define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */ |
| 227 | #define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */ |
| 228 | #define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */ |
| 229 | #define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */ |
| 230 | |
| 231 | #define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */ |
| 232 | #define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */ |
| 233 | #define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */ |
| 234 | #define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */ |
| 235 | #define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */ |
| 236 | #define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */ |
| 237 | #define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */ |
| 238 | #define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */ |
| 239 | #define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */ |
| 240 | #define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */ |
| 241 | #define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */ |
| 242 | #define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */ |
| 243 | #define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */ |
| 244 | #define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */ |
| 245 | #define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */ |
| 246 | #define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */ |
| 247 | #define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */ |
| 248 | #define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */ |
| 249 | #define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */ |
| 250 | #define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */ |
| 251 | #define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */ |
| 252 | #define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */ |
| 253 | #define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */ |
| 254 | #define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */ |
| 255 | #define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */ |
| 256 | #define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */ |
| 257 | #define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */ |
| 258 | #define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */ |
| 259 | #define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */ |
| 260 | #define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */ |
| 261 | #define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */ |
| 262 | #define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */ |
| 263 | #define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */ |
| 264 | #define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */ |
| 265 | #define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */ |
| 266 | #define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */ |
| 267 | #define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */ |
| 268 | #define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */ |
| 269 | #define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */ |
| 270 | #define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */ |
| 271 | #define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */ |
| 272 | #define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */ |
| 273 | #define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */ |
| 274 | #define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */ |
| 275 | #define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */ |
| 276 | #define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */ |
| 277 | #define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */ |
| 278 | #define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */ |
| 279 | #define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */ |
| 280 | #define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */ |
| 281 | #define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */ |
| 282 | #define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */ |
| 283 | #define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */ |
| 284 | #define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */ |
| 285 | #define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */ |
| 286 | #define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */ |
| 287 | #define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */ |
| 288 | #define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */ |
| 289 | #define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */ |
| 290 | #endif |
| 291 | |
| 292 | #endif |