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Roger Tsenge1237932013-02-04 15:45:59 +08001/* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 *
22 * Roger Tseng <rogerable@realtek.com>
23 * No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
24 */
25
26#include <linux/module.h>
27#include <linux/delay.h>
28#include <linux/mfd/rtsx_pci.h>
29
30#include "rtsx_pcr.h"
31
Wei WANG773ccdf2013-08-20 14:18:51 +080032static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
33{
34 u8 driving_3v3[4][3] = {
35 {0x13, 0x13, 0x13},
36 {0x96, 0x96, 0x96},
37 {0x7F, 0x7F, 0x7F},
38 {0x96, 0x96, 0x96},
39 };
40 u8 driving_1v8[4][3] = {
41 {0x99, 0x99, 0x99},
42 {0xAA, 0xAA, 0xAA},
43 {0xFE, 0xFE, 0xFE},
44 {0xB3, 0xB3, 0xB3},
45 };
46 u8 (*driving)[3], drive_sel;
47
48 if (voltage == OUTPUT_3V3) {
49 driving = driving_3v3;
50 drive_sel = pcr->sd30_drive_sel_3v3;
51 } else {
52 driving = driving_1v8;
53 drive_sel = pcr->sd30_drive_sel_1v8;
54 }
55
56 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
57 0xFF, driving[drive_sel][0]);
58 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
59 0xFF, driving[drive_sel][1]);
60 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
61 0xFF, driving[drive_sel][2]);
62}
63
64static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
65{
66 u32 reg;
67
68 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, &reg);
69 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
70
71 if (!rtsx_vendor_setting_valid(reg))
72 return;
73
74 pcr->aspm_en = rtsx_reg_to_aspm(reg);
75 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
76 pcr->card_drive_sel &= 0x3F;
77 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
78
79 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, &reg);
80 dev_dbg(&(pcr->pci->dev), "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
81 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
82 if (rtsx_reg_check_reverse_socket(reg))
83 pcr->flags |= PCR_REVERSE_SOCKET;
84}
85
Wei WANGeb891c62013-08-20 14:18:55 +080086static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
Wei WANG5947c162013-08-20 14:18:52 +080087{
88 /* Set relink_time to 0 */
89 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
90 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
91 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
92
Wei WANGeb891c62013-08-20 14:18:55 +080093 if (pm_state == HOST_ENTER_S3)
94 rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
95
Wei WANG5947c162013-08-20 14:18:52 +080096 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
97}
98
Roger Tsenge1237932013-02-04 15:45:59 +080099static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
100{
101 u16 cap;
102
103 rtsx_pci_init_cmd(pcr);
104
105 /* Configure GPIO as output */
106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
Wei WANG71408122013-08-20 14:18:53 +0800107 /* Reset ASPM state to default value */
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
Roger Tsenge1237932013-02-04 15:45:59 +0800109 /* Switch LDO3318 source from DV33 to card_3v3 */
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
112 /* LED shine disabled, set initial shine cycle period */
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
114 /* Configure LTR */
115 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
116 if (cap & PCI_EXP_LTR_EN)
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
118 /* Configure OBFF */
119 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
Wei WANG773ccdf2013-08-20 14:18:51 +0800120 /* Configure driving */
121 rts5227_fill_driving(pcr, OUTPUT_3V3);
122 /* Configure force_clock_req */
123 if (pcr->flags & PCR_REVERSE_SOCKET)
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
125 AUTOLOAD_CFG_BASE + 3, 0xB8, 0xB8);
126 else
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
128 AUTOLOAD_CFG_BASE + 3, 0xB8, 0x88);
Wei WANGeb891c62013-08-20 14:18:55 +0800129 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
Roger Tsenge1237932013-02-04 15:45:59 +0800130
131 return rtsx_pci_send_cmd(pcr, 100);
132}
133
134static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
135{
136 /* Optimize RX sensitivity */
137 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
138}
139
140static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
141{
142 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
143}
144
145static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
146{
147 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
148}
149
150static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
151{
152 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
153}
154
155static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
156{
157 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
158}
159
160static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
161{
162 int err;
163
164 rtsx_pci_init_cmd(pcr);
165 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
166 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
167 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
168 LDO3318_PWR_MASK, 0x02);
169 err = rtsx_pci_send_cmd(pcr, 100);
170 if (err < 0)
171 return err;
172
173 /* To avoid too large in-rush current */
174 udelay(150);
175
176 rtsx_pci_init_cmd(pcr);
177 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
178 SD_POWER_MASK, SD_POWER_ON);
179 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
180 LDO3318_PWR_MASK, 0x06);
181 err = rtsx_pci_send_cmd(pcr, 100);
182 if (err < 0)
183 return err;
184
185 return 0;
186}
187
188static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
189{
190 rtsx_pci_init_cmd(pcr);
191 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
192 SD_POWER_MASK | PMOS_STRG_MASK,
193 SD_POWER_OFF | PMOS_STRG_400mA);
194 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
195 LDO3318_PWR_MASK, 0X00);
196 return rtsx_pci_send_cmd(pcr, 100);
197}
198
199static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
200{
201 int err;
Roger Tsenge1237932013-02-04 15:45:59 +0800202
203 if (voltage == OUTPUT_3V3) {
204 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
205 if (err < 0)
206 return err;
Roger Tsenge1237932013-02-04 15:45:59 +0800207 } else if (voltage == OUTPUT_1V8) {
208 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
209 if (err < 0)
210 return err;
211 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
212 if (err < 0)
213 return err;
Roger Tsenge1237932013-02-04 15:45:59 +0800214 } else {
215 return -EINVAL;
216 }
217
218 /* set pad drive */
219 rtsx_pci_init_cmd(pcr);
Wei WANG773ccdf2013-08-20 14:18:51 +0800220 rts5227_fill_driving(pcr, voltage);
Roger Tsenge1237932013-02-04 15:45:59 +0800221 return rtsx_pci_send_cmd(pcr, 100);
222}
223
224static const struct pcr_ops rts5227_pcr_ops = {
Wei WANG773ccdf2013-08-20 14:18:51 +0800225 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
Roger Tsenge1237932013-02-04 15:45:59 +0800226 .extra_init_hw = rts5227_extra_init_hw,
227 .optimize_phy = rts5227_optimize_phy,
228 .turn_on_led = rts5227_turn_on_led,
229 .turn_off_led = rts5227_turn_off_led,
230 .enable_auto_blink = rts5227_enable_auto_blink,
231 .disable_auto_blink = rts5227_disable_auto_blink,
232 .card_power_on = rts5227_card_power_on,
233 .card_power_off = rts5227_card_power_off,
234 .switch_output_voltage = rts5227_switch_output_voltage,
235 .cd_deglitch = NULL,
236 .conv_clk_and_div_n = NULL,
Wei WANG5947c162013-08-20 14:18:52 +0800237 .force_power_down = rts5227_force_power_down,
Roger Tsenge1237932013-02-04 15:45:59 +0800238};
239
240/* SD Pull Control Enable:
241 * SD_DAT[3:0] ==> pull up
242 * SD_CD ==> pull up
243 * SD_WP ==> pull up
244 * SD_CMD ==> pull up
245 * SD_CLK ==> pull down
246 */
247static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
248 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
249 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
250 0,
251};
252
253/* SD Pull Control Disable:
254 * SD_DAT[3:0] ==> pull down
255 * SD_CD ==> pull up
256 * SD_WP ==> pull down
257 * SD_CMD ==> pull down
258 * SD_CLK ==> pull down
259 */
260static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
261 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
262 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
263 0,
264};
265
266/* MS Pull Control Enable:
267 * MS CD ==> pull up
268 * others ==> pull down
269 */
270static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
271 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
272 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
273 0,
274};
275
276/* MS Pull Control Disable:
277 * MS CD ==> pull up
278 * others ==> pull down
279 */
280static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
281 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
282 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
283 0,
284};
285
286void rts5227_init_params(struct rtsx_pcr *pcr)
287{
288 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
289 pcr->num_slots = 2;
290 pcr->ops = &rts5227_pcr_ops;
291
Wei WANG773ccdf2013-08-20 14:18:51 +0800292 pcr->flags = 0;
293 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
294 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
295 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
296 pcr->aspm_en = ASPM_L1_EN;
297
Roger Tsenge1237932013-02-04 15:45:59 +0800298 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
299 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
300 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
301 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
302}