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jilai wang9626b692015-04-10 16:15:59 -04001/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
Lina Iyer2ce76a62015-03-02 16:30:29 -07002 * Copyright (C) 2015 Linaro Ltd.
Stephen Boyd2a1eb582010-08-27 10:01:23 -07003 *
David Brown3162aa22011-02-14 16:15:26 -08004 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
Stephen Boyd2a1eb582010-08-27 10:01:23 -07007 *
David Brown3162aa22011-02-14 16:15:26 -08008 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
Stephen Boyd2a1eb582010-08-27 10:01:23 -070012 */
Kumar Gala4de43472015-02-04 16:30:46 -060013#ifndef __QCOM_SCM_H
14#define __QCOM_SCM_H
Stephen Boyd2a1eb582010-08-27 10:01:23 -070015
Jordan Crouse29ff62f2017-12-04 10:18:46 -070016#include <linux/types.h>
17#include <linux/cpumask.h>
18
Stanimir Varbanove1279912016-11-22 19:03:09 +020019#define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
20#define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
21#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
jilai wang9626b692015-04-10 16:15:59 -040022#define QCOM_SCM_HDCP_MAX_REQ_CNT 5
23
24struct qcom_scm_hdcp_req {
25 u32 addr;
26 u32 val;
27};
28
Avaneesh Kumar Dwivedid82bd352017-10-24 21:22:24 +053029struct qcom_scm_vmperm {
30 int vmid;
31 int perm;
32};
33
34#define QCOM_SCM_VMID_HLOS 0x3
35#define QCOM_SCM_VMID_MSS_MSA 0xF
36#define QCOM_SCM_PERM_READ 0x4
37#define QCOM_SCM_PERM_WRITE 0x2
38#define QCOM_SCM_PERM_EXEC 0x1
39#define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
40#define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
41
Stanimir Varbanove1279912016-11-22 19:03:09 +020042#if IS_ENABLED(CONFIG_QCOM_SCM)
43extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
44extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
Rob Clark2d3c2772015-09-29 15:48:55 -040045extern bool qcom_scm_is_available(void);
jilai wang9626b692015-04-10 16:15:59 -040046extern bool qcom_scm_hdcp_available(void);
47extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
Stanimir Varbanove1279912016-11-22 19:03:09 +020048 u32 *resp);
Bjorn Anderssonf01e90f2015-09-23 12:56:12 -070049extern bool qcom_scm_pas_supported(u32 peripheral);
50extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
Stanimir Varbanove1279912016-11-22 19:03:09 +020051 size_t size);
Bjorn Anderssonf01e90f2015-09-23 12:56:12 -070052extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
Stanimir Varbanove1279912016-11-22 19:03:09 +020053 phys_addr_t size);
Bjorn Anderssonf01e90f2015-09-23 12:56:12 -070054extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
55extern int qcom_scm_pas_shutdown(u32 peripheral);
Avaneesh Kumar Dwivedid82bd352017-10-24 21:22:24 +053056extern int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz,
57 unsigned int *src, struct qcom_scm_vmperm *newvm,
58 int dest_cnt);
Lina Iyer767b0232015-03-02 16:30:30 -070059extern void qcom_scm_cpu_power_down(u32 flags);
Kumar Gala4de43472015-02-04 16:30:46 -060060extern u32 qcom_scm_get_version(void);
Andy Grossa811b422017-01-16 23:24:15 -060061extern int qcom_scm_set_remote_state(u32 state, u32 id);
Rob Clarka2c680c2017-03-14 11:18:03 -040062extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
Stanimir Varbanovb182cc42017-03-14 11:18:04 -040063extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
64extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
Bjorn Andersson4e659db2017-08-14 15:46:17 -070065extern int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
66extern int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
Stanimir Varbanove1279912016-11-22 19:03:09 +020067#else
68static inline
69int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
70{
71 return -ENODEV;
72}
73static inline
74int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
75{
76 return -ENODEV;
77}
78static inline bool qcom_scm_is_available(void) { return false; }
79static inline bool qcom_scm_hdcp_available(void) { return false; }
80static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
81 u32 *resp) { return -ENODEV; }
82static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
83static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
84 size_t size) { return -ENODEV; }
85static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
86 phys_addr_t size) { return -ENODEV; }
87static inline int
88qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
89static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
90static inline void qcom_scm_cpu_power_down(u32 flags) {}
91static inline u32 qcom_scm_get_version(void) { return 0; }
Andy Grossa811b422017-01-16 23:24:15 -060092static inline u32
93qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
Rob Clarka2c680c2017-03-14 11:18:03 -040094static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
Stanimir Varbanovb182cc42017-03-14 11:18:04 -040095static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
96static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
Bjorn Andersson4e659db2017-08-14 15:46:17 -070097static inline int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) { return -ENODEV; }
98static inline int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { return -ENODEV; }
Stanimir Varbanove1279912016-11-22 19:03:09 +020099#endif
Stephen Boyd2a1eb582010-08-27 10:01:23 -0700100#endif