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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / e757a6ee3e6fc1583b12b156588e8583f798d35c / . / arch / arm / boot / dts / sama5d3.dtsi
blob: 53253713ac9b77cbc30e1acd1f697b0d78d5f255 [file] [log] [blame]
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel SAMA5D3 family SoC";
15 compatible = "atmel,sama5d3", "atmel,sama5";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 gpio4 = &pioE;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
31 i2c0 = &i2c0;
32 i2c1 = &i2c1;
33 i2c2 = &i2c2;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 };
37 cpus {
38 cpu@0 {
Lorenzo Pieralisie757a6e2013-04-18 18:31:35 +0100[diff] [blame^]39 device_type = "cpu";
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]40 compatible = "arm,cortex-a5";
Lorenzo Pieralisie757a6e2013-04-18 18:31:35 +0100[diff] [blame^]41 reg = <0x0>;
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]42 };
43 };
44
45 memory {
46 reg = <0x20000000 0x8000000>;
47 };
48
49 ahb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 apb {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 mmc0: mmc@f0000000 {
62 compatible = "atmel,hsmci";
63 reg = <0xf0000000 0x600>;
64 interrupts = <21 4 0>;
Ludovic Desroches05c1bc92013-04-16 15:03:10 +0200[diff] [blame]65 dmas = <&dma0 2 0>;
66 dma-names = "rxtx";
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
69 status = "disabled";
70 #address-cells = <1>;
71 #size-cells = <0>;
72 };
73
74 spi0: spi@f0004000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 compatible = "atmel,at91sam9x5-spi";
78 reg = <0xf0004000 0x100>;
79 interrupts = <24 4 3>;
80 cs-gpios = <&pioD 13 0
81 &pioD 14 0 /* conflicts with SCK0 and CANRX0 */
82 &pioD 15 0 /* conflicts with CTS0 and CANTX0 */
83 &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */
84 >;
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_spi0>;
87 status = "disabled";
88 };
89
90 ssc0: ssc@f0008000 {
91 compatible = "atmel,at91sam9g45-ssc";
92 reg = <0xf0008000 0x4000>;
93 interrupts = <38 4 4>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
96 status = "disabled";
97 };
98
99 can0: can@f000c000 {
100 compatible = "atmel,at91sam9x5-can";
101 reg = <0xf000c000 0x300>;
102 interrupts = <40 4 3>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_can0_rx_tx>;
105 status = "disabled";
106 };
107
108 tcb0: timer@f0010000 {
109 compatible = "atmel,at91sam9x5-tcb";
110 reg = <0xf0010000 0x100>;
111 interrupts = <26 4 0>;
112 };
113
114 i2c0: i2c@f0014000 {
115 compatible = "atmel,at91sam9x5-i2c";
116 reg = <0xf0014000 0x4000>;
117 interrupts = <18 4 6>;
Ludovic Desrochesd9a63a42013-04-16 15:03:08 +0200[diff] [blame]118 dmas = <&dma0 2 7>,
119 <&dma0 2 8>;
120 dma-names = "tx", "rx";
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c0>;
123 #address-cells = <1>;
124 #size-cells = <0>;
125 status = "disabled";
126 };
127
128 i2c1: i2c@f0018000 {
129 compatible = "atmel,at91sam9x5-i2c";
130 reg = <0xf0018000 0x4000>;
131 interrupts = <19 4 6>;
Ludovic Desrochesd9a63a42013-04-16 15:03:08 +0200[diff] [blame]132 dmas = <&dma0 2 9>,
133 <&dma0 2 10>;
134 dma-names = "tx", "rx";
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_i2c1>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 status = "disabled";
140 };
141
142 usart0: serial@f001c000 {
143 compatible = "atmel,at91sam9260-usart";
144 reg = <0xf001c000 0x100>;
145 interrupts = <12 4 5>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_usart0>;
148 status = "disabled";
149 };
150
151 usart1: serial@f0020000 {
152 compatible = "atmel,at91sam9260-usart";
153 reg = <0xf0020000 0x100>;
154 interrupts = <13 4 5>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_usart1>;
157 status = "disabled";
158 };
159
160 macb0: ethernet@f0028000 {
161 compatible = "cnds,pc302-gem", "cdns,gem";
162 reg = <0xf0028000 0x100>;
163 interrupts = <34 4 3>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
166 status = "disabled";
167 };
168
169 isi: isi@f0034000 {
170 compatible = "atmel,at91sam9g45-isi";
171 reg = <0xf0034000 0x4000>;
172 interrupts = <37 4 5>;
173 status = "disabled";
174 };
175
176 mmc1: mmc@f8000000 {
177 compatible = "atmel,hsmci";
178 reg = <0xf8000000 0x600>;
179 interrupts = <22 4 0>;
Ludovic Desroches05c1bc92013-04-16 15:03:10 +0200[diff] [blame]180 dmas = <&dma1 2 0>;
181 dma-names = "rxtx";
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
184 status = "disabled";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188
189 mmc2: mmc@f8004000 {
190 compatible = "atmel,hsmci";
191 reg = <0xf8004000 0x600>;
192 interrupts = <23 4 0>;
Ludovic Desroches05c1bc92013-04-16 15:03:10 +0200[diff] [blame]193 dmas = <&dma1 2 1>;
194 dma-names = "rxtx";
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
197 status = "disabled";
198 #address-cells = <1>;
199 #size-cells = <0>;
200 };
201
202 spi1: spi@f8008000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "atmel,at91sam9x5-spi";
206 reg = <0xf8008000 0x100>;
207 interrupts = <25 4 3>;
208 cs-gpios = <&pioC 25 0
209 &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */
210 &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */
211 &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */
212 >;
213 pinctrl-names = "default";
214 pinctrl-0 = <&pinctrl_spi1>;
215 status = "disabled";
216 };
217
218 ssc1: ssc@f800c000 {
219 compatible = "atmel,at91sam9g45-ssc";
220 reg = <0xf800c000 0x4000>;
221 interrupts = <39 4 4>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
224 status = "disabled";
225 };
226
227 can1: can@f8010000 {
228 compatible = "atmel,at91sam9x5-can";
229 reg = <0xf8010000 0x300>;
230 interrupts = <41 4 3>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_can1_rx_tx>;
233 };
234
235 tcb1: timer@f8014000 {
236 compatible = "atmel,at91sam9x5-tcb";
237 reg = <0xf8014000 0x100>;
238 interrupts = <27 4 0>;
239 };
240
241 adc0: adc@f8018000 {
242 compatible = "atmel,at91sam9260-adc";
243 reg = <0xf8018000 0x100>;
244 interrupts = <29 4 5>;
245 pinctrl-names = "default";
246 pinctrl-0 = <
247 &pinctrl_adc0_adtrg
248 &pinctrl_adc0_ad0
249 &pinctrl_adc0_ad1
250 &pinctrl_adc0_ad2
251 &pinctrl_adc0_ad3
252 &pinctrl_adc0_ad4
253 &pinctrl_adc0_ad5
254 &pinctrl_adc0_ad6
255 &pinctrl_adc0_ad7
256 &pinctrl_adc0_ad8
257 &pinctrl_adc0_ad9
258 &pinctrl_adc0_ad10
259 &pinctrl_adc0_ad11
260 >;
261 atmel,adc-channel-base = <0x50>;
262 atmel,adc-channels-used = <0xfff>;
263 atmel,adc-drdy-mask = <0x1000000>;
264 atmel,adc-num-channels = <12>;
265 atmel,adc-startup-time = <40>;
266 atmel,adc-status-register = <0x30>;
267 atmel,adc-trigger-register = <0xc0>;
268 atmel,adc-use-external;
269 atmel,adc-vref = <3000>;
270 atmel,adc-res = <10 12>;
271 atmel,adc-res-names = "lowres", "highres";
272 status = "disabled";
273
274 trigger@0 {
275 trigger-name = "external-rising";
276 trigger-value = <0x1>;
277 trigger-external;
278 };
279 trigger@1 {
280 trigger-name = "external-falling";
281 trigger-value = <0x2>;
282 trigger-external;
283 };
284 trigger@2 {
285 trigger-name = "external-any";
286 trigger-value = <0x3>;
287 trigger-external;
288 };
289 trigger@3 {
290 trigger-name = "continuous";
291 trigger-value = <0x6>;
292 };
293 };
294
295 tsadcc: tsadcc@f8018000 {
296 compatible = "atmel,at91sam9x5-tsadcc";
297 reg = <0xf8018000 0x4000>;
298 interrupts = <29 4 5>;
299 atmel,tsadcc_clock = <300000>;
300 atmel,filtering_average = <0x03>;
301 atmel,pendet_debounce = <0x08>;
302 atmel,pendet_sensitivity = <0x02>;
303 atmel,ts_sample_hold_time = <0x0a>;
304 status = "disabled";
305 };
306
307 i2c2: i2c@f801c000 {
308 compatible = "atmel,at91sam9x5-i2c";
309 reg = <0xf801c000 0x4000>;
310 interrupts = <20 4 6>;
Ludovic Desrochesd9a63a42013-04-16 15:03:08 +0200[diff] [blame]311 dmas = <&dma1 2 11>,
312 <&dma1 2 12>;
313 dma-names = "tx", "rx";
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]314 #address-cells = <1>;
315 #size-cells = <0>;
316 status = "disabled";
317 };
318
319 usart2: serial@f8020000 {
320 compatible = "atmel,at91sam9260-usart";
321 reg = <0xf8020000 0x100>;
322 interrupts = <14 4 5>;
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_usart2>;
325 status = "disabled";
326 };
327
328 usart3: serial@f8024000 {
329 compatible = "atmel,at91sam9260-usart";
330 reg = <0xf8024000 0x100>;
331 interrupts = <15 4 5>;
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_usart3>;
334 status = "disabled";
335 };
336
337 macb1: ethernet@f802c000 {
338 compatible = "cdns,at32ap7000-macb", "cdns,macb";
339 reg = <0xf802c000 0x100>;
340 interrupts = <35 4 3>;
341 pinctrl-names = "default";
342 pinctrl-0 = <&pinctrl_macb1_rmii>;
343 status = "disabled";
344 };
345
346 sha@f8034000 {
347 compatible = "atmel,sam9g46-sha";
348 reg = <0xf8034000 0x100>;
349 interrupts = <42 4 0>;
350 };
351
352 aes@f8038000 {
353 compatible = "atmel,sam9g46-aes";
354 reg = <0xf8038000 0x100>;
355 interrupts = <43 4 0>;
356 };
357
358 tdes@f803c000 {
359 compatible = "atmel,sam9g46-tdes";
360 reg = <0xf803c000 0x100>;
361 interrupts = <44 4 0>;
362 };
363
364 dma0: dma-controller@ffffe600 {
365 compatible = "atmel,at91sam9g45-dma";
366 reg = <0xffffe600 0x200>;
367 interrupts = <30 4 0>;
Ludovic Desroches980ce7d2013-04-16 15:03:06 +0200[diff] [blame]368 #dma-cells = <2>;
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]369 };
370
371 dma1: dma-controller@ffffe800 {
372 compatible = "atmel,at91sam9g45-dma";
373 reg = <0xffffe800 0x200>;
374 interrupts = <31 4 0>;
Ludovic Desroches980ce7d2013-04-16 15:03:06 +0200[diff] [blame]375 #dma-cells = <2>;
Ludovic Desroches655ff2662013-03-22 13:24:13 +0000[diff] [blame]376 };
377
378 ramc0: ramc@ffffea00 {
379 compatible = "atmel,at91sam9g45-ddramc";
380 reg = <0xffffea00 0x200>;
381 };
382
383 dbgu: serial@ffffee00 {
384 compatible = "atmel,at91sam9260-usart";
385 reg = <0xffffee00 0x200>;
386 interrupts = <2 4 7>;
387 pinctrl-names = "default";
388 pinctrl-0 = <&pinctrl_dbgu>;
389 status = "disabled";
390 };
391
392 aic: interrupt-controller@fffff000 {
393 #interrupt-cells = <3>;
394 compatible = "atmel,sama5d3-aic";
395 interrupt-controller;
396 reg = <0xfffff000 0x200>;
397 atmel,external-irqs = <47>;
398 };
399
400 pinctrl@fffff200 {
401 #address-cells = <1>;
402 #size-cells = <1>;
403 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
404 ranges = <0xfffff200 0xfffff200 0xa00>;
405 atmel,mux-mask = <
406 /* A B C */
407 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
408 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
409 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
410 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
411 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
412 >;
413
414 /* shared pinctrl settings */
415 adc0 {
416 pinctrl_adc0_adtrg: adc0_adtrg {
417 atmel,pins =
418 <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
419 };
420 pinctrl_adc0_ad0: adc0_ad0 {
421 atmel,pins =
422 <3 20 0x1 0x0>; /* PD20 periph A AD0 */
423 };
424 pinctrl_adc0_ad1: adc0_ad1 {
425 atmel,pins =
426 <3 21 0x1 0x0>; /* PD21 periph A AD1 */
427 };
428 pinctrl_adc0_ad2: adc0_ad2 {
429 atmel,pins =
430 <3 22 0x1 0x0>; /* PD22 periph A AD2 */
431 };
432 pinctrl_adc0_ad3: adc0_ad3 {
433 atmel,pins =
434 <3 23 0x1 0x0>; /* PD23 periph A AD3 */
435 };
436 pinctrl_adc0_ad4: adc0_ad4 {
437 atmel,pins =
438 <3 24 0x1 0x0>; /* PD24 periph A AD4 */
439 };
440 pinctrl_adc0_ad5: adc0_ad5 {
441 atmel,pins =
442 <3 25 0x1 0x0>; /* PD25 periph A AD5 */
443 };
444 pinctrl_adc0_ad6: adc0_ad6 {
445 atmel,pins =
446 <3 26 0x1 0x0>; /* PD26 periph A AD6 */
447 };
448 pinctrl_adc0_ad7: adc0_ad7 {
449 atmel,pins =
450 <3 27 0x1 0x0>; /* PD27 periph A AD7 */
451 };
452 pinctrl_adc0_ad8: adc0_ad8 {
453 atmel,pins =
454 <3 28 0x1 0x0>; /* PD28 periph A AD8 */
455 };
456 pinctrl_adc0_ad9: adc0_ad9 {
457 atmel,pins =
458 <3 29 0x1 0x0>; /* PD29 periph A AD9 */
459 };
460 pinctrl_adc0_ad10: adc0_ad10 {
461 atmel,pins =
462 <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
463 };
464 pinctrl_adc0_ad11: adc0_ad11 {
465 atmel,pins =
466 <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
467 };
468 };
469
470 can0 {
471 pinctrl_can0_rx_tx: can0_rx_tx {
472 atmel,pins =
473 <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
474 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
475 };
476 };
477
478 can1 {
479 pinctrl_can1_rx_tx: can1_rx_tx {
480 atmel,pins =
481 <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */
482 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
483 };
484 };
485
486 dbgu {
487 pinctrl_dbgu: dbgu-0 {
488 atmel,pins =
489 <1 30 0x1 0x0 /* PB30 periph A */
490 1 31 0x1 0x1>; /* PB31 periph A with pullup */
491 };
492 };
493
494 i2c0 {
495 pinctrl_i2c0: i2c0-0 {
496 atmel,pins =
497 <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
498 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
499 };
500 };
501
502 i2c1 {
503 pinctrl_i2c1: i2c1-0 {
504 atmel,pins =
505 <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
506 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
507 };
508 };
509
510 isi {
511 pinctrl_isi: isi-0 {
512 atmel,pins =
513 <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
514 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
515 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
516 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
517 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
518 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
519 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
520 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
521 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
522 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
523 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
524 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
525 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
526 };
527 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
528 atmel,pins =
529 <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
530 };
531 };
532
533 lcd {
534 pinctrl_lcd: lcd-0 {
535 atmel,pins =
536 <0 24 0x1 0x0 /* PA24 periph A LCDPWM */
537 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */
538 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */
539 0 25 0x1 0x0 /* PA25 periph A LCDDISP */
540 0 29 0x1 0x0 /* PA29 periph A LCDDEN */
541 0 28 0x1 0x0 /* PA28 periph A LCDPCK */
542 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */
543 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */
544 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */
545 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */
546 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */
547 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */
548 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */
549 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */
550 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */
551 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */
552 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */
553 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */
554 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */
555 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */
556 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */
557 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */
558 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */
559 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */
560 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */
561 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */
562 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */
563 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */
564 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */
565 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
566 };
567 };
568
569 macb0 {
570 pinctrl_macb0_data_rgmii: macb0_data_rgmii {
571 atmel,pins =
572 <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */
573 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */
574 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */
575 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */
576 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */
577 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */
578 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */
579 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */
580 };
581 pinctrl_macb0_data_gmii: macb0_data_gmii {
582 atmel,pins =
583 <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */
584 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
585 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
586 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
587 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
588 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */
589 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */
590 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
591 };
592 pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
593 atmel,pins =
594 <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */
595 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
596 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
597 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
598 1 16 0x1 0x0 /* PB16 periph A GMDC */
599 1 17 0x1 0x0 /* PB17 periph A GMDIO */
600 1 18 0x1 0x0>; /* PB18 periph A G125CK */
601 };
602 pinctrl_macb0_signal_gmii: macb0_signal_gmii {
603 atmel,pins =
604 <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */
605 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */
606 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */
607 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */
608 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */
609 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */
610 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */
611 1 16 0x1 0x0 /* PB16 periph A GMDC */
612 1 17 0x1 0x0 /* PB17 periph A GMDIO */
613 1 27 0x2 0x0>; /* PB27 periph B G125CKO */
614 };
615
616 };
617
618 macb1 {
619 pinctrl_macb1_rmii: macb1_rmii-0 {
620 atmel,pins =
621 <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */
622 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */
623 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */
624 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */
625 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */
626 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */
627 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */
628 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */
629 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */
630 2 9 0x1 0x0>; /* PC9 periph A EMDIO */
631 };
632 };
633
634 mmc0 {
635 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
636 atmel,pins =
637 <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */
638 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */
639 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */
640 };
641 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
642 atmel,pins =
643 <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */
644 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */
645 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */
646 };
647 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
648 atmel,pins =
649 <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
650 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
651 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
652 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
653 };
654 };
655
656 mmc1 {
657 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
658 atmel,pins =
659 <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */
660 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
661 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
662 };
663 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
664 atmel,pins =
665 <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
666 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
667 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
668 };
669 };
670
671 mmc2 {
672 pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
673 atmel,pins =
674 <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */
675 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */
676 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
677 };
678 pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
679 atmel,pins =
680 <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
681 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
682 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
683 };
684 };
685
686 nand0 {
687 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
688 atmel,pins =
689 <4 21 0x1 0x1 /* PE21 periph A with pullup */
690 4 22 0x1 0x1>; /* PE22 periph A with pullup */
691 };
692 };
693
694 pioA: gpio@fffff200 {
695 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
696 reg = <0xfffff200 0x100>;
697 interrupts = <6 4 1>;
698 #gpio-cells = <2>;
699 gpio-controller;
700 interrupt-controller;
701 #interrupt-cells = <2>;
702 };
703
704 pioB: gpio@fffff400 {
705 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
706 reg = <0xfffff400 0x100>;
707 interrupts = <7 4 1>;
708 #gpio-cells = <2>;
709 gpio-controller;
710 interrupt-controller;
711 #interrupt-cells = <2>;
712 };
713
714 pioC: gpio@fffff600 {
715 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
716 reg = <0xfffff600 0x100>;
717 interrupts = <8 4 1>;
718 #gpio-cells = <2>;
719 gpio-controller;
720 interrupt-controller;
721 #interrupt-cells = <2>;
722 };
723
724 pioD: gpio@fffff800 {
725 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
726 reg = <0xfffff800 0x100>;
727 interrupts = <9 4 1>;
728 #gpio-cells = <2>;
729 gpio-controller;
730 interrupt-controller;
731 #interrupt-cells = <2>;
732 };
733
734 pioE: gpio@fffffa00 {
735 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
736 reg = <0xfffffa00 0x100>;
737 interrupts = <10 4 1>;
738 #gpio-cells = <2>;
739 gpio-controller;
740 interrupt-controller;
741 #interrupt-cells = <2>;
742 };
743
744 spi0 {
745 pinctrl_spi0: spi0-0 {
746 atmel,pins =
747 <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */
748 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */
749 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */
750 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
751 };
752 };
753
754 spi1 {
755 pinctrl_spi1: spi1-0 {
756 atmel,pins =
757 <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */
758 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */
759 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */
760 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
761 };
762 };
763
764 ssc0 {
765 pinctrl_ssc0_tx: ssc0_tx {
766 atmel,pins =
767 <2 16 0x1 0x0 /* PC16 periph A TK0 */
768 2 17 0x1 0x0 /* PC17 periph A TF0 */
769 2 18 0x1 0x0>; /* PC18 periph A TD0 */
770 };
771
772 pinctrl_ssc0_rx: ssc0_rx {
773 atmel,pins =
774 <2 19 0x1 0x0 /* PC19 periph A RK0 */
775 2 20 0x1 0x0 /* PC20 periph A RF0 */
776 2 21 0x1 0x0>; /* PC21 periph A RD0 */
777 };
778 };
779
780 ssc1 {
781 pinctrl_ssc1_tx: ssc1_tx {
782 atmel,pins =
783 <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */
784 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */
785 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */
786 };
787
788 pinctrl_ssc1_rx: ssc1_rx {
789 atmel,pins =
790 <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */
791 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */
792 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
793 };
794 };
795
796 uart0 {
797 pinctrl_uart0: uart0-0 {
798 atmel,pins =
799 <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
800 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
801 };
802 };
803
804 uart1 {
805 pinctrl_uart1: uart1-0 {
806 atmel,pins =
807 <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
808 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
809 };
810 };
811
812 usart0 {
813 pinctrl_usart0: usart0-0 {
814 atmel,pins =
815 <3 17 0x1 0x0 /* PD17 periph A */
816 3 18 0x1 0x1>; /* PD18 periph A with pullup */
817 };
818
819 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
820 atmel,pins =
821 <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
822 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
823 };
824 };
825
826 usart1 {
827 pinctrl_usart1: usart1-0 {
828 atmel,pins =
829 <1 28 0x1 0x0 /* PB28 periph A */
830 1 29 0x1 0x1>; /* PB29 periph A with pullup */
831 };
832
833 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
834 atmel,pins =
835 <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */
836 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
837 };
838 };
839
840 usart2 {
841 pinctrl_usart2: usart2-0 {
842 atmel,pins =
843 <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */
844 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
845 };
846
847 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
848 atmel,pins =
849 <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */
850 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
851 };
852 };
853
854 usart3 {
855 pinctrl_usart3: usart3-0 {
856 atmel,pins =
857 <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */
858 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
859 };
860
861 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
862 atmel,pins =
863 <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */
864 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
865 };
866 };
867 };
868
869 pmc: pmc@fffffc00 {
870 compatible = "atmel,at91rm9200-pmc";
871 reg = <0xfffffc00 0x120>;
872 };
873
874 rstc@fffffe00 {
875 compatible = "atmel,at91sam9g45-rstc";
876 reg = <0xfffffe00 0x10>;
877 };
878
879 pit: timer@fffffe30 {
880 compatible = "atmel,at91sam9260-pit";
881 reg = <0xfffffe30 0xf>;
882 interrupts = <3 4 5>;
883 };
884
885 watchdog@fffffe40 {
886 compatible = "atmel,at91sam9260-wdt";
887 reg = <0xfffffe40 0x10>;
888 status = "disabled";
889 };
890
891 rtc@fffffeb0 {
892 compatible = "atmel,at91rm9200-rtc";
893 reg = <0xfffffeb0 0x30>;
894 interrupts = <1 4 7>;
895 };
896 };
897
898 usb0: gadget@00500000 {
899 #address-cells = <1>;
900 #size-cells = <0>;
901 compatible = "atmel,at91sam9rl-udc";
902 reg = <0x00500000 0x100000
903 0xf8030000 0x4000>;
904 interrupts = <33 4 2>;
905 status = "disabled";
906
907 ep0 {
908 reg = <0>;
909 atmel,fifo-size = <64>;
910 atmel,nb-banks = <1>;
911 };
912
913 ep1 {
914 reg = <1>;
915 atmel,fifo-size = <1024>;
916 atmel,nb-banks = <3>;
917 atmel,can-dma;
918 atmel,can-isoc;
919 };
920
921 ep2 {
922 reg = <2>;
923 atmel,fifo-size = <1024>;
924 atmel,nb-banks = <3>;
925 atmel,can-dma;
926 atmel,can-isoc;
927 };
928
929 ep3 {
930 reg = <3>;
931 atmel,fifo-size = <1024>;
932 atmel,nb-banks = <2>;
933 atmel,can-dma;
934 };
935
936 ep4 {
937 reg = <4>;
938 atmel,fifo-size = <1024>;
939 atmel,nb-banks = <2>;
940 atmel,can-dma;
941 };
942
943 ep5 {
944 reg = <5>;
945 atmel,fifo-size = <1024>;
946 atmel,nb-banks = <2>;
947 atmel,can-dma;
948 };
949
950 ep6 {
951 reg = <6>;
952 atmel,fifo-size = <1024>;
953 atmel,nb-banks = <2>;
954 atmel,can-dma;
955 };
956
957 ep7 {
958 reg = <7>;
959 atmel,fifo-size = <1024>;
960 atmel,nb-banks = <2>;
961 atmel,can-dma;
962 };
963
964 ep8 {
965 reg = <8>;
966 atmel,fifo-size = <1024>;
967 atmel,nb-banks = <2>;
968 };
969
970 ep9 {
971 reg = <9>;
972 atmel,fifo-size = <1024>;
973 atmel,nb-banks = <2>;
974 };
975
976 ep10 {
977 reg = <10>;
978 atmel,fifo-size = <1024>;
979 atmel,nb-banks = <2>;
980 };
981
982 ep11 {
983 reg = <11>;
984 atmel,fifo-size = <1024>;
985 atmel,nb-banks = <2>;
986 };
987
988 ep12 {
989 reg = <12>;
990 atmel,fifo-size = <1024>;
991 atmel,nb-banks = <2>;
992 };
993
994 ep13 {
995 reg = <13>;
996 atmel,fifo-size = <1024>;
997 atmel,nb-banks = <2>;
998 };
999
1000 ep14 {
1001 reg = <14>;
1002 atmel,fifo-size = <1024>;
1003 atmel,nb-banks = <2>;
1004 };
1005
1006 ep15 {
1007 reg = <15>;
1008 atmel,fifo-size = <1024>;
1009 atmel,nb-banks = <2>;
1010 };
1011 };
1012
1013 usb1: ohci@00600000 {
1014 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1015 reg = <0x00600000 0x100000>;
1016 interrupts = <32 4 2>;
1017 status = "disabled";
1018 };
1019
1020 usb2: ehci@00700000 {
1021 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1022 reg = <0x00700000 0x100000>;
1023 interrupts = <32 4 2>;
1024 status = "disabled";
1025 };
1026
1027 nand0: nand@60000000 {
1028 compatible = "atmel,at91rm9200-nand";
1029 #address-cells = <1>;
1030 #size-cells = <1>;
1031 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1032 0xffffc070 0x00000490 /* SMC PMECC regs */
1033 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1034 0x00100000 0x00100000 /* ROM code */
1035 0x70000000 0x10000000 /* NFC Command Registers */
1036 0xffffc000 0x00000070 /* NFC HSMC regs */
1037 0x00200000 0x00100000 /* NFC SRAM banks */
1038 >;
1039 interrupts = <5 4 6>;
1040 atmel,nand-addr-offset = <21>;
1041 atmel,nand-cmd-offset = <22>;
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1044 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>;
1045 status = "disabled";
1046 };
1047 };
1048};