Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_FUTEX_H |
| 17 | #define __ASM_FUTEX_H |
| 18 | |
| 19 | #ifdef __KERNEL__ |
| 20 | |
| 21 | #include <linux/futex.h> |
| 22 | #include <linux/uaccess.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 23 | |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 24 | #include <asm/errno.h> |
| 25 | |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 26 | #define FUTEX_MAX_LOOPS 128 /* What's the largest number you can think of? */ |
| 27 | |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 28 | #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 29 | do { \ |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 30 | unsigned int loops = FUTEX_MAX_LOOPS; \ |
| 31 | \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 32 | uaccess_enable(); \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 33 | asm volatile( \ |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 34 | " prfm pstl1strm, %2\n" \ |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 35 | "1: ldxr %w1, %2\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 36 | insn "\n" \ |
Will Deacon | 045afc2 | 2019-04-08 12:45:09 +0100 | [diff] [blame] | 37 | "2: stlxr %w0, %w3, %2\n" \ |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 38 | " cbz %w0, 3f\n" \ |
| 39 | " sub %w4, %w4, %w0\n" \ |
| 40 | " cbnz %w4, 1b\n" \ |
| 41 | " mov %w0, %w7\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 42 | "3:\n" \ |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 43 | " dmb ish\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 44 | " .pushsection .fixup,\"ax\"\n" \ |
Will Deacon | 4da7a56 | 2013-11-06 19:31:24 +0000 | [diff] [blame] | 45 | " .align 2\n" \ |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 46 | "4: mov %w0, %w6\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 47 | " b 3b\n" \ |
| 48 | " .popsection\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 49 | _ASM_EXTABLE(1b, 4b) \ |
| 50 | _ASM_EXTABLE(2b, 4b) \ |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 51 | : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp), \ |
| 52 | "+r" (loops) \ |
| 53 | : "r" (oparg), "Ir" (-EFAULT), "Ir" (-EAGAIN) \ |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 54 | : "memory"); \ |
| 55 | uaccess_disable(); \ |
| 56 | } while (0) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 57 | |
| 58 | static inline int |
Will Deacon | 91b2d34 | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 59 | arch_futex_atomic_op_inuser(int op, int oparg, int *oval, u32 __user *_uaddr) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 60 | { |
Nathan Chancellor | ff8acf9 | 2019-04-17 00:21:21 -0700 | [diff] [blame] | 61 | int oldval = 0, ret, tmp; |
Will Deacon | 91b2d34 | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 62 | u32 __user *uaddr = __uaccess_mask_ptr(_uaddr); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 63 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 64 | pagefault_disable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 65 | |
| 66 | switch (op) { |
| 67 | case FUTEX_OP_SET: |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 68 | __futex_atomic_op("mov %w3, %w5", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 69 | ret, oldval, uaddr, tmp, oparg); |
| 70 | break; |
| 71 | case FUTEX_OP_ADD: |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 72 | __futex_atomic_op("add %w3, %w1, %w5", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 73 | ret, oldval, uaddr, tmp, oparg); |
| 74 | break; |
| 75 | case FUTEX_OP_OR: |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 76 | __futex_atomic_op("orr %w3, %w1, %w5", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 77 | ret, oldval, uaddr, tmp, oparg); |
| 78 | break; |
| 79 | case FUTEX_OP_ANDN: |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 80 | __futex_atomic_op("and %w3, %w1, %w5", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 81 | ret, oldval, uaddr, tmp, ~oparg); |
| 82 | break; |
| 83 | case FUTEX_OP_XOR: |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 84 | __futex_atomic_op("eor %w3, %w1, %w5", |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 85 | ret, oldval, uaddr, tmp, oparg); |
| 86 | break; |
| 87 | default: |
| 88 | ret = -ENOSYS; |
| 89 | } |
| 90 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 91 | pagefault_enable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 92 | |
Jiri Slaby | 30d6e0a | 2017-08-24 09:31:05 +0200 | [diff] [blame] | 93 | if (!ret) |
| 94 | *oval = oldval; |
| 95 | |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 96 | return ret; |
| 97 | } |
| 98 | |
| 99 | static inline int |
Will Deacon | 91b2d34 | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 100 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *_uaddr, |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 101 | u32 oldval, u32 newval) |
| 102 | { |
| 103 | int ret = 0; |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 104 | unsigned int loops = FUTEX_MAX_LOOPS; |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 105 | u32 val, tmp; |
Will Deacon | 91b2d34 | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 106 | u32 __user *uaddr; |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 107 | |
Linus Torvalds | 96d4f26 | 2019-01-03 18:57:57 -0800 | [diff] [blame] | 108 | if (!access_ok(_uaddr, sizeof(u32))) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 109 | return -EFAULT; |
| 110 | |
Will Deacon | 91b2d34 | 2018-02-05 15:34:24 +0000 | [diff] [blame] | 111 | uaddr = __uaccess_mask_ptr(_uaddr); |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 112 | uaccess_enable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 113 | asm volatile("// futex_atomic_cmpxchg_inatomic\n" |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 114 | " prfm pstl1strm, %2\n" |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 115 | "1: ldxr %w1, %2\n" |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 116 | " sub %w3, %w1, %w5\n" |
| 117 | " cbnz %w3, 4f\n" |
| 118 | "2: stlxr %w3, %w6, %2\n" |
| 119 | " cbz %w3, 3f\n" |
| 120 | " sub %w4, %w4, %w3\n" |
| 121 | " cbnz %w4, 1b\n" |
| 122 | " mov %w0, %w8\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 123 | "3:\n" |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 124 | " dmb ish\n" |
| 125 | "4:\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 126 | " .pushsection .fixup,\"ax\"\n" |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 127 | "5: mov %w0, %w7\n" |
| 128 | " b 4b\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 129 | " .popsection\n" |
Will Deacon | 03110a5 | 2019-04-08 14:23:17 +0100 | [diff] [blame] | 130 | _ASM_EXTABLE(1b, 5b) |
| 131 | _ASM_EXTABLE(2b, 5b) |
| 132 | : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp), "+r" (loops) |
| 133 | : "r" (oldval), "r" (newval), "Ir" (-EFAULT), "Ir" (-EAGAIN) |
Will Deacon | 95c4189 | 2014-02-04 12:29:13 +0000 | [diff] [blame] | 134 | : "memory"); |
Catalin Marinas | bd38967 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 135 | uaccess_disable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 136 | |
Will Deacon | 8e4e0ac | 2019-04-10 11:49:11 +0100 | [diff] [blame] | 137 | if (!ret) |
| 138 | *uval = val; |
| 139 | |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 140 | return ret; |
| 141 | } |
| 142 | |
| 143 | #endif /* __KERNEL__ */ |
| 144 | #endif /* __ASM_FUTEX_H */ |