Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / e66796b9bb87d2c48f68e5eb27dcfbc4c26c18d4 / . / arch / arm / boot / dts / r8a7792.dtsi
blob: b6e34b431a51c0b8bdd96c1063d8aca7f5b26cd9 [file] [log] [blame]
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]1/*
2 * Device Tree Source for the r8a7792 SoC
3 *
4 * Copyright (C) 2016 Cogent Embedded Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/r8a7792-clock.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/power/r8a7792-sysc.h>
15
16/ {
17 compatible = "renesas,r8a7792";
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a15";
28 reg = <0>;
29 clock-frequency = <1000000000>;
30 clocks = <&cpg_clocks R8A7792_CLK_Z>;
31 power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
32 next-level-cache = <&L2_CA15>;
33 };
34
35 L2_CA15: cache-controller@0 {
36 compatible = "cache";
37 reg = <0>;
38 cache-unified;
39 cache-level = <2>;
40 power-domains = <&sysc R8A7792_PD_CA15_SCU>;
41 };
42 };
43
44 soc {
45 compatible = "simple-bus";
46 interrupt-parent = <&gic>;
47
48 #address-cells = <2>;
49 #size-cells = <2>;
50 ranges;
51
52 gic: interrupt-controller@f1001000 {
53 compatible = "arm,gic-400";
54 #interrupt-cells = <3>;
55 interrupt-controller;
56 reg = <0 0xf1001000 0 0x1000>,
57 <0 0xf1002000 0 0x1000>,
58 <0 0xf1004000 0 0x2000>,
59 <0 0xf1006000 0 0x2000>;
60 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
61 IRQ_TYPE_LEVEL_HIGH)>;
62 };
63
64 timer {
65 compatible = "arm,armv7-timer";
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
67 IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
69 IRQ_TYPE_LEVEL_LOW)>,
70 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
71 IRQ_TYPE_LEVEL_LOW)>,
72 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
73 IRQ_TYPE_LEVEL_LOW)>;
74 };
75
76 sysc: system-controller@e6180000 {
77 compatible = "renesas,r8a7792-sysc";
78 reg = <0 0xe6180000 0 0x0200>;
79 #power-domain-cells = <1>;
80 };
81
Sergei Shtylyovfdf8ec02016-06-13 00:08:18 +0300[diff] [blame]82 dmac0: dma-controller@e6700000 {
83 compatible = "renesas,dmac-r8a7792",
84 "renesas,rcar-dmac";
85 reg = <0 0xe6700000 0 0x20000>;
86 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
87 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
88 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
89 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
90 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
91 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
92 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
93 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
94 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
95 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
96 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
97 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
98 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
99 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
100 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
101 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
102 interrupt-names = "error",
103 "ch0", "ch1", "ch2", "ch3",
104 "ch4", "ch5", "ch6", "ch7",
105 "ch8", "ch9", "ch10", "ch11",
106 "ch12", "ch13", "ch14";
107 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
108 clock-names = "fck";
109 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
110 #dma-cells = <1>;
111 dma-channels = <15>;
112 };
113
114 dmac1: dma-controller@e6720000 {
115 compatible = "renesas,dmac-r8a7792",
116 "renesas,rcar-dmac";
117 reg = <0 0xe6720000 0 0x20000>;
118 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
123 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
124 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
125 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
126 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
127 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
128 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
129 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
130 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
131 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
132 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
133 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-names = "error",
135 "ch0", "ch1", "ch2", "ch3",
136 "ch4", "ch5", "ch6", "ch7",
137 "ch8", "ch9", "ch10", "ch11",
138 "ch12", "ch13", "ch14";
139 clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
140 clock-names = "fck";
141 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
142 #dma-cells = <1>;
143 dma-channels = <15>;
144 };
145
Sergei Shtylyove66796b2016-06-13 00:09:42 +0300[diff] [blame^]146 scif0: serial@e6e60000 {
147 compatible = "renesas,scif-r8a7792",
148 "renesas,rcar-gen2-scif", "renesas,scif";
149 reg = <0 0xe6e60000 0 64>;
150 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
152 <&scif_clk>;
153 clock-names = "fck", "brg_int", "scif_clk";
154 dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
155 <&dmac1 0x29>, <&dmac1 0x2a>;
156 dma-names = "tx", "rx", "tx", "rx";
157 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
158 status = "disabled";
159 };
160
161 scif1: serial@e6e68000 {
162 compatible = "renesas,scif-r8a7792",
163 "renesas,rcar-gen2-scif", "renesas,scif";
164 reg = <0 0xe6e68000 0 64>;
165 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
167 <&scif_clk>;
168 clock-names = "fck", "brg_int", "scif_clk";
169 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
170 <&dmac1 0x2d>, <&dmac1 0x2e>;
171 dma-names = "tx", "rx", "tx", "rx";
172 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
173 status = "disabled";
174 };
175
176 scif2: serial@e6e58000 {
177 compatible = "renesas,scif-r8a7792",
178 "renesas,rcar-gen2-scif", "renesas,scif";
179 reg = <0 0xe6e58000 0 64>;
180 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
182 <&scif_clk>;
183 clock-names = "fck", "brg_int", "scif_clk";
184 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
185 <&dmac1 0x2b>, <&dmac1 0x2c>;
186 dma-names = "tx", "rx", "tx", "rx";
187 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
188 status = "disabled";
189 };
190
191 scif3: serial@e6ea8000 {
192 compatible = "renesas,scif-r8a7792",
193 "renesas,rcar-gen2-scif", "renesas,scif";
194 reg = <0 0xe6ea8000 0 64>;
195 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
197 <&scif_clk>;
198 clock-names = "fck", "brg_int", "scif_clk";
199 dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
200 <&dmac1 0x2f>, <&dmac1 0x30>;
201 dma-names = "tx", "rx", "tx", "rx";
202 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
203 status = "disabled";
204 };
205
206 hscif0: serial@e62c0000 {
207 compatible = "renesas,hscif-r8a7792",
208 "renesas,rcar-gen2-hscif", "renesas,hscif";
209 reg = <0 0xe62c0000 0 96>;
210 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
212 <&scif_clk>;
213 clock-names = "fck", "brg_int", "scif_clk";
214 dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
215 <&dmac1 0x39>, <&dmac1 0x3a>;
216 dma-names = "tx", "rx", "tx", "rx";
217 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
218 status = "disabled";
219 };
220
221 hscif1: serial@e62c8000 {
222 compatible = "renesas,hscif-r8a7792",
223 "renesas,rcar-gen2-hscif", "renesas,hscif";
224 reg = <0 0xe62c8000 0 96>;
225 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
227 <&scif_clk>;
228 clock-names = "fck", "brg_int", "scif_clk";
229 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
230 <&dmac1 0x4d>, <&dmac1 0x4e>;
231 dma-names = "tx", "rx", "tx", "rx";
232 power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
233 status = "disabled";
234 };
235
Sergei Shtylyov7c4163a2016-06-13 00:06:52 +0300[diff] [blame]236 /* Special CPG clocks */
237 cpg_clocks: cpg_clocks@e6150000 {
238 compatible = "renesas,r8a7792-cpg-clocks",
239 "renesas,rcar-gen2-cpg-clocks";
240 reg = <0 0xe6150000 0 0x1000>;
241 clocks = <&extal_clk>;
242 #clock-cells = <1>;
243 clock-output-names = "main", "pll0", "pll1", "pll3",
244 "lb", "qspi", "z", "adsp";
245 #power-domain-cells = <0>;
246 };
247
248 /* Fixed factor clocks */
249 zs_clk: zs {
250 compatible = "fixed-factor-clock";
251 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
252 #clock-cells = <0>;
253 clock-div = <6>;
254 clock-mult = <1>;
255 };
256 p_clk: p {
257 compatible = "fixed-factor-clock";
258 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
259 #clock-cells = <0>;
260 clock-div = <24>;
261 clock-mult = <1>;
262 };
263 cp_clk: cp {
264 compatible = "fixed-factor-clock";
265 clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
266 #clock-cells = <0>;
267 clock-div = <48>;
268 clock-mult = <1>;
269 };
270
271 /* Gate clocks */
272 mstp2_clks: mstp2_clks@e6150138 {
273 compatible = "renesas,r8a7792-mstp-clocks",
274 "renesas,cpg-mstp-clocks";
275 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
276 clocks = <&zs_clk>, <&zs_clk>;
277 #clock-cells = <1>;
278 clock-indices = <
279 R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
280 >;
281 clock-output-names = "sys-dmac1", "sys-dmac0";
282 };
283 mstp4_clks: mstp4_clks@e6150140 {
284 compatible = "renesas,r8a7792-mstp-clocks",
285 "renesas,cpg-mstp-clocks";
286 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
287 clocks = <&cp_clk>;
288 #clock-cells = <1>;
289 clock-indices = <R8A7792_CLK_IRQC>;
290 clock-output-names = "irqc";
291 };
292 mstp7_clks: mstp7_clks@e615014c {
293 compatible = "renesas,r8a7792-mstp-clocks",
294 "renesas,cpg-mstp-clocks";
295 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
296 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
297 <&p_clk>, <&p_clk>;
298 #clock-cells = <1>;
299 clock-indices = <
300 R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
301 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
302 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
303 >;
304 clock-output-names = "hscif1", "hscif0", "scif3",
305 "scif2", "scif1", "scif0";
306 };
307 };
308
309 /* External root clock */
310 extal_clk: extal {
311 compatible = "fixed-clock";
312 #clock-cells = <0>;
313 /* This value must be overridden by the board. */
314 clock-frequency = <0>;
315 };
316
317 /* External SCIF clock */
318 scif_clk: scif {
319 compatible = "fixed-clock";
320 #clock-cells = <0>;
321 /* This value must be overridden by the board. */
322 clock-frequency = <0>;
323 };
324};