blob: 62ea0c9e321b4c1e7e095ed6f70091ae775c5e5b [file] [log] [blame]
Thomas Gleixnerd2912cb2019-06-04 10:11:33 +02001// SPDX-License-Identifier: GPL-2.0-only
Thomas Chou0b782532011-02-14 10:10:43 +08002/*
3 * Altera SPI driver
4 *
5 * Copyright (C) 2008 Thomas Chou <thomas@wytron.com.tw>
6 *
7 * Based on spi_s3c24xx.c, which is:
8 * Copyright (c) 2006 Ben Dooks
9 * Copyright (c) 2006 Simtec Electronics
10 * Ben Dooks <ben@simtec.co.uk>
Thomas Chou0b782532011-02-14 10:10:43 +080011 */
12
Thomas Chou0b782532011-02-14 10:10:43 +080013#include <linux/interrupt.h>
14#include <linux/errno.h>
Paul Gortmakerd7614de2011-07-03 15:44:29 -040015#include <linux/module.h>
Thomas Chou0b782532011-02-14 10:10:43 +080016#include <linux/platform_device.h>
Xu Yilun8e041872020-06-11 11:25:07 +080017#include <linux/spi/altera.h>
Thomas Chou0b782532011-02-14 10:10:43 +080018#include <linux/spi/spi.h>
Thomas Chou0b782532011-02-14 10:10:43 +080019#include <linux/io.h>
20#include <linux/of.h>
21
22#define DRV_NAME "spi_altera"
23
24#define ALTERA_SPI_RXDATA 0
25#define ALTERA_SPI_TXDATA 4
26#define ALTERA_SPI_STATUS 8
27#define ALTERA_SPI_CONTROL 12
28#define ALTERA_SPI_SLAVE_SEL 20
29
30#define ALTERA_SPI_STATUS_ROE_MSK 0x8
31#define ALTERA_SPI_STATUS_TOE_MSK 0x10
32#define ALTERA_SPI_STATUS_TMT_MSK 0x20
33#define ALTERA_SPI_STATUS_TRDY_MSK 0x40
34#define ALTERA_SPI_STATUS_RRDY_MSK 0x80
35#define ALTERA_SPI_STATUS_E_MSK 0x100
36
37#define ALTERA_SPI_CONTROL_IROE_MSK 0x8
38#define ALTERA_SPI_CONTROL_ITOE_MSK 0x10
39#define ALTERA_SPI_CONTROL_ITRDY_MSK 0x40
40#define ALTERA_SPI_CONTROL_IRRDY_MSK 0x80
41#define ALTERA_SPI_CONTROL_IE_MSK 0x100
42#define ALTERA_SPI_CONTROL_SSO_MSK 0x400
43
Xu Yilun8e041872020-06-11 11:25:07 +080044#define ALTERA_SPI_MAX_CS 32
45
Xu Yilun38200612020-06-19 09:43:40 +080046enum altera_spi_type {
47 ALTERA_SPI_TYPE_UNKNOWN,
48 ALTERA_SPI_TYPE_SUBDEV,
49};
50
Thomas Chou0b782532011-02-14 10:10:43 +080051struct altera_spi {
Thomas Chou0b782532011-02-14 10:10:43 +080052 int irq;
53 int len;
54 int count;
55 int bytes_per_word;
Matthew Gerlachd9dd0fb2020-06-19 09:43:41 +080056 u32 imr;
Thomas Chou0b782532011-02-14 10:10:43 +080057
58 /* data buffers */
59 const unsigned char *tx;
60 unsigned char *rx;
Xu Yilun3c651972020-06-19 09:43:39 +080061
62 struct regmap *regmap;
Xu Yilun38200612020-06-19 09:43:40 +080063 u32 regoff;
Xu Yilun3c651972020-06-19 09:43:39 +080064 struct device *dev;
Thomas Chou0b782532011-02-14 10:10:43 +080065};
66
Xu Yilun3c651972020-06-19 09:43:39 +080067static const struct regmap_config spi_altera_config = {
68 .reg_bits = 32,
69 .reg_stride = 4,
70 .val_bits = 32,
71 .fast_io = true,
72};
73
74static int altr_spi_writel(struct altera_spi *hw, unsigned int reg,
75 unsigned int val)
76{
77 int ret;
78
Xu Yilun38200612020-06-19 09:43:40 +080079 ret = regmap_write(hw->regmap, hw->regoff + reg, val);
Xu Yilun3c651972020-06-19 09:43:39 +080080 if (ret)
81 dev_err(hw->dev, "fail to write reg 0x%x val 0x%x: %d\n",
82 reg, val, ret);
83
84 return ret;
85}
86
87static int altr_spi_readl(struct altera_spi *hw, unsigned int reg,
88 unsigned int *val)
89{
90 int ret;
91
Xu Yilun38200612020-06-19 09:43:40 +080092 ret = regmap_read(hw->regmap, hw->regoff + reg, val);
Xu Yilun3c651972020-06-19 09:43:39 +080093 if (ret)
94 dev_err(hw->dev, "fail to read reg 0x%x: %d\n", reg, ret);
95
96 return ret;
97}
98
Thomas Chou0b782532011-02-14 10:10:43 +080099static inline struct altera_spi *altera_spi_to_hw(struct spi_device *sdev)
100{
101 return spi_master_get_devdata(sdev->master);
102}
103
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200104static void altera_spi_set_cs(struct spi_device *spi, bool is_high)
Thomas Chou0b782532011-02-14 10:10:43 +0800105{
106 struct altera_spi *hw = altera_spi_to_hw(spi);
107
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200108 if (is_high) {
109 hw->imr &= ~ALTERA_SPI_CONTROL_SSO_MSK;
Xu Yilun3c651972020-06-19 09:43:39 +0800110 altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
111 altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL, 0);
Thomas Chou0b782532011-02-14 10:10:43 +0800112 } else {
Xu Yilun3c651972020-06-19 09:43:39 +0800113 altr_spi_writel(hw, ALTERA_SPI_SLAVE_SEL,
114 BIT(spi->chip_select));
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200115 hw->imr |= ALTERA_SPI_CONTROL_SSO_MSK;
Xu Yilun3c651972020-06-19 09:43:39 +0800116 altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
Thomas Chou0b782532011-02-14 10:10:43 +0800117 }
118}
119
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200120static void altera_spi_tx_word(struct altera_spi *hw)
Thomas Chou0b782532011-02-14 10:10:43 +0800121{
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200122 unsigned int txd = 0;
123
Thomas Chou0b782532011-02-14 10:10:43 +0800124 if (hw->tx) {
125 switch (hw->bytes_per_word) {
126 case 1:
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200127 txd = hw->tx[hw->count];
128 break;
Thomas Chou0b782532011-02-14 10:10:43 +0800129 case 2:
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200130 txd = (hw->tx[hw->count * 2]
131 | (hw->tx[hw->count * 2 + 1] << 8));
132 break;
Xu Yilun3011d312020-06-11 11:25:06 +0800133 case 4:
134 txd = (hw->tx[hw->count * 4]
135 | (hw->tx[hw->count * 4 + 1] << 8)
136 | (hw->tx[hw->count * 4 + 2] << 16)
137 | (hw->tx[hw->count * 4 + 3] << 24));
138 break;
139
Thomas Chou0b782532011-02-14 10:10:43 +0800140 }
141 }
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200142
Xu Yilun3c651972020-06-19 09:43:39 +0800143 altr_spi_writel(hw, ALTERA_SPI_TXDATA, txd);
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200144}
145
146static void altera_spi_rx_word(struct altera_spi *hw)
147{
148 unsigned int rxd;
149
Xu Yilun3c651972020-06-19 09:43:39 +0800150 altr_spi_readl(hw, ALTERA_SPI_RXDATA, &rxd);
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200151 if (hw->rx) {
152 switch (hw->bytes_per_word) {
153 case 1:
154 hw->rx[hw->count] = rxd;
155 break;
156 case 2:
157 hw->rx[hw->count * 2] = rxd;
158 hw->rx[hw->count * 2 + 1] = rxd >> 8;
159 break;
Xu Yilun3011d312020-06-11 11:25:06 +0800160 case 4:
161 hw->rx[hw->count * 4] = rxd;
162 hw->rx[hw->count * 4 + 1] = rxd >> 8;
163 hw->rx[hw->count * 4 + 2] = rxd >> 16;
164 hw->rx[hw->count * 4 + 3] = rxd >> 24;
165 break;
166
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200167 }
168 }
169
170 hw->count++;
Thomas Chou0b782532011-02-14 10:10:43 +0800171}
172
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200173static int altera_spi_txrx(struct spi_master *master,
174 struct spi_device *spi, struct spi_transfer *t)
Thomas Chou0b782532011-02-14 10:10:43 +0800175{
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200176 struct altera_spi *hw = spi_master_get_devdata(master);
Xu Yilun3c651972020-06-19 09:43:39 +0800177 u32 val;
Thomas Chou0b782532011-02-14 10:10:43 +0800178
179 hw->tx = t->tx_buf;
180 hw->rx = t->rx_buf;
181 hw->count = 0;
Axel Linf073d372013-08-29 23:41:20 +0800182 hw->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
Thomas Chou0b782532011-02-14 10:10:43 +0800183 hw->len = t->len / hw->bytes_per_word;
184
185 if (hw->irq >= 0) {
186 /* enable receive interrupt */
187 hw->imr |= ALTERA_SPI_CONTROL_IRRDY_MSK;
Xu Yilun3c651972020-06-19 09:43:39 +0800188 altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
Thomas Chou0b782532011-02-14 10:10:43 +0800189
190 /* send the first byte */
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200191 altera_spi_tx_word(hw);
Axel Lin72be0ee2013-08-15 14:18:46 +0800192
Xu Yilun78755372020-12-29 13:27:41 +0800193 return 1;
Thomas Chou0b782532011-02-14 10:10:43 +0800194 }
195
Xu Yilun78755372020-12-29 13:27:41 +0800196 while (hw->count < hw->len) {
197 altera_spi_tx_word(hw);
198
199 for (;;) {
200 altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
201 if (val & ALTERA_SPI_STATUS_RRDY_MSK)
202 break;
203
204 cpu_relax();
205 }
206
207 altera_spi_rx_word(hw);
208 }
209 spi_finalize_current_transfer(master);
210
211 return 0;
Thomas Chou0b782532011-02-14 10:10:43 +0800212}
213
214static irqreturn_t altera_spi_irq(int irq, void *dev)
215{
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200216 struct spi_master *master = dev;
217 struct altera_spi *hw = spi_master_get_devdata(master);
Thomas Chou0b782532011-02-14 10:10:43 +0800218
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200219 altera_spi_rx_word(hw);
Thomas Chou0b782532011-02-14 10:10:43 +0800220
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200221 if (hw->count < hw->len) {
Lars-Peter Clausenb64836a2017-08-16 11:33:12 +0200222 altera_spi_tx_word(hw);
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200223 } else {
224 /* disable receive interrupt */
225 hw->imr &= ~ALTERA_SPI_CONTROL_IRRDY_MSK;
Xu Yilun3c651972020-06-19 09:43:39 +0800226 altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200227
228 spi_finalize_current_transfer(master);
229 }
Thomas Chou0b782532011-02-14 10:10:43 +0800230
231 return IRQ_HANDLED;
232}
233
Grant Likelyfd4a3192012-12-07 16:57:14 +0000234static int altera_spi_probe(struct platform_device *pdev)
Thomas Chou0b782532011-02-14 10:10:43 +0800235{
Xu Yilun38200612020-06-19 09:43:40 +0800236 const struct platform_device_id *platid = platform_get_device_id(pdev);
Xu Yilun8e041872020-06-11 11:25:07 +0800237 struct altera_spi_platform_data *pdata = dev_get_platdata(&pdev->dev);
Xu Yilun38200612020-06-19 09:43:40 +0800238 enum altera_spi_type type = ALTERA_SPI_TYPE_UNKNOWN;
Thomas Chou0b782532011-02-14 10:10:43 +0800239 struct altera_spi *hw;
240 struct spi_master *master;
Thomas Chou0b782532011-02-14 10:10:43 +0800241 int err = -ENODEV;
Xu Yilun3c651972020-06-19 09:43:39 +0800242 u32 val;
Xu Yilun1fccd182020-06-11 11:25:08 +0800243 u16 i;
Thomas Chou0b782532011-02-14 10:10:43 +0800244
245 master = spi_alloc_master(&pdev->dev, sizeof(struct altera_spi));
246 if (!master)
247 return err;
248
249 /* setup the master state. */
250 master->bus_num = pdev->id;
Xu Yilun8e041872020-06-11 11:25:07 +0800251
252 if (pdata) {
253 if (pdata->num_chipselect > ALTERA_SPI_MAX_CS) {
254 dev_err(&pdev->dev,
255 "Invalid number of chipselect: %hu\n",
256 pdata->num_chipselect);
Pan Biancea3d7c2021-01-20 00:26:35 -0800257 err = -EINVAL;
258 goto exit;
Xu Yilun8e041872020-06-11 11:25:07 +0800259 }
260
261 master->num_chipselect = pdata->num_chipselect;
262 master->mode_bits = pdata->mode_bits;
263 master->bits_per_word_mask = pdata->bits_per_word_mask;
264 } else {
265 master->num_chipselect = 16;
266 master->mode_bits = SPI_CS_HIGH;
267 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
268 }
269
Axel Linbf2f2f72014-03-21 11:21:58 +0800270 master->dev.of_node = pdev->dev.of_node;
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200271 master->transfer_one = altera_spi_txrx;
272 master->set_cs = altera_spi_set_cs;
Thomas Chou0b782532011-02-14 10:10:43 +0800273
274 hw = spi_master_get_devdata(master);
Xu Yilun3c651972020-06-19 09:43:39 +0800275 hw->dev = &pdev->dev;
Thomas Chou0b782532011-02-14 10:10:43 +0800276
Xu Yilun38200612020-06-19 09:43:40 +0800277 if (platid)
278 type = platid->driver_data;
Xu Yilun3c651972020-06-19 09:43:39 +0800279
Xu Yilun38200612020-06-19 09:43:40 +0800280 /* find and map our resources */
281 if (type == ALTERA_SPI_TYPE_SUBDEV) {
282 struct resource *regoff;
283
284 hw->regmap = dev_get_regmap(pdev->dev.parent, NULL);
285 if (!hw->regmap) {
286 dev_err(&pdev->dev, "get regmap failed\n");
287 goto exit;
288 }
289
290 regoff = platform_get_resource(pdev, IORESOURCE_REG, 0);
291 if (regoff)
292 hw->regoff = regoff->start;
293 } else {
294 void __iomem *res;
295
296 res = devm_platform_ioremap_resource(pdev, 0);
297 if (IS_ERR(res)) {
298 err = PTR_ERR(res);
299 goto exit;
300 }
301
302 hw->regmap = devm_regmap_init_mmio(&pdev->dev, res,
303 &spi_altera_config);
304 if (IS_ERR(hw->regmap)) {
305 dev_err(&pdev->dev, "regmap mmio init failed\n");
306 err = PTR_ERR(hw->regmap);
307 goto exit;
308 }
Xu Yilun3c651972020-06-19 09:43:39 +0800309 }
310
Thomas Chou0b782532011-02-14 10:10:43 +0800311 /* program defaults into the registers */
312 hw->imr = 0; /* disable spi interrupts */
Xu Yilun3c651972020-06-19 09:43:39 +0800313 altr_spi_writel(hw, ALTERA_SPI_CONTROL, hw->imr);
314 altr_spi_writel(hw, ALTERA_SPI_STATUS, 0); /* clear status reg */
315 altr_spi_readl(hw, ALTERA_SPI_STATUS, &val);
316 if (val & ALTERA_SPI_STATUS_RRDY_MSK)
317 altr_spi_readl(hw, ALTERA_SPI_RXDATA, &val); /* flush rxdata */
Thomas Chou0b782532011-02-14 10:10:43 +0800318 /* irq is optional */
319 hw->irq = platform_get_irq(pdev, 0);
320 if (hw->irq >= 0) {
Thomas Chou0b782532011-02-14 10:10:43 +0800321 err = devm_request_irq(&pdev->dev, hw->irq, altera_spi_irq, 0,
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200322 pdev->name, master);
Thomas Chou0b782532011-02-14 10:10:43 +0800323 if (err)
324 goto exit;
325 }
Thomas Chou0b782532011-02-14 10:10:43 +0800326
Lars-Peter Clausene19b63c2017-08-16 11:33:11 +0200327 err = devm_spi_register_master(&pdev->dev, master);
Thomas Chou0b782532011-02-14 10:10:43 +0800328 if (err)
329 goto exit;
Xu Yilun1fccd182020-06-11 11:25:08 +0800330
331 if (pdata) {
332 for (i = 0; i < pdata->num_devices; i++) {
333 if (!spi_new_device(master, pdata->devices + i))
334 dev_warn(&pdev->dev,
335 "unable to create SPI device: %s\n",
336 pdata->devices[i].modalias);
337 }
338 }
339
Xu Yilun38200612020-06-19 09:43:40 +0800340 dev_info(&pdev->dev, "regoff %u, irq %d\n", hw->regoff, hw->irq);
Thomas Chou0b782532011-02-14 10:10:43 +0800341
342 return 0;
Thomas Chou0b782532011-02-14 10:10:43 +0800343exit:
Thomas Chou0b782532011-02-14 10:10:43 +0800344 spi_master_put(master);
345 return err;
346}
347
Thomas Chou0b782532011-02-14 10:10:43 +0800348#ifdef CONFIG_OF
349static const struct of_device_id altera_spi_match[] = {
350 { .compatible = "ALTR,spi-1.0", },
Dinh Nguyen13960b42013-08-14 15:25:19 -0500351 { .compatible = "altr,spi-1.0", },
Thomas Chou0b782532011-02-14 10:10:43 +0800352 {},
353};
354MODULE_DEVICE_TABLE(of, altera_spi_match);
Thomas Chou0b782532011-02-14 10:10:43 +0800355#endif /* CONFIG_OF */
356
Xu Yilun38200612020-06-19 09:43:40 +0800357static const struct platform_device_id altera_spi_ids[] = {
Xu Yilunde5fd9c2020-06-24 09:31:25 +0800358 { DRV_NAME, ALTERA_SPI_TYPE_UNKNOWN },
359 { "subdev_spi_altera", ALTERA_SPI_TYPE_SUBDEV },
Xu Yilun38200612020-06-19 09:43:40 +0800360 { }
361};
Xu Yilun1ac6f212020-06-24 09:31:26 +0800362MODULE_DEVICE_TABLE(platform, altera_spi_ids);
Xu Yilun38200612020-06-19 09:43:40 +0800363
Thomas Chou0b782532011-02-14 10:10:43 +0800364static struct platform_driver altera_spi_driver = {
365 .probe = altera_spi_probe,
Thomas Chou0b782532011-02-14 10:10:43 +0800366 .driver = {
367 .name = DRV_NAME,
Thomas Chou0b782532011-02-14 10:10:43 +0800368 .pm = NULL,
Tobias Klauser89f98dc2012-08-15 09:30:28 +0200369 .of_match_table = of_match_ptr(altera_spi_match),
Thomas Chou0b782532011-02-14 10:10:43 +0800370 },
Xu Yilun38200612020-06-19 09:43:40 +0800371 .id_table = altera_spi_ids,
Thomas Chou0b782532011-02-14 10:10:43 +0800372};
Grant Likely940ab882011-10-05 11:29:49 -0600373module_platform_driver(altera_spi_driver);
Thomas Chou0b782532011-02-14 10:10:43 +0800374
375MODULE_DESCRIPTION("Altera SPI driver");
376MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
377MODULE_LICENSE("GPL");
378MODULE_ALIAS("platform:" DRV_NAME);