| Masahiro Yamada | 4b7f48d | 2015-12-09 15:52:59 +0900 | [diff] [blame] | 1 | UniPhier System Bus |
| 2 | |
| 3 | The UniPhier System Bus is an external bus that connects on-board devices to |
| 4 | the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and |
| 5 | some control signals. It supports up to 8 banks (chip selects). |
| 6 | |
| 7 | Before any access to the bus, the bus controller must be configured; the bus |
| 8 | controller registers provide the control for the translation from the offset |
| 9 | within each bank to the CPU-viewed address. The needed setup includes the base |
| 10 | address, the size of each bank. Optionally, some timing parameters can be |
| 11 | optimized for faster bus access. |
| 12 | |
| 13 | Required properties: |
| 14 | - compatible: should be "socionext,uniphier-system-bus". |
| 15 | - reg: offset and length of the register set for the bus controller device. |
| 16 | - #address-cells: should be 2. The first cell is the bank number (chip select). |
| 17 | The second cell is the address offset within the bank. |
| 18 | - #size-cells: should be 1. |
| 19 | - ranges: should provide a proper address translation from the System Bus to |
| 20 | the parent bus. |
| 21 | |
| 22 | Note: |
| 23 | The address region(s) that can be assigned for the System Bus is implementation |
| 24 | defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff, |
| 25 | while other SoCs can only use 0x40000000-0x4fffffff. There might be additional |
| 26 | limitations depending on SoCs and the boot mode. The address translation is |
| 27 | arbitrary as long as the banks are assigned in the supported address space with |
| 28 | the required alignment and they do not overlap one another. |
| 29 | For example, it is possible to map: |
| 30 | bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff |
| 31 | It is also possible to map: |
| 32 | bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff |
| 33 | There is no reason to stick to a particular translation mapping, but the |
| 34 | "ranges" property should provide a "reasonable" default that is known to work. |
| 35 | The software should initialize the bus controller according to it. |
| 36 | |
| 37 | Example: |
| 38 | |
| 39 | system-bus { |
| 40 | compatible = "socionext,uniphier-system-bus"; |
| 41 | reg = <0x58c00000 0x400>; |
| 42 | #address-cells = <2>; |
| 43 | #size-cells = <1>; |
| 44 | ranges = <1 0x00000000 0x42000000 0x02000000 |
| 45 | 5 0x00000000 0x46000000 0x01000000>; |
| 46 | |
| 47 | ethernet@1,01f00000 { |
| 48 | compatible = "smsc,lan9115"; |
| 49 | reg = <1 0x01f00000 0x1000>; |
| 50 | interrupts = <0 48 4> |
| 51 | phy-mode = "mii"; |
| 52 | }; |
| 53 | |
| 54 | uart@5,00200000 { |
| 55 | compatible = "ns16550a"; |
| 56 | reg = <5 0x00200000 0x20>; |
| 57 | interrupts = <0 49 4> |
| 58 | clock-frequency = <12288000>; |
| 59 | }; |
| 60 | }; |
| 61 | |
| 62 | In this example, |
| 63 | - the Ethernet device is connected at the offset 0x01f00000 of CS1 and |
| 64 | mapped to 0x43f00000 of the parent bus. |
| 65 | - the UART device is connected at the offset 0x00200000 of CS5 and |
| 66 | mapped to 0x46200000 of the parent bus. |