blob: 5dd34a1a7b899217eaabdb8b4abdb8985695684c [file] [log] [blame]
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001/*
Andy Flemingbb40dcb2005-09-23 22:54:21 -04002 * drivers/net/gianfar_mii.c
3 *
4 * Gianfar Ethernet Driver -- MIIM bus implementation
5 * Provides Bus interface for MIIM regs
6 *
7 * Author: Andy Fleming
Kumar Gala4c8d3d92005-11-13 16:06:30 -08008 * Maintainer: Kumar Gala
Andy Flemingbb40dcb2005-09-23 22:54:21 -04009 *
10 * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18
Andy Flemingbb40dcb2005-09-23 22:54:21 -040019#include <linux/kernel.h>
Andy Flemingbb40dcb2005-09-23 22:54:21 -040020#include <linux/string.h>
21#include <linux/errno.h>
22#include <linux/unistd.h>
23#include <linux/slab.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/spinlock.h>
31#include <linux/mm.h>
32#include <linux/module.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010033#include <linux/platform_device.h>
Andy Flemingbb40dcb2005-09-23 22:54:21 -040034#include <asm/ocp.h>
35#include <linux/crc32.h>
36#include <linux/mii.h>
37#include <linux/phy.h>
38
39#include <asm/io.h>
40#include <asm/irq.h>
41#include <asm/uaccess.h>
42
43#include "gianfar.h"
44#include "gianfar_mii.h"
45
Kapil Junejad3c12872007-05-11 18:25:11 -050046/*
47 * Write value to the PHY at mii_id at register regnum,
48 * on the bus attached to the local interface, which may be different from the
49 * generic mdio bus (tied to a single interface), waiting until the write is
50 * done before returning. This is helpful in programming interfaces like
51 * the TBI which control interfaces like onchip SERDES and are always tied to
52 * the local mdio pins, which may not be the same as system mdio bus, used for
53 * controlling the external PHYs, for example.
54 */
55int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id,
56 int regnum, u16 value)
Andy Flemingbb40dcb2005-09-23 22:54:21 -040057{
Andy Flemingbb40dcb2005-09-23 22:54:21 -040058 /* Set the PHY address and the register address we want to write */
59 gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
60
61 /* Write out the value we want */
62 gfar_write(&regs->miimcon, value);
63
64 /* Wait for the transaction to finish */
65 while (gfar_read(&regs->miimind) & MIIMIND_BUSY)
66 cpu_relax();
67
68 return 0;
69}
70
Kapil Junejad3c12872007-05-11 18:25:11 -050071/*
72 * Read the bus for PHY at addr mii_id, register regnum, and
73 * return the value. Clears miimcom first. All PHY operation
74 * done on the bus attached to the local interface,
75 * which may be different from the generic mdio bus
76 * This is helpful in programming interfaces like
77 * the TBI which, inturn, control interfaces like onchip SERDES
78 * and are always tied to the local mdio pins, which may not be the
79 * same as system mdio bus, used for controlling the external PHYs, for eg.
80 */
81int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum)
82
Andy Flemingbb40dcb2005-09-23 22:54:21 -040083{
Andy Flemingbb40dcb2005-09-23 22:54:21 -040084 u16 value;
85
86 /* Set the PHY address and the register address we want to read */
87 gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
88
89 /* Clear miimcom, and then initiate a read */
90 gfar_write(&regs->miimcom, 0);
91 gfar_write(&regs->miimcom, MII_READ_COMMAND);
92
93 /* Wait for the transaction to finish */
94 while (gfar_read(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
95 cpu_relax();
96
97 /* Grab the value of the register from miimstat */
98 value = gfar_read(&regs->miimstat);
99
100 return value;
101}
102
Kapil Junejad3c12872007-05-11 18:25:11 -0500103/* Write value to the PHY at mii_id at register regnum,
104 * on the bus, waiting until the write is done before returning.
105 * All PHY configuration is done through the TSEC1 MIIM regs */
106int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
107{
108 struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
109
110 /* Write to the local MII regs */
111 return(gfar_local_mdio_write(regs, mii_id, regnum, value));
112}
113
114/* Read the bus for PHY at addr mii_id, register regnum, and
115 * return the value. Clears miimcom first. All PHY
116 * configuration has to be done through the TSEC1 MIIM regs */
117int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
118{
119 struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
120
121 /* Read the local MII regs */
122 return(gfar_local_mdio_read(regs, mii_id, regnum));
123}
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400124
125/* Reset the MIIM registers, and wait for the bus to free */
126int gfar_mdio_reset(struct mii_bus *bus)
127{
Kumar Galacc8c6e32006-02-01 15:18:03 -0600128 struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400129 unsigned int timeout = PHY_INIT_TIMEOUT;
130
131 spin_lock_bh(&bus->mdio_lock);
132
133 /* Reset the management interface */
134 gfar_write(&regs->miimcfg, MIIMCFG_RESET);
135
136 /* Setup the MII Mgmt clock speed */
137 gfar_write(&regs->miimcfg, MIIMCFG_INIT_VALUE);
138
139 /* Wait until the bus is free */
140 while ((gfar_read(&regs->miimind) & MIIMIND_BUSY) &&
141 timeout--)
142 cpu_relax();
143
144 spin_unlock_bh(&bus->mdio_lock);
145
146 if(timeout <= 0) {
147 printk(KERN_ERR "%s: The MII Bus is stuck!\n",
148 bus->name);
149 return -EBUSY;
150 }
151
152 return 0;
153}
154
155
156int gfar_mdio_probe(struct device *dev)
157{
158 struct platform_device *pdev = to_platform_device(dev);
159 struct gianfar_mdio_data *pdata;
Kumar Galacc8c6e32006-02-01 15:18:03 -0600160 struct gfar_mii __iomem *regs;
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400161 struct mii_bus *new_bus;
Kumar Gala1d532672006-01-11 11:27:32 -0800162 struct resource *r;
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400163 int err = 0;
164
165 if (NULL == dev)
166 return -EINVAL;
167
Kumar Gala125d1282005-11-09 12:13:11 -0600168 new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400169
170 if (NULL == new_bus)
171 return -ENOMEM;
172
173 new_bus->name = "Gianfar MII Bus",
174 new_bus->read = &gfar_mdio_read,
175 new_bus->write = &gfar_mdio_write,
176 new_bus->reset = &gfar_mdio_reset,
177 new_bus->id = pdev->id;
178
179 pdata = (struct gianfar_mdio_data *)pdev->dev.platform_data;
180
181 if (NULL == pdata) {
182 printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
183 return -ENODEV;
184 }
185
Kumar Gala1d532672006-01-11 11:27:32 -0800186 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
187
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400188 /* Set the PHY base address */
Kumar Galacc8c6e32006-02-01 15:18:03 -0600189 regs = ioremap(r->start, sizeof (struct gfar_mii));
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400190
191 if (NULL == regs) {
192 err = -ENOMEM;
193 goto reg_map_fail;
194 }
195
Kumar Galacc8c6e32006-02-01 15:18:03 -0600196 new_bus->priv = (void __force *)regs;
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400197
198 new_bus->irq = pdata->irq;
199
200 new_bus->dev = dev;
201 dev_set_drvdata(dev, new_bus);
202
203 err = mdiobus_register(new_bus);
204
205 if (0 != err) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400206 printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400207 new_bus->name);
208 goto bus_register_fail;
209 }
210
211 return 0;
212
213bus_register_fail:
Kumar Galacc8c6e32006-02-01 15:18:03 -0600214 iounmap(regs);
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400215reg_map_fail:
216 kfree(new_bus);
217
218 return err;
219}
220
221
222int gfar_mdio_remove(struct device *dev)
223{
224 struct mii_bus *bus = dev_get_drvdata(dev);
225
226 mdiobus_unregister(bus);
227
228 dev_set_drvdata(dev, NULL);
229
Kumar Galacc8c6e32006-02-01 15:18:03 -0600230 iounmap((void __iomem *)bus->priv);
Andy Flemingbb40dcb2005-09-23 22:54:21 -0400231 bus->priv = NULL;
232 kfree(bus);
233
234 return 0;
235}
236
237static struct device_driver gianfar_mdio_driver = {
238 .name = "fsl-gianfar_mdio",
239 .bus = &platform_bus_type,
240 .probe = gfar_mdio_probe,
241 .remove = gfar_mdio_remove,
242};
243
244int __init gfar_mdio_init(void)
245{
246 return driver_register(&gianfar_mdio_driver);
247}
248
249void __exit gfar_mdio_exit(void)
250{
251 driver_unregister(&gianfar_mdio_driver);
252}