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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / d381f45c890a3fb136afb0dc1cbe025e066cb981 / . / arch / arm / boot / dts / imx51.dtsi
blob: fcf035bf7c5af45a453c6ad2d8c78811329b4e4f [file] [log] [blame]
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]24 };
25
26 tzic: tz-interrupt-controller@e0000000 {
27 compatible = "fsl,imx51-tzic", "fsl,tzic";
28 interrupt-controller;
29 #interrupt-cells = <1>;
30 reg = <0xe0000000 0x4000>;
31 };
32
33 clocks {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 ckil {
38 compatible = "fsl,imx-ckil", "fixed-clock";
39 clock-frequency = <32768>;
40 };
41
42 ckih1 {
43 compatible = "fsl,imx-ckih1", "fixed-clock";
44 clock-frequency = <22579200>;
45 };
46
47 ckih2 {
48 compatible = "fsl,imx-ckih2", "fixed-clock";
49 clock-frequency = <0>;
50 };
51
52 osc {
53 compatible = "fsl,imx-osc", "fixed-clock";
54 clock-frequency = <24000000>;
55 };
56 };
57
58 soc {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 compatible = "simple-bus";
62 interrupt-parent = <&tzic>;
63 ranges;
64
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]65 ipu: ipu@40000000 {
66 #crtc-cells = <1>;
67 compatible = "fsl,imx51-ipu";
68 reg = <0x40000000 0x20000000>;
69 interrupts = <11 10>;
70 };
71
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]72 aips@70000000 { /* AIPS1 */
73 compatible = "fsl,aips-bus", "simple-bus";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 reg = <0x70000000 0x10000000>;
77 ranges;
78
79 spba@70000000 {
80 compatible = "fsl,spba-bus", "simple-bus";
81 #address-cells = <1>;
82 #size-cells = <1>;
83 reg = <0x70000000 0x40000>;
84 ranges;
85
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]86 esdhc1: esdhc@70004000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]87 compatible = "fsl,imx51-esdhc";
88 reg = <0x70004000 0x4000>;
89 interrupts = <1>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]90 clocks = <&clks 44>, <&clks 0>, <&clks 71>;
91 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]92 status = "disabled";
93 };
94
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]95 esdhc2: esdhc@70008000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]96 compatible = "fsl,imx51-esdhc";
97 reg = <0x70008000 0x4000>;
98 interrupts = <2>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]99 clocks = <&clks 45>, <&clks 0>, <&clks 72>;
100 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]101 bus-width = <4>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]102 status = "disabled";
103 };
104
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]105 uart3: serial@7000c000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]106 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
107 reg = <0x7000c000 0x4000>;
108 interrupts = <33>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]109 clocks = <&clks 32>, <&clks 33>;
110 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]111 status = "disabled";
112 };
113
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]114 ecspi1: ecspi@70010000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]115 #address-cells = <1>;
116 #size-cells = <0>;
117 compatible = "fsl,imx51-ecspi";
118 reg = <0x70010000 0x4000>;
119 interrupts = <36>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]120 clocks = <&clks 51>, <&clks 52>;
121 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]122 status = "disabled";
123 };
124
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]125 ssi2: ssi@70014000 {
126 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
127 reg = <0x70014000 0x4000>;
128 interrupts = <30>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]129 clocks = <&clks 49>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]130 fsl,fifo-depth = <15>;
131 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
132 status = "disabled";
133 };
134
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]135 esdhc3: esdhc@70020000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]136 compatible = "fsl,imx51-esdhc";
137 reg = <0x70020000 0x4000>;
138 interrupts = <3>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]139 clocks = <&clks 46>, <&clks 0>, <&clks 73>;
140 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]141 bus-width = <4>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]142 status = "disabled";
143 };
144
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]145 esdhc4: esdhc@70024000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]146 compatible = "fsl,imx51-esdhc";
147 reg = <0x70024000 0x4000>;
148 interrupts = <4>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]149 clocks = <&clks 47>, <&clks 0>, <&clks 74>;
150 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]151 bus-width = <4>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]152 status = "disabled";
153 };
154 };
155
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]156 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]157 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
158 reg = <0x73f80000 0x0200>;
159 interrupts = <18>;
160 status = "disabled";
161 };
162
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]163 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]164 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
165 reg = <0x73f80200 0x0200>;
166 interrupts = <14>;
167 status = "disabled";
168 };
169
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]170 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]171 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
172 reg = <0x73f80400 0x0200>;
173 interrupts = <16>;
174 status = "disabled";
175 };
176
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]177 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]178 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
179 reg = <0x73f80600 0x0200>;
180 interrupts = <17>;
181 status = "disabled";
182 };
183
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]184 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]185 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]186 reg = <0x73f84000 0x4000>;
187 interrupts = <50 51>;
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]191 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]192 };
193
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]194 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]195 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]196 reg = <0x73f88000 0x4000>;
197 interrupts = <52 53>;
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]201 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]202 };
203
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]204 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]205 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]206 reg = <0x73f8c000 0x4000>;
207 interrupts = <54 55>;
208 gpio-controller;
209 #gpio-cells = <2>;
210 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]211 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]212 };
213
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]214 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]215 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]216 reg = <0x73f90000 0x4000>;
217 interrupts = <56 57>;
218 gpio-controller;
219 #gpio-cells = <2>;
220 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]221 #interrupt-cells = <2>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]222 };
223
Liu Ying6012555c2013-01-03 20:37:33 +0800[diff] [blame]224 kpp: kpp@73f94000 {
225 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
226 reg = <0x73f94000 0x4000>;
227 interrupts = <60>;
228 clocks = <&clks 0>;
229 status = "disabled";
230 };
231
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]232 wdog1: wdog@73f98000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]233 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
234 reg = <0x73f98000 0x4000>;
235 interrupts = <58>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]236 clocks = <&clks 0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]237 };
238
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]239 wdog2: wdog@73f9c000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]240 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
241 reg = <0x73f9c000 0x4000>;
242 interrupts = <59>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]243 clocks = <&clks 0>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]244 status = "disabled";
245 };
246
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]247 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]248 compatible = "fsl,imx51-iomuxc";
249 reg = <0x73fa8000 0x4000>;
250
251 audmux {
252 pinctrl_audmux_1: audmuxgrp-1 {
253 fsl,pins = <
254 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
255 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
256 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
257 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
258 >;
259 };
260 };
261
262 fec {
263 pinctrl_fec_1: fecgrp-1 {
264 fsl,pins = <
265 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
266 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
267 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
268 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
269 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
270 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
271 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
272 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
273 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
274 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
275 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
276 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
277 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
278 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
279 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
280 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
281 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
282 >;
283 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]284
285 pinctrl_fec_2: fecgrp-2 {
286 fsl,pins = <
287 589 0x80000000 /* MX51_PAD_DI_GP3__FEC_TX_ER */
288 592 0x80000000 /* MX51_PAD_DI2_PIN4__FEC_CRS */
289 594 0x80000000 /* MX51_PAD_DI2_PIN2__FEC_MDC */
290 596 0x80000000 /* MX51_PAD_DI2_PIN3__FEC_MDIO */
291 598 0x80000000 /* MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 */
292 602 0x80000000 /* MX51_PAD_DI_GP4__FEC_RDATA2 */
293 604 0x80000000 /* MX51_PAD_DISP2_DAT0__FEC_RDATA3 */
294 609 0x80000000 /* MX51_PAD_DISP2_DAT1__FEC_RX_ER */
295 618 0x80000000 /* MX51_PAD_DISP2_DAT6__FEC_TDATA1 */
296 623 0x80000000 /* MX51_PAD_DISP2_DAT7__FEC_TDATA2 */
297 628 0x80000000 /* MX51_PAD_DISP2_DAT8__FEC_TDATA3 */
298 634 0x80000000 /* MX51_PAD_DISP2_DAT9__FEC_TX_EN */
299 639 0x80000000 /* MX51_PAD_DISP2_DAT10__FEC_COL */
300 644 0x80000000 /* MX51_PAD_DISP2_DAT11__FEC_RX_CLK */
301 649 0x80000000 /* MX51_PAD_DISP2_DAT12__FEC_RX_DV */
302 653 0x80000000 /* MX51_PAD_DISP2_DAT13__FEC_TX_CLK */
303 657 0x80000000 /* MX51_PAD_DISP2_DAT14__FEC_RDATA0 */
304 662 0x80000000 /* MX51_PAD_DISP2_DAT15__FEC_TDATA0 */
305 >;
306 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]307 };
308
309 ecspi1 {
310 pinctrl_ecspi1_1: ecspi1grp-1 {
311 fsl,pins = <
312 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
313 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
314 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
315 >;
316 };
317 };
318
319 esdhc1 {
320 pinctrl_esdhc1_1: esdhc1grp-1 {
321 fsl,pins = <
322 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
323 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
324 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
325 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
326 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
327 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
328 >;
329 };
330 };
331
332 esdhc2 {
333 pinctrl_esdhc2_1: esdhc2grp-1 {
334 fsl,pins = <
335 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
336 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
337 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
338 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
339 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
340 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
341 >;
342 };
343 };
344
345 i2c2 {
346 pinctrl_i2c2_1: i2c2grp-1 {
347 fsl,pins = <
348 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
349 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
350 >;
351 };
352 };
353
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100[diff] [blame]354 ipu_disp1 {
355 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
356 fsl,pins = <
357 528 0x5 /* MX51_PAD_DISP1_DAT0__DISP1_DAT0 */
358 529 0x5 /* MX51_PAD_DISP1_DAT1__DISP1_DAT1 */
359 530 0x5 /* MX51_PAD_DISP1_DAT2__DISP1_DAT2 */
360 531 0x5 /* MX51_PAD_DISP1_DAT3__DISP1_DAT3 */
361 532 0x5 /* MX51_PAD_DISP1_DAT4__DISP1_DAT4 */
362 533 0x5 /* MX51_PAD_DISP1_DAT5__DISP1_DAT5 */
363 535 0x5 /* MX51_PAD_DISP1_DAT6__DISP1_DAT6 */
364 537 0x5 /* MX51_PAD_DISP1_DAT7__DISP1_DAT7 */
365 539 0x5 /* MX51_PAD_DISP1_DAT8__DISP1_DAT8 */
366 541 0x5 /* MX51_PAD_DISP1_DAT9__DISP1_DAT9 */
367 543 0x5 /* MX51_PAD_DISP1_DAT10__DISP1_DAT10 */
368 545 0x5 /* MX51_PAD_DISP1_DAT11__DISP1_DAT11 */
369 547 0x5 /* MX51_PAD_DISP1_DAT12__DISP1_DAT12 */
370 549 0x5 /* MX51_PAD_DISP1_DAT13__DISP1_DAT13 */
371 551 0x5 /* MX51_PAD_DISP1_DAT14__DISP1_DAT14 */
372 553 0x5 /* MX51_PAD_DISP1_DAT15__DISP1_DAT15 */
373 555 0x5 /* MX51_PAD_DISP1_DAT16__DISP1_DAT16 */
374 557 0x5 /* MX51_PAD_DISP1_DAT17__DISP1_DAT17 */
375 559 0x5 /* MX51_PAD_DISP1_DAT18__DISP1_DAT18 */
376 563 0x5 /* MX51_PAD_DISP1_DAT19__DISP1_DAT19 */
377 567 0x5 /* MX51_PAD_DISP1_DAT20__DISP1_DAT20 */
378 571 0x5 /* MX51_PAD_DISP1_DAT21__DISP1_DAT21 */
379 575 0x5 /* MX51_PAD_DISP1_DAT22__DISP1_DAT22 */
380 579 0x5 /* MX51_PAD_DISP1_DAT23__DISP1_DAT23 */
381 584 0x5 /* MX51_PAD_DI1_PIN2__DI1_PIN2 (hsync) */
382 583 0x5 /* MX51_PAD_DI1_PIN3__DI1_PIN3 (vsync) */
383 >;
384 };
385 };
386
387 ipu_disp2 {
388 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
389 fsl,pins = <
390 603 0x5 /* MX51_PAD_DISP2_DAT0__DISP2_DAT0 */
391 608 0x5 /* MX51_PAD_DISP2_DAT1__DISP2_DAT1 */
392 613 0x5 /* MX51_PAD_DISP2_DAT2__DISP2_DAT2 */
393 614 0x5 /* MX51_PAD_DISP2_DAT3__DISP2_DAT3 */
394 615 0x5 /* MX51_PAD_DISP2_DAT4__DISP2_DAT4 */
395 616 0x5 /* MX51_PAD_DISP2_DAT5__DISP2_DAT5 */
396 617 0x5 /* MX51_PAD_DISP2_DAT6__DISP2_DAT6 */
397 622 0x5 /* MX51_PAD_DISP2_DAT7__DISP2_DAT7 */
398 627 0x5 /* MX51_PAD_DISP2_DAT8__DISP2_DAT8 */
399 633 0x5 /* MX51_PAD_DISP2_DAT9__DISP2_DAT9 */
400 637 0x5 /* MX51_PAD_DISP2_DAT10__DISP2_DAT10 */
401 643 0x5 /* MX51_PAD_DISP2_DAT11__DISP2_DAT11 */
402 648 0x5 /* MX51_PAD_DISP2_DAT12__DISP2_DAT12 */
403 652 0x5 /* MX51_PAD_DISP2_DAT13__DISP2_DAT13 */
404 656 0x5 /* MX51_PAD_DISP2_DAT14__DISP2_DAT14 */
405 661 0x5 /* MX51_PAD_DISP2_DAT15__DISP2_DAT15 */
406 593 0x5 /* MX51_PAD_DI2_PIN2__DI2_PIN2 (hsync) */
407 595 0x5 /* MX51_PAD_DI2_PIN3__DI2_PIN3 (vsync) */
408 597 0x5 /* MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK */
409 599 0x5 /* MX51_PAD_DI_GP4__DI2_PIN15 */
410 >;
411 };
412 };
413
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]414 uart1 {
415 pinctrl_uart1_1: uart1grp-1 {
416 fsl,pins = <
417 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
418 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
419 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
420 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
421 >;
422 };
423 };
424
425 uart2 {
426 pinctrl_uart2_1: uart2grp-1 {
427 fsl,pins = <
428 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
429 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
430 >;
431 };
432 };
433
434 uart3 {
435 pinctrl_uart3_1: uart3grp-1 {
436 fsl,pins = <
437 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
438 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
439 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
440 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
441 >;
442 };
Laurent Cans1982d5b2013-01-20 23:55:29 +0100[diff] [blame]443
444 pinctrl_uart3_2: uart3grp-2 {
445 fsl,pins = <
446 434 0x1c5 /* MX51_PAD_UART3_RXD__UART3_RXD */
447 430 0x1c5 /* MX51_PAD_UART3_TXD__UART3_TXD */
448 >;
449 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]450 };
Liu Ying6012555c2013-01-03 20:37:33 +0800[diff] [blame]451
452 kpp {
453 pinctrl_kpp_1: kppgrp-1 {
454 fsl,pins = <
455 438 0xe0 /* MX51_PAD_KEY_ROW0__KEY_ROW0 */
456 439 0xe0 /* MX51_PAD_KEY_ROW1__KEY_ROW1 */
457 440 0xe0 /* MX51_PAD_KEY_ROW2__KEY_ROW2 */
458 441 0xe0 /* MX51_PAD_KEY_ROW3__KEY_ROW3 */
459 442 0xe8 /* MX51_PAD_KEY_COL0__KEY_COL0 */
460 444 0xe8 /* MX51_PAD_KEY_COL1__KEY_COL1 */
461 446 0xe8 /* MX51_PAD_KEY_COL2__KEY_COL2 */
462 448 0xe8 /* MX51_PAD_KEY_COL3__KEY_COL3 */
463 >;
464 };
465 };
Shawn Guob72cf102012-08-13 19:45:19 +0800[diff] [blame]466 };
467
Sascha Hauer82a618d2012-11-19 00:57:08 +0100[diff] [blame]468 pwm1: pwm@73fb4000 {
469 #pwm-cells = <2>;
470 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
471 reg = <0x73fb4000 0x4000>;
472 clocks = <&clks 37>, <&clks 38>;
473 clock-names = "ipg", "per";
474 interrupts = <61>;
475 };
476
477 pwm2: pwm@73fb8000 {
478 #pwm-cells = <2>;
479 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
480 reg = <0x73fb8000 0x4000>;
481 clocks = <&clks 39>, <&clks 40>;
482 clock-names = "ipg", "per";
483 interrupts = <94>;
484 };
485
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]486 uart1: serial@73fbc000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]487 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
488 reg = <0x73fbc000 0x4000>;
489 interrupts = <31>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]490 clocks = <&clks 28>, <&clks 29>;
491 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]492 status = "disabled";
493 };
494
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]495 uart2: serial@73fc0000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]496 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
497 reg = <0x73fc0000 0x4000>;
498 interrupts = <32>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]499 clocks = <&clks 30>, <&clks 31>;
500 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]501 status = "disabled";
502 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]503
504 clks: ccm@73fd4000{
505 compatible = "fsl,imx51-ccm";
506 reg = <0x73fd4000 0x4000>;
507 interrupts = <0 71 0x04 0 72 0x04>;
508 #clock-cells = <1>;
509 };
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]510 };
511
512 aips@80000000 { /* AIPS2 */
513 compatible = "fsl,aips-bus", "simple-bus";
514 #address-cells = <1>;
515 #size-cells = <1>;
516 reg = <0x80000000 0x10000000>;
517 ranges;
518
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]519 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]520 #address-cells = <1>;
521 #size-cells = <0>;
522 compatible = "fsl,imx51-ecspi";
523 reg = <0x83fac000 0x4000>;
524 interrupts = <37>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]525 clocks = <&clks 53>, <&clks 54>;
526 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]527 status = "disabled";
528 };
529
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]530 sdma: sdma@83fb0000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]531 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
532 reg = <0x83fb0000 0x4000>;
533 interrupts = <6>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]534 clocks = <&clks 56>, <&clks 56>;
535 clock-names = "ipg", "ahb";
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]536 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]537 };
538
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]539 cspi: cspi@83fc0000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]540 #address-cells = <1>;
541 #size-cells = <0>;
542 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
543 reg = <0x83fc0000 0x4000>;
544 interrupts = <38>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]545 clocks = <&clks 55>, <&clks 0>;
546 clock-names = "ipg", "per";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]547 status = "disabled";
548 };
549
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]550 i2c2: i2c@83fc4000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]551 #address-cells = <1>;
552 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]553 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]554 reg = <0x83fc4000 0x4000>;
555 interrupts = <63>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]556 clocks = <&clks 35>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]557 status = "disabled";
558 };
559
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]560 i2c1: i2c@83fc8000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]561 #address-cells = <1>;
562 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]563 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]564 reg = <0x83fc8000 0x4000>;
565 interrupts = <62>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]566 clocks = <&clks 34>;
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]567 status = "disabled";
568 };
569
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]570 ssi1: ssi@83fcc000 {
571 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
572 reg = <0x83fcc000 0x4000>;
573 interrupts = <29>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]574 clocks = <&clks 48>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]575 fsl,fifo-depth = <15>;
576 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
577 status = "disabled";
578 };
579
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]580 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]581 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
582 reg = <0x83fd0000 0x4000>;
583 status = "disabled";
584 };
585
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]586 nfc: nand@83fdb000 {
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]587 compatible = "fsl,imx51-nand";
588 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
589 interrupts = <8>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]590 clocks = <&clks 60>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]591 status = "disabled";
592 };
593
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]594 ssi3: ssi@83fe8000 {
595 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
596 reg = <0x83fe8000 0x4000>;
597 interrupts = <96>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]598 clocks = <&clks 50>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800[diff] [blame]599 fsl,fifo-depth = <15>;
600 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
601 status = "disabled";
602 };
603
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]604 fec: ethernet@83fec000 {
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]605 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
606 reg = <0x83fec000 0x4000>;
607 interrupts = <87>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200[diff] [blame]608 clocks = <&clks 42>, <&clks 42>, <&clks 42>;
609 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf31a2011-10-17 08:42:17 +0800[diff] [blame]610 status = "disabled";
611 };
612 };
613 };
614};