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Wu Zhangjin28c945c2010-06-01 18:29:04 +08001#
2# Loongson Processors' Support
3#
4
Wu Zhangjin28c945c2010-06-01 18:29:04 +08005
Jiaxun Yang268a2d62019-10-20 22:43:13 +08006cflags-$(CONFIG_CPU_LOONGSON64) += -Wa,--trap
Huacai Chene02e07e2019-01-15 16:04:54 +08007
8#
9# Some versions of binutils, not currently mainline as of 2019/02/04, support
10# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
Paul Burton7f56b1232019-10-01 21:53:40 +000011# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
Huacai Chene02e07e2019-01-15 16:04:54 +080012# description).
13#
14# We disable this in order to prevent the assembler meddling with the
15# instruction that labels refer to, ie. if we label an ll instruction:
16#
17# 1: ll v0, 0(a0)
18#
19# ...then with the assembler fix applied the label may actually point at a sync
20# instruction inserted by the assembler, and if we were using the label in an
21# exception table the table would no longer contain the address of the ll
22# instruction.
23#
24# Avoid this by explicitly disabling that assembler behaviour. If upstream
25# binutils does not merge support for the flag then we can revisit & remove
26# this later - for now it ensures vendor toolchains don't cause problems.
27#
Jiaxun Yang268a2d62019-10-20 22:43:13 +080028cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
Huacai Chene02e07e2019-01-15 16:04:54 +080029
Huacai Chen51881292016-01-21 21:09:48 +080030#
31# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
32# as MIPS64 R2; older versions as just R1. This leaves the possibility open
33# that GCC might generate R2 code for -march=loongson3a which then is rejected
34# by GAS. The cc-option can't probe for this behaviour so -march=loongson3a
35# can't easily be used safely within the kbuild framework.
36#
37ifeq ($(call cc-ifversion, -ge, 0409, y), y)
Huacai Chen820880c2016-03-17 20:41:06 +080038 ifeq ($(call ld-ifversion, -ge, 225000000, y), y)
Jiaxun Yang268a2d62019-10-20 22:43:13 +080039 cflags-$(CONFIG_CPU_LOONGSON64) += \
Huacai Chen51881292016-01-21 21:09:48 +080040 $(call cc-option,-march=loongson3a -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
41 else
Jiaxun Yang268a2d62019-10-20 22:43:13 +080042 cflags-$(CONFIG_CPU_LOONGSON64) += \
Huacai Chen51881292016-01-21 21:09:48 +080043 $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
44 endif
45else
Jiaxun Yang268a2d62019-10-20 22:43:13 +080046 cflags-$(CONFIG_CPU_LOONGSON64) += \
Huacai Chen51881292016-01-21 21:09:48 +080047 $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64)
48endif
49
Paul Burton2f2b4fd2019-10-10 18:54:03 +000050# Some -march= flags enable MMI instructions, and GCC complains about that
51# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
52cflags-y += $(call cc-option,-mno-loongson-mmi)
53
Wu Zhangjin28c945c2010-06-01 18:29:04 +080054#
55# Loongson Machines' Support
56#
57
Huacai Chen30ad29b2015-04-21 10:00:35 +080058platform-$(CONFIG_MACH_LOONGSON64) += loongson64/
59cflags-$(CONFIG_MACH_LOONGSON64) += -I$(srctree)/arch/mips/include/asm/mach-loongson64 -mno-branch-likely
Jiaxun Yang1bdb7b72019-10-20 23:01:35 +080060load-$(CONFIG_CPU_LOONGSON64) += 0xffffffff80200000