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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / b2661357df24b1c7b1838fa47a9b07ba7007c01a / . / arch / arm / boot / dts / omap34xx.dtsi
blob: ac4f8795b756f597356d5776475d811f93483e62 [file] [log] [blame]
Nishanth Menon1e633d72013-03-19 12:53:03 -0500[diff] [blame]1/*
2 * Device Tree Source for OMAP34xx/OMAP35xx SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Sakari Ailuse5211762015-03-19 01:50:23 +0200[diff] [blame]11#include <dt-bindings/media/omap3-isp.h>
12
Florian Vaussard98ef79572013-05-31 14:32:55 +0200[diff] [blame]13#include "omap3.dtsi"
Nishanth Menon1e633d72013-03-19 12:53:03 -0500[diff] [blame]14
15/ {
16 cpus {
Keerthya761d512017-03-09 13:35:55 +0530[diff] [blame]17 cpu: cpu@0 {
Nishanth Menon1e633d72013-03-19 12:53:03 -0500[diff] [blame]18 /* OMAP343x/OMAP35xx variants OPP1-5 */
19 operating-points = <
20 /* kHz uV */
21 125000 975000
22 250000 1075000
23 500000 1200000
24 550000 1270000
25 600000 1350000
26 >;
27 clock-latency = <300000>; /* From legacy driver */
28 };
29 };
Laurent Pinchart3d495382014-01-07 14:01:39 -0800[diff] [blame]30
Javier Martinez Canillasf515f812016-08-01 12:46:55 -0400[diff] [blame]31 ocp@68000000 {
Laurent Pinchart3d495382014-01-07 14:01:39 -0800[diff] [blame]32 omap3_pmx_core2: pinmux@480025d8 {
33 compatible = "ti,omap3-padconf", "pinctrl-single";
34 reg = <0x480025d8 0x24>;
35 #address-cells = <1>;
36 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]37 #pinctrl-cells = <1>;
Laurent Pinchart3d495382014-01-07 14:01:39 -0800[diff] [blame]38 #interrupt-cells = <1>;
39 interrupt-controller;
40 pinctrl-single,register-width = <16>;
41 pinctrl-single,function-mask = <0xff1f>;
42 };
Sakari Ailuse5211762015-03-19 01:50:23 +0200[diff] [blame]43
44 isp: isp@480bc000 {
45 compatible = "ti,omap3-isp";
46 reg = <0x480bc000 0x12fc
47 0x480bd800 0x017c>;
48 interrupts = <24>;
49 iommus = <&mmu_isp>;
Ivaylo Dimitrove180fea2016-04-16 09:20:28 +0300[diff] [blame]50 syscon = <&scm_conf 0x6c>;
Sakari Ailuse5211762015-03-19 01:50:23 +0200[diff] [blame]51 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
52 #clock-cells = <1>;
53 ports {
54 #address-cells = <1>;
55 #size-cells = <0>;
56 };
57 };
Pali Rohár12e47442015-12-26 00:32:25 +0100[diff] [blame]58
Keerthya761d512017-03-09 13:35:55 +0530[diff] [blame]59 bandgap: bandgap@48002524 {
Pali Rohár12e47442015-12-26 00:32:25 +0100[diff] [blame]60 reg = <0x48002524 0x4>;
61 compatible = "ti,omap34xx-bandgap";
62 #thermal-sensor-cells = <0>;
63 };
Laurent Pinchart3d495382014-01-07 14:01:39 -0800[diff] [blame]64 };
Keerthya761d512017-03-09 13:35:55 +0530[diff] [blame]65
66 thermal_zones: thermal-zones {
67 #include "omap3-cpu-thermal.dtsi"
68 };
Nishanth Menon1e633d72013-03-19 12:53:03 -0500[diff] [blame]69};
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]70
Sebastian Reichel782e25a2014-05-10 18:37:49 +0200[diff] [blame]71&ssi {
72 status = "ok";
73
74 clocks = <&ssi_ssr_fck>,
75 <&ssi_sst_fck>,
76 <&ssi_ick>;
77 clock-names = "ssi_ssr_fck",
78 "ssi_sst_fck",
79 "ssi_ick";
80};
81
Tero Kristo657fc112013-07-22 12:29:29 +0300[diff] [blame]82/include/ "omap34xx-omap36xx-clocks.dtsi"
83/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
Linus Torvaldsd30492a2014-01-28 18:44:53 -0800[diff] [blame]84/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"