Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 3 | #include <dt-bindings/input/input.h> |
Stephen Warren | 1bd0bd4 | 2012-10-17 16:38:21 -0600 | [diff] [blame] | 4 | #include "tegra20.dtsi" |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 5 | |
| 6 | / { |
| 7 | model = "Compulab TrimSlice board"; |
| 8 | compatible = "compulab,trimslice", "nvidia,tegra20"; |
| 9 | |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 10 | aliases { |
| 11 | rtc0 = "/i2c@7000c500/rtc@56"; |
| 12 | rtc1 = "/rtc@7000e000"; |
Olof Johansson | c4574aa | 2014-11-11 12:49:30 -0800 | [diff] [blame] | 13 | serial0 = &uarta; |
Stephen Warren | 553c0a2 | 2013-12-09 14:43:59 -0700 | [diff] [blame] | 14 | }; |
| 15 | |
Jon Hunter | f5bbb32 | 2016-02-09 13:51:59 +0000 | [diff] [blame] | 16 | chosen { |
| 17 | stdout-path = "serial0:115200n8"; |
| 18 | }; |
| 19 | |
Stephen Warren | f9eb26a | 2012-05-11 16:17:47 -0600 | [diff] [blame] | 20 | memory { |
Stephen Warren | 95decf8 | 2012-05-11 16:11:38 -0600 | [diff] [blame] | 21 | reg = <0x00000000 0x40000000>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 22 | }; |
| 23 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 24 | host1x@50000000 { |
| 25 | hdmi@54280000 { |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 26 | status = "okay"; |
| 27 | |
| 28 | vdd-supply = <&hdmi_vdd_reg>; |
| 29 | pll-supply = <&hdmi_pll_reg>; |
| 30 | |
| 31 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 32 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 33 | GPIO_ACTIVE_HIGH>; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 34 | }; |
| 35 | }; |
| 36 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 37 | pinmux@70000014 { |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 38 | pinctrl-names = "default"; |
| 39 | pinctrl-0 = <&state_default>; |
| 40 | |
| 41 | state_default: pinmux { |
| 42 | ata { |
| 43 | nvidia,pins = "ata"; |
| 44 | nvidia,function = "ide"; |
| 45 | }; |
| 46 | atb { |
| 47 | nvidia,pins = "atb", "gma"; |
| 48 | nvidia,function = "sdio4"; |
| 49 | }; |
| 50 | atc { |
| 51 | nvidia,pins = "atc", "gmb"; |
| 52 | nvidia,function = "nand"; |
| 53 | }; |
| 54 | atd { |
| 55 | nvidia,pins = "atd", "ate", "gme", "pta"; |
| 56 | nvidia,function = "gmi"; |
| 57 | }; |
| 58 | cdev1 { |
| 59 | nvidia,pins = "cdev1"; |
| 60 | nvidia,function = "plla_out"; |
| 61 | }; |
| 62 | cdev2 { |
| 63 | nvidia,pins = "cdev2"; |
| 64 | nvidia,function = "pllp_out4"; |
| 65 | }; |
| 66 | crtp { |
| 67 | nvidia,pins = "crtp"; |
| 68 | nvidia,function = "crt"; |
| 69 | }; |
| 70 | csus { |
| 71 | nvidia,pins = "csus"; |
| 72 | nvidia,function = "vi_sensor_clk"; |
| 73 | }; |
| 74 | dap1 { |
| 75 | nvidia,pins = "dap1"; |
| 76 | nvidia,function = "dap1"; |
| 77 | }; |
| 78 | dap2 { |
| 79 | nvidia,pins = "dap2"; |
| 80 | nvidia,function = "dap2"; |
| 81 | }; |
| 82 | dap3 { |
| 83 | nvidia,pins = "dap3"; |
| 84 | nvidia,function = "dap3"; |
| 85 | }; |
| 86 | dap4 { |
| 87 | nvidia,pins = "dap4"; |
| 88 | nvidia,function = "dap4"; |
| 89 | }; |
| 90 | ddc { |
| 91 | nvidia,pins = "ddc"; |
| 92 | nvidia,function = "i2c2"; |
| 93 | }; |
| 94 | dta { |
| 95 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 96 | nvidia,function = "vi"; |
| 97 | }; |
| 98 | dtf { |
| 99 | nvidia,pins = "dtf"; |
| 100 | nvidia,function = "i2c3"; |
| 101 | }; |
| 102 | gmc { |
| 103 | nvidia,pins = "gmc", "gmd"; |
| 104 | nvidia,function = "sflash"; |
| 105 | }; |
| 106 | gpu { |
| 107 | nvidia,pins = "gpu"; |
| 108 | nvidia,function = "uarta"; |
| 109 | }; |
| 110 | gpu7 { |
| 111 | nvidia,pins = "gpu7"; |
| 112 | nvidia,function = "rtck"; |
| 113 | }; |
| 114 | gpv { |
| 115 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 116 | nvidia,function = "pcie"; |
| 117 | }; |
| 118 | hdint { |
| 119 | nvidia,pins = "hdint"; |
| 120 | nvidia,function = "hdmi"; |
| 121 | }; |
| 122 | i2cp { |
| 123 | nvidia,pins = "i2cp"; |
| 124 | nvidia,function = "i2cp"; |
| 125 | }; |
| 126 | irrx { |
| 127 | nvidia,pins = "irrx", "irtx"; |
| 128 | nvidia,function = "uartb"; |
| 129 | }; |
| 130 | kbca { |
| 131 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 132 | "kbce", "kbcf"; |
| 133 | nvidia,function = "kbc"; |
| 134 | }; |
| 135 | lcsn { |
| 136 | nvidia,pins = "lcsn", "ld0", "ld1", "ld2", |
| 137 | "ld3", "ld4", "ld5", "ld6", "ld7", |
| 138 | "ld8", "ld9", "ld10", "ld11", "ld12", |
| 139 | "ld13", "ld14", "ld15", "ld16", "ld17", |
| 140 | "ldc", "ldi", "lhp0", "lhp1", "lhp2", |
| 141 | "lhs", "lm0", "lm1", "lpp", "lpw0", |
| 142 | "lpw1", "lpw2", "lsc0", "lsc1", "lsck", |
| 143 | "lsda", "lsdi", "lspi", "lvp0", "lvp1", |
| 144 | "lvs"; |
| 145 | nvidia,function = "displaya"; |
| 146 | }; |
| 147 | owc { |
| 148 | nvidia,pins = "owc", "uac"; |
| 149 | nvidia,function = "rsvd2"; |
| 150 | }; |
| 151 | pmc { |
| 152 | nvidia,pins = "pmc"; |
| 153 | nvidia,function = "pwr_on"; |
| 154 | }; |
| 155 | rm { |
| 156 | nvidia,pins = "rm"; |
| 157 | nvidia,function = "i2c1"; |
| 158 | }; |
| 159 | sdb { |
| 160 | nvidia,pins = "sdb", "sdc", "sdd"; |
| 161 | nvidia,function = "pwm"; |
| 162 | }; |
| 163 | sdio1 { |
| 164 | nvidia,pins = "sdio1"; |
| 165 | nvidia,function = "sdio1"; |
| 166 | }; |
| 167 | slxc { |
| 168 | nvidia,pins = "slxc", "slxd"; |
| 169 | nvidia,function = "sdio3"; |
| 170 | }; |
| 171 | spdi { |
| 172 | nvidia,pins = "spdi", "spdo"; |
| 173 | nvidia,function = "spdif"; |
| 174 | }; |
| 175 | spia { |
| 176 | nvidia,pins = "spia", "spib", "spic"; |
| 177 | nvidia,function = "spi2"; |
| 178 | }; |
| 179 | spid { |
| 180 | nvidia,pins = "spid", "spie", "spif"; |
| 181 | nvidia,function = "spi1"; |
| 182 | }; |
| 183 | spig { |
| 184 | nvidia,pins = "spig", "spih"; |
| 185 | nvidia,function = "spi2_alt"; |
| 186 | }; |
| 187 | uaa { |
| 188 | nvidia,pins = "uaa", "uab", "uda"; |
| 189 | nvidia,function = "ulpi"; |
| 190 | }; |
| 191 | uad { |
| 192 | nvidia,pins = "uad"; |
| 193 | nvidia,function = "irda"; |
| 194 | }; |
| 195 | uca { |
| 196 | nvidia,pins = "uca", "ucb"; |
| 197 | nvidia,function = "uartc"; |
| 198 | }; |
| 199 | conf_ata { |
| 200 | nvidia,pins = "ata", "atc", "atd", "ate", |
| 201 | "crtp", "dap2", "dap3", "dap4", "dta", |
| 202 | "dtb", "dtc", "dtd", "dte", "gmb", |
| 203 | "gme", "i2cp", "pta", "slxc", "slxd", |
| 204 | "spdi", "spdo", "uda"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 205 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 206 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 207 | }; |
| 208 | conf_atb { |
Stephen Warren | 563da21 | 2012-04-13 16:35:20 -0600 | [diff] [blame] | 209 | nvidia,pins = "atb", "cdev1", "cdev2", "dap1", |
| 210 | "gma", "gmc", "gmd", "gpu", "gpu7", |
| 211 | "gpv", "sdio1", "slxa", "slxk", "uac"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 212 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 213 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 214 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 215 | conf_ck32 { |
| 216 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 217 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 219 | }; |
Stephen Warren | 563da21 | 2012-04-13 16:35:20 -0600 | [diff] [blame] | 220 | conf_csus { |
| 221 | nvidia,pins = "csus", "spia", "spib", |
| 222 | "spid", "spif"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 223 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 224 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | 563da21 | 2012-04-13 16:35:20 -0600 | [diff] [blame] | 225 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 226 | conf_ddc { |
| 227 | nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 228 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 229 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 230 | }; |
| 231 | conf_hdint { |
| 232 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 233 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
| 234 | "lvp0", "pmc"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 235 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 236 | }; |
| 237 | conf_irrx { |
| 238 | nvidia,pins = "irrx", "irtx", "kbca", "kbcb", |
| 239 | "kbcc", "kbcd", "kbce", "kbcf", "owc", |
| 240 | "spic", "spie", "spig", "spih", "uaa", |
| 241 | "uab", "uad", "uca", "ucb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 242 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 243 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 244 | }; |
| 245 | conf_lc { |
| 246 | nvidia,pins = "lc", "ls"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 247 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 248 | }; |
| 249 | conf_ld0 { |
| 250 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 251 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 252 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 253 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 254 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 255 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
| 256 | "lvs", "sdb"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 257 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 258 | }; |
| 259 | conf_ld17_0 { |
| 260 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 261 | "ld23_22"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 262 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 263 | }; |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 264 | conf_spif { |
| 265 | nvidia,pins = "spif"; |
Laxman Dewangan | ba4104e | 2013-12-05 16:14:08 +0530 | [diff] [blame] | 266 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 268 | }; |
Stephen Warren | ecc295b | 2012-03-15 16:27:36 -0600 | [diff] [blame] | 269 | }; |
| 270 | }; |
| 271 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 272 | i2s@70002800 { |
| 273 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 274 | }; |
| 275 | |
| 276 | serial@70006000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 277 | status = "okay"; |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 278 | }; |
| 279 | |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 280 | dvi_ddc: i2c@7000c000 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 281 | status = "okay"; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 282 | clock-frequency = <100000>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 283 | }; |
| 284 | |
Stephen Warren | fea221e | 2012-11-12 12:51:22 -0700 | [diff] [blame] | 285 | spi@7000c380 { |
| 286 | status = "okay"; |
| 287 | spi-max-frequency = <48000000>; |
| 288 | spi-flash@0 { |
| 289 | compatible = "winbond,w25q80bl"; |
| 290 | reg = <0>; |
| 291 | spi-max-frequency = <48000000>; |
| 292 | }; |
| 293 | }; |
| 294 | |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 295 | hdmi_ddc: i2c@7000c400 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 296 | status = "okay"; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 297 | clock-frequency = <100000>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 298 | }; |
| 299 | |
| 300 | i2c@7000c500 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 301 | status = "okay"; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 302 | clock-frequency = <400000>; |
Stephen Warren | 081cc0a | 2012-04-27 09:22:44 -0600 | [diff] [blame] | 303 | |
Stephen Warren | 22bfe10 | 2012-04-27 13:24:03 -0600 | [diff] [blame] | 304 | codec: codec@1a { |
| 305 | compatible = "ti,tlv320aic23"; |
| 306 | reg = <0x1a>; |
| 307 | }; |
| 308 | |
Stephen Warren | 081cc0a | 2012-04-27 09:22:44 -0600 | [diff] [blame] | 309 | rtc@56 { |
| 310 | compatible = "emmicro,em3027"; |
| 311 | reg = <0x56>; |
| 312 | }; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 313 | }; |
| 314 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 315 | pmc@7000e400 { |
Joseph Lo | 47d2d63 | 2013-08-12 17:40:07 +0800 | [diff] [blame] | 316 | nvidia,suspend-mode = <1>; |
Joseph Lo | a44a019 | 2013-04-03 19:31:52 +0800 | [diff] [blame] | 317 | nvidia,cpu-pwr-good-time = <5000>; |
| 318 | nvidia,cpu-pwr-off-time = <5000>; |
| 319 | nvidia,core-pwr-good-time = <3845 3845>; |
| 320 | nvidia,core-pwr-off-time = <3875>; |
| 321 | nvidia,sys-clock-req-active-high; |
| 322 | }; |
| 323 | |
Rob Herring | 508d690 | 2017-03-21 21:03:06 -0500 | [diff] [blame] | 324 | pcie@80003000 { |
Thierry Reding | 1798efd | 2013-08-09 16:49:23 +0200 | [diff] [blame] | 325 | status = "okay"; |
Thierry Reding | cca8614 | 2014-05-28 16:49:12 +0200 | [diff] [blame] | 326 | |
| 327 | avdd-pex-supply = <&pci_vdd_reg>; |
| 328 | vdd-pex-supply = <&pci_vdd_reg>; |
| 329 | avdd-pex-pll-supply = <&pci_vdd_reg>; |
| 330 | avdd-plle-supply = <&pci_vdd_reg>; |
| 331 | vddio-pex-clk-supply = <&pci_clk_reg>; |
| 332 | |
Thierry Reding | 1798efd | 2013-08-09 16:49:23 +0200 | [diff] [blame] | 333 | pci@1,0 { |
| 334 | status = "okay"; |
| 335 | }; |
| 336 | }; |
| 337 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 338 | usb@c5000000 { |
| 339 | status = "okay"; |
Stephen Warren | 88950f3b | 2011-11-21 14:44:09 -0700 | [diff] [blame] | 340 | }; |
| 341 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 342 | usb-phy@c5000000 { |
| 343 | status = "okay"; |
| 344 | vbus-supply = <&vbus_reg>; |
| 345 | }; |
| 346 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 347 | usb@c5004000 { |
Stephen Warren | a6a3dd1 | 2012-07-25 14:02:43 -0600 | [diff] [blame] | 348 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 349 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 350 | GPIO_ACTIVE_LOW>; |
Venu Byravarasu | 9dffe3b | 2013-05-16 19:42:56 +0530 | [diff] [blame] | 351 | }; |
| 352 | |
| 353 | usb-phy@c5004000 { |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 354 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 355 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0) |
| 356 | GPIO_ACTIVE_LOW>; |
Stephen Warren | 31c1ec9 | 2011-11-21 14:44:10 -0700 | [diff] [blame] | 357 | }; |
| 358 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 359 | usb@c5008000 { |
| 360 | status = "okay"; |
Stephen Warren | 1292c12 | 2011-11-21 14:44:11 -0700 | [diff] [blame] | 361 | }; |
| 362 | |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 363 | usb-phy@c5008000 { |
| 364 | status = "okay"; |
| 365 | }; |
| 366 | |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 367 | sdhci@c8000000 { |
| 368 | status = "okay"; |
Rask Ingemann Lambertsen | a3e4863 | 2017-01-22 22:17:48 +0100 | [diff] [blame] | 369 | broken-cd; |
Arnd Bergmann | deb88cc | 2012-05-14 22:35:04 +0200 | [diff] [blame] | 370 | bus-width = <4>; |
Stephen Warren | 1292c12 | 2011-11-21 14:44:11 -0700 | [diff] [blame] | 371 | }; |
| 372 | |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 373 | sdhci@c8000600 { |
Stephen Warren | 2a5fdc9 | 2012-05-11 17:32:56 -0600 | [diff] [blame] | 374 | status = "okay"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 375 | cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>; |
| 376 | wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
Arnd Bergmann | deb88cc | 2012-05-14 22:35:04 +0200 | [diff] [blame] | 377 | bus-width = <4>; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 378 | }; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 379 | |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 380 | clocks { |
| 381 | compatible = "simple-bus"; |
| 382 | #address-cells = <1>; |
| 383 | #size-cells = <0>; |
| 384 | |
Stephen Warren | 58ecb23 | 2013-11-25 17:53:16 -0700 | [diff] [blame] | 385 | clk32k_in: clock@0 { |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 386 | compatible = "fixed-clock"; |
Thierry Reding | 4ec2e60 | 2016-06-10 18:55:24 +0200 | [diff] [blame] | 387 | reg = <0>; |
Joseph Lo | 7021d12 | 2013-04-03 19:31:27 +0800 | [diff] [blame] | 388 | #clock-cells = <0>; |
| 389 | clock-frequency = <32768>; |
| 390 | }; |
| 391 | }; |
| 392 | |
Joseph Lo | 5741a25 | 2013-04-03 19:31:48 +0800 | [diff] [blame] | 393 | gpio-keys { |
| 394 | compatible = "gpio-keys"; |
| 395 | |
| 396 | power { |
| 397 | label = "Power"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 398 | gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; |
Laxman Dewangan | 6bccbd5 | 2013-12-02 18:39:57 +0530 | [diff] [blame] | 399 | linux,code = <KEY_POWER>; |
Sudeep Holla | d1c04d3 | 2016-02-08 21:55:43 +0000 | [diff] [blame] | 400 | wakeup-source; |
Joseph Lo | 5741a25 | 2013-04-03 19:31:48 +0800 | [diff] [blame] | 401 | }; |
| 402 | }; |
| 403 | |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 404 | poweroff { |
| 405 | compatible = "gpio-poweroff"; |
Stephen Warren | 3325f1b | 2013-02-12 17:25:15 -0700 | [diff] [blame] | 406 | gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; |
Stephen Warren | bff1ea7 | 2012-12-06 14:23:52 -0700 | [diff] [blame] | 407 | }; |
| 408 | |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 409 | regulators { |
| 410 | compatible = "simple-bus"; |
| 411 | #address-cells = <1>; |
| 412 | #size-cells = <0>; |
| 413 | |
| 414 | hdmi_vdd_reg: regulator@0 { |
| 415 | compatible = "regulator-fixed"; |
| 416 | reg = <0>; |
| 417 | regulator-name = "avdd_hdmi"; |
| 418 | regulator-min-microvolt = <3300000>; |
| 419 | regulator-max-microvolt = <3300000>; |
| 420 | regulator-always-on; |
| 421 | }; |
| 422 | |
| 423 | hdmi_pll_reg: regulator@1 { |
| 424 | compatible = "regulator-fixed"; |
| 425 | reg = <1>; |
| 426 | regulator-name = "avdd_hdmi_pll"; |
| 427 | regulator-min-microvolt = <1800000>; |
| 428 | regulator-max-microvolt = <1800000>; |
| 429 | regulator-always-on; |
| 430 | }; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 431 | |
| 432 | vbus_reg: regulator@2 { |
| 433 | compatible = "regulator-fixed"; |
| 434 | reg = <2>; |
| 435 | regulator-name = "usb1_vbus"; |
| 436 | regulator-min-microvolt = <5000000>; |
| 437 | regulator-max-microvolt = <5000000>; |
Stephen Warren | 9f310de | 2013-07-01 15:07:05 -0600 | [diff] [blame] | 438 | enable-active-high; |
Stephen Warren | 23f95ef | 2013-08-01 12:26:01 -0600 | [diff] [blame] | 439 | gpio = <&gpio TEGRA_GPIO(V, 2) 0>; |
Stephen Warren | 30ca222 | 2013-08-20 14:00:13 -0600 | [diff] [blame] | 440 | regulator-always-on; |
| 441 | regulator-boot-on; |
Venu Byravarasu | 4c94c8b | 2013-05-16 19:42:57 +0530 | [diff] [blame] | 442 | }; |
Thierry Reding | 1798efd | 2013-08-09 16:49:23 +0200 | [diff] [blame] | 443 | |
| 444 | pci_clk_reg: regulator@3 { |
| 445 | compatible = "regulator-fixed"; |
| 446 | reg = <3>; |
| 447 | regulator-name = "pci_clk"; |
| 448 | regulator-min-microvolt = <3300000>; |
| 449 | regulator-max-microvolt = <3300000>; |
| 450 | regulator-always-on; |
| 451 | }; |
| 452 | |
| 453 | pci_vdd_reg: regulator@4 { |
| 454 | compatible = "regulator-fixed"; |
| 455 | reg = <4>; |
| 456 | regulator-name = "pci_vdd"; |
| 457 | regulator-min-microvolt = <1050000>; |
| 458 | regulator-max-microvolt = <1050000>; |
| 459 | regulator-always-on; |
| 460 | }; |
Thierry Reding | dced3e3 | 2012-09-20 10:39:20 +0200 | [diff] [blame] | 461 | }; |
| 462 | |
Stephen Warren | c04abb3 | 2012-05-11 17:03:26 -0600 | [diff] [blame] | 463 | sound { |
| 464 | compatible = "nvidia,tegra-audio-trimslice"; |
| 465 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 466 | nvidia,audio-codec = <&codec>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 467 | |
Hiroshi Doyu | 885a8cf | 2013-05-22 19:45:32 +0300 | [diff] [blame] | 468 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 469 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
| 470 | <&tegra_car TEGRA20_CLK_CDEV1>; |
Stephen Warren | f9cd2b3 | 2013-03-26 16:45:52 -0600 | [diff] [blame] | 471 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
Stephen Warren | aa607eb | 2012-04-12 15:46:49 -0600 | [diff] [blame] | 472 | }; |
Stephen Warren | a7db2c1 | 2011-10-25 02:01:28 +0000 | [diff] [blame] | 473 | }; |