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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / aef15dbaf43db2b8803f28b5d47ccaedbf32c962 / . / arch / arm / boot / dts / imx6qdl-gw52xx.dtsi
blob: 102219761b206e5e11af2071838dfae7a4fd7038 [file] [log] [blame]
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/ {
13 /* these are used by bootloader for disabling nodes */
14 aliases {
15 ethernet0 = &fec;
16 led0 = &led0;
17 led1 = &led1;
18 led2 = &led2;
19 nand = &gpmi;
20 ssi0 = &ssi1;
21 usb0 = &usbh1;
22 usb1 = &usbotg;
23 usdhc2 = &usdhc3;
24 };
25
26 chosen {
27 bootargs = "console=ttymxc1,115200";
28 };
29
30 leds {
31 compatible = "gpio-leds";
32
33 led0: user1 {
34 label = "user1";
35 gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
36 default-state = "on";
37 linux,default-trigger = "heartbeat";
38 };
39
40 led1: user2 {
41 label = "user2";
42 gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */
43 default-state = "off";
44 };
45
46 led2: user3 {
47 label = "user3";
48 gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */
49 default-state = "off";
50 };
51 };
52
53 memory {
54 reg = <0x10000000 0x20000000>;
55 };
56
57 pps {
58 compatible = "pps-gpio";
59 gpios = <&gpio1 26 0>;
60 status = "okay";
61 };
62
63 regulators {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 reg_1p0v: regulator@0 {
69 compatible = "regulator-fixed";
70 reg = <0>;
71 regulator-name = "1P0V";
72 regulator-min-microvolt = <1000000>;
73 regulator-max-microvolt = <1000000>;
74 regulator-always-on;
75 };
76
77 /* remove this fixed regulator once ltc3676__sw2 driver available */
78 reg_1p8v: regulator@1 {
79 compatible = "regulator-fixed";
80 reg = <1>;
81 regulator-name = "1P8V";
82 regulator-min-microvolt = <1800000>;
83 regulator-max-microvolt = <1800000>;
84 regulator-always-on;
85 };
86
87 reg_3p3v: regulator@2 {
88 compatible = "regulator-fixed";
89 reg = <2>;
90 regulator-name = "3P3V";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 regulator-always-on;
94 };
95
96 reg_5p0v: regulator@3 {
97 compatible = "regulator-fixed";
98 reg = <3>;
99 regulator-name = "5P0V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-always-on;
103 };
104
105 reg_usb_otg_vbus: regulator@4 {
106 compatible = "regulator-fixed";
107 reg = <4>;
108 regulator-name = "usb_otg_vbus";
109 regulator-min-microvolt = <5000000>;
110 regulator-max-microvolt = <5000000>;
111 gpio = <&gpio3 22 0>;
112 enable-active-high;
113 };
114 };
115
116 sound {
117 compatible = "fsl,imx6q-sabrelite-sgtl5000",
118 "fsl,imx-audio-sgtl5000";
119 model = "imx6q-sabrelite-sgtl5000";
120 ssi-controller = <&ssi1>;
121 audio-codec = <&codec>;
122 audio-routing =
123 "MIC_IN", "Mic Jack",
124 "Mic Jack", "Mic Bias",
125 "Headphone Jack", "HP_OUT";
126 mux-int-port = <1>;
127 mux-ext-port = <4>;
128 };
129};
130
131&audmux {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_audmux>;
134 status = "okay";
135};
136
137&fec {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_enet>;
140 phy-mode = "rgmii";
141 phy-reset-gpios = <&gpio1 30 0>;
142 status = "okay";
143};
144
145&gpmi {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_gpmi_nand>;
148 status = "okay";
149};
150
Tim Harveyaef15db2014-04-23 00:47:51 -0700[diff] [blame^]151&hdmi {
152 ddc-i2c-bus = <&i2c3>;
153 status = "okay";
154};
155
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]156&i2c1 {
157 clock-frequency = <100000>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_i2c1>;
160 status = "okay";
161
162 eeprom1: eeprom@50 {
163 compatible = "atmel,24c02";
164 reg = <0x50>;
165 pagesize = <16>;
166 };
167
168 eeprom2: eeprom@51 {
169 compatible = "atmel,24c02";
170 reg = <0x51>;
171 pagesize = <16>;
172 };
173
174 eeprom3: eeprom@52 {
175 compatible = "atmel,24c02";
176 reg = <0x52>;
177 pagesize = <16>;
178 };
179
180 eeprom4: eeprom@53 {
181 compatible = "atmel,24c02";
182 reg = <0x53>;
183 pagesize = <16>;
184 };
185
186 gpio: pca9555@23 {
187 compatible = "nxp,pca9555";
188 reg = <0x23>;
189 gpio-controller;
190 #gpio-cells = <2>;
191 };
192
193 hwmon: gsc@29 {
194 compatible = "gw,gsp";
195 reg = <0x29>;
196 };
197
198 rtc: ds1672@68 {
199 compatible = "dallas,ds1672";
200 reg = <0x68>;
201 };
202};
203
204&i2c2 {
205 clock-frequency = <100000>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_i2c2>;
208 status = "okay";
209
210 pciswitch: pex8609@3f {
211 compatible = "plx,pex8609";
212 reg = <0x3f>;
213 };
214
215 pmic: ltc3676@3c {
216 compatible = "ltc,ltc3676";
217 reg = <0x3c>;
218
219 regulators {
220 sw1_reg: ltc3676__sw1 {
221 regulator-min-microvolt = <1175000>;
222 regulator-max-microvolt = <1175000>;
223 regulator-boot-on;
224 regulator-always-on;
225 };
226
227 sw2_reg: ltc3676__sw2 {
228 regulator-min-microvolt = <1800000>;
229 regulator-max-microvolt = <1800000>;
230 regulator-boot-on;
231 regulator-always-on;
232 };
233
234 sw3_reg: ltc3676__sw3 {
235 regulator-min-microvolt = <1175000>;
236 regulator-max-microvolt = <1175000>;
237 regulator-boot-on;
238 regulator-always-on;
239 };
240
241 sw4_reg: ltc3676__sw4 {
242 regulator-min-microvolt = <1500000>;
243 regulator-max-microvolt = <1500000>;
244 regulator-boot-on;
245 regulator-always-on;
246 };
247
248 ldo2_reg: ltc3676__ldo2 {
249 regulator-min-microvolt = <2500000>;
250 regulator-max-microvolt = <2500000>;
251 regulator-boot-on;
252 regulator-always-on;
253 };
254
255 ldo3_reg: ltc3676__ldo3 {
256 regulator-min-microvolt = <1800000>;
257 regulator-max-microvolt = <1800000>;
258 regulator-boot-on;
259 regulator-always-on;
260 };
261
262 ldo4_reg: ltc3676__ldo4 {
263 regulator-min-microvolt = <3000000>;
264 regulator-max-microvolt = <3000000>;
265 };
266 };
267 };
268};
269
270&i2c3 {
271 clock-frequency = <100000>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_i2c3>;
274 status = "okay";
275
276 accelerometer: fxos8700@1e {
277 compatible = "fsl,fxos8700";
278 reg = <0x13>;
279 };
280
281 codec: sgtl5000@0a {
282 compatible = "fsl,sgtl5000";
283 reg = <0x0a>;
284 clocks = <&clks 169>;
285 VDDA-supply = <&reg_1p8v>;
286 VDDIO-supply = <&reg_3p3v>;
287 };
288
289 touchscreen: egalax_ts@04 {
290 compatible = "eeti,egalax_ts";
291 reg = <0x04>;
292 interrupt-parent = <&gpio7>;
293 interrupts = <12 2>; /* gpio7_12 active low */
294 wakeup-gpios = <&gpio7 12 0>;
295 };
296
297 videoin: adv7180@20 {
298 compatible = "adi,adv7180";
299 reg = <0x20>;
300 };
301};
302
303&iomuxc {
304 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_hog>;
306
307 imx6qdl-gw52xx {
308 pinctrl_hog: hoggrp {
309 fsl,pins = <
310 MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */
311 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */
312 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
313 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */
314 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */
315 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */
316 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */
317 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */
318 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */
319 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */
320 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */
321 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */
322 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */
323 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */
324 MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */
325 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */
326 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */
327 >;
328 };
329
330 pinctrl_audmux: audmuxgrp {
331 fsl,pins = <
332 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
333 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
334 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
335 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
336 >;
337 };
338
339 pinctrl_enet: enetgrp {
340 fsl,pins = <
341 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
342 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
343 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
344 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
345 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
346 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
347 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
348 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
349 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
350 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
351 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
352 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
353 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
354 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
355 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
356 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
357 >;
358 };
359
360 pinctrl_gpmi_nand: gpminandgrp {
361 fsl,pins = <
362 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
363 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
364 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
365 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
366 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
367 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
368 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
369 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
370 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
371 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
372 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
373 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
374 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
375 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
376 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
377 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
378 >;
379 };
380
381 pinctrl_i2c1: i2c1grp {
382 fsl,pins = <
383 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
384 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
385 >;
386 };
387
388 pinctrl_i2c2: i2c2grp {
389 fsl,pins = <
390 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
391 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
392 >;
393 };
394
395 pinctrl_i2c3: i2c3grp {
396 fsl,pins = <
397 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
398 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
399 >;
400 };
401
402 pinctrl_uart1: uart1grp {
403 fsl,pins = <
404 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
405 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
406 >;
407 };
408
409 pinctrl_uart2: uart2grp {
410 fsl,pins = <
411 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
412 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
413 >;
414 };
415
416 pinctrl_uart5: uart5grp {
417 fsl,pins = <
418 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
419 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
420 >;
421 };
422
423 pinctrl_usbotg: usbotggrp {
424 fsl,pins = <
425 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
426 >;
427 };
428
429 pinctrl_usdhc3: usdhc3grp {
430 fsl,pins = <
431 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
432 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
433 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
434 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
435 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
436 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
437 >;
438 };
439 };
440};
441
442&ldb {
443 status = "okay";
Tim Harveye3946fe2014-02-07 15:24:56 +0800[diff] [blame]444};
445
446&pcie {
447 reset-gpio = <&gpio1 29 0>;
448 status = "okay";
449};
450
451&ssi1 {
452 fsl,mode = "i2s-slave";
453 status = "okay";
454};
455
456&uart1 {
457 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_uart1>;
459 status = "okay";
460};
461
462&uart2 {
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_uart2>;
465 status = "okay";
466};
467
468&uart5 {
469 pinctrl-names = "default";
470 pinctrl-0 = <&pinctrl_uart5>;
471 status = "okay";
472};
473
474&usbotg {
475 vbus-supply = <&reg_usb_otg_vbus>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pinctrl_usbotg>;
478 disable-over-current;
479 status = "okay";
480};
481
482&usbh1 {
483 status = "okay";
484};
485
486&usdhc3 {
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_usdhc3>;
489 cd-gpios = <&gpio7 0 0>;
490 vmmc-supply = <&reg_3p3v>;
491 status = "okay";
492};