Thomas Gleixner | 1802d0b | 2019-05-27 08:55:21 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Pinctrl driver for Rockchip SoCs |
| 4 | * |
| 5 | * Copyright (c) 2013 MundoReader S.L. |
| 6 | * Author: Heiko Stuebner <heiko@sntech.de> |
| 7 | * |
| 8 | * With some ideas taken from pinctrl-samsung: |
| 9 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. |
| 10 | * http://www.samsung.com |
| 11 | * Copyright (c) 2012 Linaro Ltd |
Alexander A. Klimov | 3e3f742 | 2020-07-13 20:35:41 +0200 | [diff] [blame] | 12 | * https://www.linaro.org |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 13 | * |
| 14 | * and pinctrl-at91: |
| 15 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
Paul Gortmaker | 2f43620 | 2016-08-23 17:19:42 -0400 | [diff] [blame] | 18 | #include <linux/init.h> |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/bitops.h> |
Linus Walleij | 1c5fb66 | 2018-09-13 13:58:21 +0200 | [diff] [blame] | 22 | #include <linux/gpio/driver.h> |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 23 | #include <linux/of_address.h> |
| 24 | #include <linux/of_irq.h> |
| 25 | #include <linux/pinctrl/machine.h> |
| 26 | #include <linux/pinctrl/pinconf.h> |
| 27 | #include <linux/pinctrl/pinctrl.h> |
| 28 | #include <linux/pinctrl/pinmux.h> |
| 29 | #include <linux/pinctrl/pinconf-generic.h> |
| 30 | #include <linux/irqchip/chained_irq.h> |
Heiko Stübner | 7e865ab | 2013-07-23 13:34:20 +0200 | [diff] [blame] | 31 | #include <linux/clk.h> |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 32 | #include <linux/regmap.h> |
Heiko Stübner | 14dee86 | 2014-05-05 13:59:09 +0200 | [diff] [blame] | 33 | #include <linux/mfd/syscon.h> |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 34 | #include <dt-bindings/pinctrl/rockchip.h> |
| 35 | |
| 36 | #include "core.h" |
| 37 | #include "pinconf.h" |
| 38 | |
| 39 | /* GPIO control registers */ |
| 40 | #define GPIO_SWPORT_DR 0x00 |
| 41 | #define GPIO_SWPORT_DDR 0x04 |
| 42 | #define GPIO_INTEN 0x30 |
| 43 | #define GPIO_INTMASK 0x34 |
| 44 | #define GPIO_INTTYPE_LEVEL 0x38 |
| 45 | #define GPIO_INT_POLARITY 0x3c |
| 46 | #define GPIO_INT_STATUS 0x40 |
| 47 | #define GPIO_INT_RAWSTATUS 0x44 |
| 48 | #define GPIO_DEBOUNCE 0x48 |
| 49 | #define GPIO_PORTS_EOI 0x4c |
| 50 | #define GPIO_EXT_PORT 0x50 |
| 51 | #define GPIO_LS_SYNC 0x60 |
| 52 | |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 53 | enum rockchip_pinctrl_type { |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 54 | PX30, |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 55 | RV1108, |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 56 | RK2928, |
| 57 | RK3066B, |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 58 | RK3128, |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 59 | RK3188, |
Heiko Stübner | 66d750e | 2014-07-20 01:49:17 +0200 | [diff] [blame] | 60 | RK3288, |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 61 | RK3308, |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 62 | RK3368, |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 63 | RK3399, |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 64 | }; |
| 65 | |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 66 | /* |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 67 | * Encode variants of iomux registers into a type variable |
| 68 | */ |
| 69 | #define IOMUX_GPIO_ONLY BIT(0) |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 70 | #define IOMUX_WIDTH_4BIT BIT(1) |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 71 | #define IOMUX_SOURCE_PMU BIT(2) |
Heiko Stübner | 62f4922 | 2014-06-16 01:37:49 +0200 | [diff] [blame] | 72 | #define IOMUX_UNROUTED BIT(3) |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 73 | #define IOMUX_WIDTH_3BIT BIT(4) |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 74 | #define IOMUX_WIDTH_2BIT BIT(5) |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 75 | |
| 76 | /** |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 77 | * struct rockchip_iomux |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 78 | * @type: iomux variant using IOMUX_* constants |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 79 | * @offset: if initialized to -1 it will be autocalculated, by specifying |
| 80 | * an initial offset value the relevant source offset can be reset |
| 81 | * to a new value for autocalculating the following iomux registers. |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 82 | */ |
| 83 | struct rockchip_iomux { |
| 84 | int type; |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 85 | int offset; |
Heiko Stübner | 65fca61 | 2013-10-16 01:07:49 +0200 | [diff] [blame] | 86 | }; |
| 87 | |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 88 | /* |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 89 | * enum type index corresponding to rockchip_perpin_drv_list arrays index. |
| 90 | */ |
| 91 | enum rockchip_pin_drv_type { |
| 92 | DRV_TYPE_IO_DEFAULT = 0, |
| 93 | DRV_TYPE_IO_1V8_OR_3V0, |
| 94 | DRV_TYPE_IO_1V8_ONLY, |
| 95 | DRV_TYPE_IO_1V8_3V0_AUTO, |
| 96 | DRV_TYPE_IO_3V3_ONLY, |
| 97 | DRV_TYPE_MAX |
| 98 | }; |
| 99 | |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 100 | /* |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 101 | * enum type index corresponding to rockchip_pull_list arrays index. |
| 102 | */ |
| 103 | enum rockchip_pin_pull_type { |
| 104 | PULL_TYPE_IO_DEFAULT = 0, |
| 105 | PULL_TYPE_IO_1V8_ONLY, |
| 106 | PULL_TYPE_MAX |
| 107 | }; |
| 108 | |
| 109 | /** |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 110 | * struct rockchip_drv |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 111 | * @drv_type: drive strength variant using rockchip_perpin_drv_type |
| 112 | * @offset: if initialized to -1 it will be autocalculated, by specifying |
| 113 | * an initial offset value the relevant source offset can be reset |
| 114 | * to a new value for autocalculating the following drive strength |
| 115 | * registers. if used chips own cal_drv func instead to calculate |
| 116 | * registers offset, the variant could be ignored. |
| 117 | */ |
| 118 | struct rockchip_drv { |
| 119 | enum rockchip_pin_drv_type drv_type; |
| 120 | int offset; |
| 121 | }; |
| 122 | |
| 123 | /** |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 124 | * struct rockchip_pin_bank |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 125 | * @reg_base: register base of the gpio bank |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 126 | * @regmap_pull: optional separate register for additional pull settings |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 127 | * @clk: clock of the gpio bank |
| 128 | * @irq: interrupt of the gpio bank |
Doug Anderson | 5ae0c7a | 2015-01-26 08:24:03 -0800 | [diff] [blame] | 129 | * @saved_masks: Saved content of GPIO_INTEN at suspend time. |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 130 | * @pin_base: first pin number |
| 131 | * @nr_pins: number of pins in this bank |
| 132 | * @name: name of the bank |
| 133 | * @bank_num: number of the bank, to account for holes |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 134 | * @iomux: array describing the 4 iomux sources of the bank |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 135 | * @drv: array describing the 4 drive strength sources of the bank |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 136 | * @pull_type: array describing the 4 pull type sources of the bank |
Markus Elfring | 85dc397 | 2017-12-23 22:22:54 +0100 | [diff] [blame] | 137 | * @valid: is all necessary information present |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 138 | * @of_node: dt node of this bank |
| 139 | * @drvdata: common pinctrl basedata |
| 140 | * @domain: irqdomain of the gpio bank |
| 141 | * @gpio_chip: gpiolib chip |
| 142 | * @grange: gpio range |
| 143 | * @slock: spinlock for the gpio bank |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 144 | * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode |
| 145 | * @recalced_mask: bit mask to indicate a need to recalulate the mask |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 146 | * @route_mask: bits describing the routing pins of per bank |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 147 | */ |
| 148 | struct rockchip_pin_bank { |
| 149 | void __iomem *reg_base; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 150 | struct regmap *regmap_pull; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 151 | struct clk *clk; |
| 152 | int irq; |
Doug Anderson | 5ae0c7a | 2015-01-26 08:24:03 -0800 | [diff] [blame] | 153 | u32 saved_masks; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 154 | u32 pin_base; |
| 155 | u8 nr_pins; |
| 156 | char *name; |
| 157 | u8 bank_num; |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 158 | struct rockchip_iomux iomux[4]; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 159 | struct rockchip_drv drv[4]; |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 160 | enum rockchip_pin_pull_type pull_type[4]; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 161 | bool valid; |
| 162 | struct device_node *of_node; |
| 163 | struct rockchip_pinctrl *drvdata; |
| 164 | struct irq_domain *domain; |
| 165 | struct gpio_chip gpio_chip; |
| 166 | struct pinctrl_gpio_range grange; |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 167 | raw_spinlock_t slock; |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 168 | u32 toggle_edge_mode; |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 169 | u32 recalced_mask; |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 170 | u32 route_mask; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | #define PIN_BANK(id, pins, label) \ |
| 174 | { \ |
| 175 | .bank_num = id, \ |
| 176 | .nr_pins = pins, \ |
| 177 | .name = label, \ |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 178 | .iomux = { \ |
| 179 | { .offset = -1 }, \ |
| 180 | { .offset = -1 }, \ |
| 181 | { .offset = -1 }, \ |
| 182 | { .offset = -1 }, \ |
| 183 | }, \ |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 184 | } |
| 185 | |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 186 | #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ |
| 187 | { \ |
| 188 | .bank_num = id, \ |
| 189 | .nr_pins = pins, \ |
| 190 | .name = label, \ |
| 191 | .iomux = { \ |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 192 | { .type = iom0, .offset = -1 }, \ |
| 193 | { .type = iom1, .offset = -1 }, \ |
| 194 | { .type = iom2, .offset = -1 }, \ |
| 195 | { .type = iom3, .offset = -1 }, \ |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 196 | }, \ |
| 197 | } |
| 198 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 199 | #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ |
| 200 | { \ |
| 201 | .bank_num = id, \ |
| 202 | .nr_pins = pins, \ |
| 203 | .name = label, \ |
| 204 | .iomux = { \ |
| 205 | { .offset = -1 }, \ |
| 206 | { .offset = -1 }, \ |
| 207 | { .offset = -1 }, \ |
| 208 | { .offset = -1 }, \ |
| 209 | }, \ |
| 210 | .drv = { \ |
| 211 | { .drv_type = type0, .offset = -1 }, \ |
| 212 | { .drv_type = type1, .offset = -1 }, \ |
| 213 | { .drv_type = type2, .offset = -1 }, \ |
| 214 | { .drv_type = type3, .offset = -1 }, \ |
| 215 | }, \ |
| 216 | } |
| 217 | |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 218 | #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \ |
| 219 | drv2, drv3, pull0, pull1, \ |
| 220 | pull2, pull3) \ |
| 221 | { \ |
| 222 | .bank_num = id, \ |
| 223 | .nr_pins = pins, \ |
| 224 | .name = label, \ |
| 225 | .iomux = { \ |
| 226 | { .offset = -1 }, \ |
| 227 | { .offset = -1 }, \ |
| 228 | { .offset = -1 }, \ |
| 229 | { .offset = -1 }, \ |
| 230 | }, \ |
| 231 | .drv = { \ |
| 232 | { .drv_type = drv0, .offset = -1 }, \ |
| 233 | { .drv_type = drv1, .offset = -1 }, \ |
| 234 | { .drv_type = drv2, .offset = -1 }, \ |
| 235 | { .drv_type = drv3, .offset = -1 }, \ |
| 236 | }, \ |
| 237 | .pull_type[0] = pull0, \ |
| 238 | .pull_type[1] = pull1, \ |
| 239 | .pull_type[2] = pull2, \ |
| 240 | .pull_type[3] = pull3, \ |
| 241 | } |
| 242 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 243 | #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \ |
| 244 | iom2, iom3, drv0, drv1, drv2, \ |
| 245 | drv3, offset0, offset1, \ |
| 246 | offset2, offset3) \ |
| 247 | { \ |
| 248 | .bank_num = id, \ |
| 249 | .nr_pins = pins, \ |
| 250 | .name = label, \ |
| 251 | .iomux = { \ |
| 252 | { .type = iom0, .offset = -1 }, \ |
| 253 | { .type = iom1, .offset = -1 }, \ |
| 254 | { .type = iom2, .offset = -1 }, \ |
| 255 | { .type = iom3, .offset = -1 }, \ |
| 256 | }, \ |
| 257 | .drv = { \ |
| 258 | { .drv_type = drv0, .offset = offset0 }, \ |
| 259 | { .drv_type = drv1, .offset = offset1 }, \ |
| 260 | { .drv_type = drv2, .offset = offset2 }, \ |
| 261 | { .drv_type = drv3, .offset = offset3 }, \ |
| 262 | }, \ |
| 263 | } |
| 264 | |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 265 | #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \ |
| 266 | label, iom0, iom1, iom2, \ |
| 267 | iom3, drv0, drv1, drv2, \ |
| 268 | drv3, offset0, offset1, \ |
| 269 | offset2, offset3, pull0, \ |
| 270 | pull1, pull2, pull3) \ |
| 271 | { \ |
| 272 | .bank_num = id, \ |
| 273 | .nr_pins = pins, \ |
| 274 | .name = label, \ |
| 275 | .iomux = { \ |
| 276 | { .type = iom0, .offset = -1 }, \ |
| 277 | { .type = iom1, .offset = -1 }, \ |
| 278 | { .type = iom2, .offset = -1 }, \ |
| 279 | { .type = iom3, .offset = -1 }, \ |
| 280 | }, \ |
| 281 | .drv = { \ |
| 282 | { .drv_type = drv0, .offset = offset0 }, \ |
| 283 | { .drv_type = drv1, .offset = offset1 }, \ |
| 284 | { .drv_type = drv2, .offset = offset2 }, \ |
| 285 | { .drv_type = drv3, .offset = offset3 }, \ |
| 286 | }, \ |
| 287 | .pull_type[0] = pull0, \ |
| 288 | .pull_type[1] = pull1, \ |
| 289 | .pull_type[2] = pull2, \ |
| 290 | .pull_type[3] = pull3, \ |
| 291 | } |
| 292 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 293 | /** |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 294 | * struct rockchip_mux_recalced_data: represent a pin iomux data. |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 295 | * @num: bank number. |
| 296 | * @pin: pin number. |
| 297 | * @bit: index at register. |
| 298 | * @reg: register offset. |
| 299 | * @mask: mask bit |
| 300 | */ |
| 301 | struct rockchip_mux_recalced_data { |
| 302 | u8 num; |
| 303 | u8 pin; |
David Wu | 12b8f01 | 2017-08-23 16:00:07 +0800 | [diff] [blame] | 304 | u32 reg; |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 305 | u8 bit; |
| 306 | u8 mask; |
| 307 | }; |
| 308 | |
Heiko Stuebner | 51ff47a | 2018-11-11 22:00:46 +0100 | [diff] [blame] | 309 | enum rockchip_mux_route_location { |
| 310 | ROCKCHIP_ROUTE_SAME = 0, |
| 311 | ROCKCHIP_ROUTE_PMU, |
| 312 | ROCKCHIP_ROUTE_GRF, |
| 313 | }; |
| 314 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 315 | /** |
| 316 | * struct rockchip_mux_recalced_data: represent a pin iomux data. |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 317 | * @bank_num: bank number. |
| 318 | * @pin: index at register or used to calc index. |
| 319 | * @func: the min pin. |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 320 | * @route_location: the mux route location (same, pmu, grf). |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 321 | * @route_offset: the max pin. |
| 322 | * @route_val: the register offset. |
| 323 | */ |
| 324 | struct rockchip_mux_route_data { |
| 325 | u8 bank_num; |
| 326 | u8 pin; |
| 327 | u8 func; |
Heiko Stuebner | 51ff47a | 2018-11-11 22:00:46 +0100 | [diff] [blame] | 328 | enum rockchip_mux_route_location route_location; |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 329 | u32 route_offset; |
| 330 | u32 route_val; |
| 331 | }; |
| 332 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 333 | struct rockchip_pin_ctrl { |
| 334 | struct rockchip_pin_bank *pin_banks; |
| 335 | u32 nr_banks; |
| 336 | u32 nr_pins; |
| 337 | char *label; |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 338 | enum rockchip_pinctrl_type type; |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 339 | int grf_mux_offset; |
| 340 | int pmu_mux_offset; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 341 | int grf_drv_offset; |
| 342 | int pmu_drv_offset; |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 343 | struct rockchip_mux_recalced_data *iomux_recalced; |
| 344 | u32 niomux_recalced; |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 345 | struct rockchip_mux_route_data *iomux_routes; |
| 346 | u32 niomux_routes; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 347 | |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 348 | void (*pull_calc_reg)(struct rockchip_pin_bank *bank, |
| 349 | int pin_num, struct regmap **regmap, |
| 350 | int *reg, u8 *bit); |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 351 | void (*drv_calc_reg)(struct rockchip_pin_bank *bank, |
| 352 | int pin_num, struct regmap **regmap, |
| 353 | int *reg, u8 *bit); |
david.wu | e3b357d | 2017-03-02 15:11:23 +0800 | [diff] [blame] | 354 | int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, |
| 355 | int pin_num, struct regmap **regmap, |
| 356 | int *reg, u8 *bit); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | struct rockchip_pin_config { |
| 360 | unsigned int func; |
| 361 | unsigned long *configs; |
| 362 | unsigned int nconfigs; |
| 363 | }; |
| 364 | |
| 365 | /** |
| 366 | * struct rockchip_pin_group: represent group of pins of a pinmux function. |
| 367 | * @name: name of the pin group, used to lookup the group. |
| 368 | * @pins: the pins included in this group. |
| 369 | * @npins: number of pins included in this group. |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 370 | * @data: local pin configuration |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 371 | */ |
| 372 | struct rockchip_pin_group { |
| 373 | const char *name; |
| 374 | unsigned int npins; |
| 375 | unsigned int *pins; |
| 376 | struct rockchip_pin_config *data; |
| 377 | }; |
| 378 | |
| 379 | /** |
| 380 | * struct rockchip_pmx_func: represent a pin function. |
| 381 | * @name: name of the pin function, used to lookup the function. |
| 382 | * @groups: one or more names of pin groups that provide this function. |
Lee Jones | e1524ea | 2020-07-13 15:49:24 +0100 | [diff] [blame] | 383 | * @ngroups: number of groups included in @groups. |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 384 | */ |
| 385 | struct rockchip_pmx_func { |
| 386 | const char *name; |
| 387 | const char **groups; |
| 388 | u8 ngroups; |
| 389 | }; |
| 390 | |
| 391 | struct rockchip_pinctrl { |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 392 | struct regmap *regmap_base; |
Heiko Stübner | bfc7a42 | 2014-05-05 13:58:00 +0200 | [diff] [blame] | 393 | int reg_size; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 394 | struct regmap *regmap_pull; |
Heiko Stübner | 14dee86 | 2014-05-05 13:59:09 +0200 | [diff] [blame] | 395 | struct regmap *regmap_pmu; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 396 | struct device *dev; |
| 397 | struct rockchip_pin_ctrl *ctrl; |
| 398 | struct pinctrl_desc pctl; |
| 399 | struct pinctrl_dev *pctl_dev; |
| 400 | struct rockchip_pin_group *groups; |
| 401 | unsigned int ngroups; |
| 402 | struct rockchip_pmx_func *functions; |
| 403 | unsigned int nfunctions; |
| 404 | }; |
| 405 | |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 406 | static struct regmap_config rockchip_regmap_config = { |
| 407 | .reg_bits = 32, |
| 408 | .val_bits = 32, |
| 409 | .reg_stride = 4, |
| 410 | }; |
| 411 | |
Arnd Bergmann | 56411f3 | 2016-06-13 17:18:34 +0200 | [diff] [blame] | 412 | static inline const struct rockchip_pin_group *pinctrl_name_to_group( |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 413 | const struct rockchip_pinctrl *info, |
| 414 | const char *name) |
| 415 | { |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 416 | int i; |
| 417 | |
| 418 | for (i = 0; i < info->ngroups; i++) { |
Axel Lin | 1cb9539 | 2013-08-21 10:28:50 +0800 | [diff] [blame] | 419 | if (!strcmp(info->groups[i].name, name)) |
| 420 | return &info->groups[i]; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 421 | } |
| 422 | |
Axel Lin | 1cb9539 | 2013-08-21 10:28:50 +0800 | [diff] [blame] | 423 | return NULL; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 424 | } |
| 425 | |
| 426 | /* |
| 427 | * given a pin number that is local to a pin controller, find out the pin bank |
| 428 | * and the register base of the pin bank. |
| 429 | */ |
| 430 | static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, |
| 431 | unsigned pin) |
| 432 | { |
| 433 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; |
| 434 | |
Axel Lin | 51578b9 | 2013-08-23 15:49:00 +0800 | [diff] [blame] | 435 | while (pin >= (b->pin_base + b->nr_pins)) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 436 | b++; |
| 437 | |
| 438 | return b; |
| 439 | } |
| 440 | |
| 441 | static struct rockchip_pin_bank *bank_num_to_bank( |
| 442 | struct rockchip_pinctrl *info, |
| 443 | unsigned num) |
| 444 | { |
| 445 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; |
| 446 | int i; |
| 447 | |
Axel Lin | 1cb9539 | 2013-08-21 10:28:50 +0800 | [diff] [blame] | 448 | for (i = 0; i < info->ctrl->nr_banks; i++, b++) { |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 449 | if (b->bank_num == num) |
Axel Lin | 1cb9539 | 2013-08-21 10:28:50 +0800 | [diff] [blame] | 450 | return b; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 451 | } |
| 452 | |
Axel Lin | 1cb9539 | 2013-08-21 10:28:50 +0800 | [diff] [blame] | 453 | return ERR_PTR(-EINVAL); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 454 | } |
| 455 | |
| 456 | /* |
| 457 | * Pinctrl_ops handling |
| 458 | */ |
| 459 | |
| 460 | static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) |
| 461 | { |
| 462 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 463 | |
| 464 | return info->ngroups; |
| 465 | } |
| 466 | |
| 467 | static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, |
| 468 | unsigned selector) |
| 469 | { |
| 470 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 471 | |
| 472 | return info->groups[selector].name; |
| 473 | } |
| 474 | |
| 475 | static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, |
| 476 | unsigned selector, const unsigned **pins, |
| 477 | unsigned *npins) |
| 478 | { |
| 479 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 480 | |
| 481 | if (selector >= info->ngroups) |
| 482 | return -EINVAL; |
| 483 | |
| 484 | *pins = info->groups[selector].pins; |
| 485 | *npins = info->groups[selector].npins; |
| 486 | |
| 487 | return 0; |
| 488 | } |
| 489 | |
| 490 | static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, |
| 491 | struct device_node *np, |
| 492 | struct pinctrl_map **map, unsigned *num_maps) |
| 493 | { |
| 494 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 495 | const struct rockchip_pin_group *grp; |
| 496 | struct pinctrl_map *new_map; |
| 497 | struct device_node *parent; |
| 498 | int map_num = 1; |
| 499 | int i; |
| 500 | |
| 501 | /* |
| 502 | * first find the group of this node and check if we need to create |
| 503 | * config maps for pins |
| 504 | */ |
| 505 | grp = pinctrl_name_to_group(info, np->name); |
| 506 | if (!grp) { |
Rob Herring | 94f4e54 | 2018-08-27 20:52:41 -0500 | [diff] [blame] | 507 | dev_err(info->dev, "unable to find group for node %pOFn\n", |
| 508 | np); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 509 | return -EINVAL; |
| 510 | } |
| 511 | |
| 512 | map_num += grp->npins; |
Dafna Hirschfeld | d7faa8f | 2020-05-06 12:09:03 +0200 | [diff] [blame] | 513 | |
| 514 | new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 515 | if (!new_map) |
| 516 | return -ENOMEM; |
| 517 | |
| 518 | *map = new_map; |
| 519 | *num_maps = map_num; |
| 520 | |
| 521 | /* create mux map */ |
| 522 | parent = of_get_parent(np); |
| 523 | if (!parent) { |
Dafna Hirschfeld | d7faa8f | 2020-05-06 12:09:03 +0200 | [diff] [blame] | 524 | kfree(new_map); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 525 | return -EINVAL; |
| 526 | } |
| 527 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; |
| 528 | new_map[0].data.mux.function = parent->name; |
| 529 | new_map[0].data.mux.group = np->name; |
| 530 | of_node_put(parent); |
| 531 | |
| 532 | /* create config map */ |
| 533 | new_map++; |
| 534 | for (i = 0; i < grp->npins; i++) { |
| 535 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; |
| 536 | new_map[i].data.configs.group_or_pin = |
| 537 | pin_get_name(pctldev, grp->pins[i]); |
| 538 | new_map[i].data.configs.configs = grp->data[i].configs; |
| 539 | new_map[i].data.configs.num_configs = grp->data[i].nconfigs; |
| 540 | } |
| 541 | |
| 542 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", |
| 543 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); |
| 544 | |
| 545 | return 0; |
| 546 | } |
| 547 | |
| 548 | static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, |
| 549 | struct pinctrl_map *map, unsigned num_maps) |
| 550 | { |
Dafna Hirschfeld | d7faa8f | 2020-05-06 12:09:03 +0200 | [diff] [blame] | 551 | kfree(map); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | static const struct pinctrl_ops rockchip_pctrl_ops = { |
| 555 | .get_groups_count = rockchip_get_groups_count, |
| 556 | .get_group_name = rockchip_get_group_name, |
| 557 | .get_group_pins = rockchip_get_group_pins, |
| 558 | .dt_node_to_map = rockchip_dt_node_to_map, |
| 559 | .dt_free_map = rockchip_dt_free_map, |
| 560 | }; |
| 561 | |
| 562 | /* |
| 563 | * Hardware access |
| 564 | */ |
| 565 | |
David Wu | 12b8f01 | 2017-08-23 16:00:07 +0800 | [diff] [blame] | 566 | static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = { |
| 567 | { |
| 568 | .num = 1, |
| 569 | .pin = 0, |
| 570 | .reg = 0x418, |
| 571 | .bit = 0, |
| 572 | .mask = 0x3 |
| 573 | }, { |
| 574 | .num = 1, |
| 575 | .pin = 1, |
| 576 | .reg = 0x418, |
| 577 | .bit = 2, |
| 578 | .mask = 0x3 |
| 579 | }, { |
| 580 | .num = 1, |
| 581 | .pin = 2, |
| 582 | .reg = 0x418, |
| 583 | .bit = 4, |
| 584 | .mask = 0x3 |
| 585 | }, { |
| 586 | .num = 1, |
| 587 | .pin = 3, |
| 588 | .reg = 0x418, |
| 589 | .bit = 6, |
| 590 | .mask = 0x3 |
| 591 | }, { |
| 592 | .num = 1, |
| 593 | .pin = 4, |
| 594 | .reg = 0x418, |
| 595 | .bit = 8, |
| 596 | .mask = 0x3 |
| 597 | }, { |
| 598 | .num = 1, |
| 599 | .pin = 5, |
| 600 | .reg = 0x418, |
| 601 | .bit = 10, |
| 602 | .mask = 0x3 |
| 603 | }, { |
| 604 | .num = 1, |
| 605 | .pin = 6, |
| 606 | .reg = 0x418, |
| 607 | .bit = 12, |
| 608 | .mask = 0x3 |
| 609 | }, { |
| 610 | .num = 1, |
| 611 | .pin = 7, |
| 612 | .reg = 0x418, |
| 613 | .bit = 14, |
| 614 | .mask = 0x3 |
| 615 | }, { |
| 616 | .num = 1, |
| 617 | .pin = 8, |
| 618 | .reg = 0x41c, |
| 619 | .bit = 0, |
| 620 | .mask = 0x3 |
| 621 | }, { |
| 622 | .num = 1, |
| 623 | .pin = 9, |
| 624 | .reg = 0x41c, |
| 625 | .bit = 2, |
| 626 | .mask = 0x3 |
| 627 | }, |
| 628 | }; |
| 629 | |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 630 | static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = { |
| 631 | { |
| 632 | .num = 2, |
| 633 | .pin = 20, |
| 634 | .reg = 0xe8, |
| 635 | .bit = 0, |
| 636 | .mask = 0x7 |
| 637 | }, { |
| 638 | .num = 2, |
| 639 | .pin = 21, |
| 640 | .reg = 0xe8, |
| 641 | .bit = 4, |
| 642 | .mask = 0x7 |
| 643 | }, { |
| 644 | .num = 2, |
| 645 | .pin = 22, |
| 646 | .reg = 0xe8, |
| 647 | .bit = 8, |
| 648 | .mask = 0x7 |
| 649 | }, { |
| 650 | .num = 2, |
| 651 | .pin = 23, |
| 652 | .reg = 0xe8, |
| 653 | .bit = 12, |
| 654 | .mask = 0x7 |
| 655 | }, { |
| 656 | .num = 2, |
| 657 | .pin = 24, |
| 658 | .reg = 0xd4, |
| 659 | .bit = 12, |
| 660 | .mask = 0x7 |
| 661 | }, |
| 662 | }; |
| 663 | |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 664 | static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { |
| 665 | { |
| 666 | .num = 1, |
| 667 | .pin = 14, |
| 668 | .reg = 0x28, |
| 669 | .bit = 12, |
| 670 | .mask = 0xf |
| 671 | }, { |
| 672 | .num = 1, |
| 673 | .pin = 15, |
| 674 | .reg = 0x2c, |
| 675 | .bit = 0, |
| 676 | .mask = 0x3 |
| 677 | }, { |
| 678 | .num = 1, |
| 679 | .pin = 18, |
| 680 | .reg = 0x30, |
| 681 | .bit = 4, |
| 682 | .mask = 0xf |
| 683 | }, { |
| 684 | .num = 1, |
| 685 | .pin = 19, |
| 686 | .reg = 0x30, |
| 687 | .bit = 8, |
| 688 | .mask = 0xf |
| 689 | }, { |
| 690 | .num = 1, |
| 691 | .pin = 20, |
| 692 | .reg = 0x30, |
| 693 | .bit = 12, |
| 694 | .mask = 0xf |
| 695 | }, { |
| 696 | .num = 1, |
| 697 | .pin = 21, |
| 698 | .reg = 0x34, |
| 699 | .bit = 0, |
| 700 | .mask = 0xf |
| 701 | }, { |
| 702 | .num = 1, |
| 703 | .pin = 22, |
| 704 | .reg = 0x34, |
| 705 | .bit = 4, |
| 706 | .mask = 0xf |
| 707 | }, { |
| 708 | .num = 1, |
| 709 | .pin = 23, |
| 710 | .reg = 0x34, |
| 711 | .bit = 8, |
| 712 | .mask = 0xf |
| 713 | }, { |
| 714 | .num = 3, |
| 715 | .pin = 12, |
| 716 | .reg = 0x68, |
| 717 | .bit = 8, |
| 718 | .mask = 0xf |
| 719 | }, { |
| 720 | .num = 3, |
| 721 | .pin = 13, |
| 722 | .reg = 0x68, |
| 723 | .bit = 12, |
| 724 | .mask = 0xf |
| 725 | }, { |
| 726 | .num = 2, |
| 727 | .pin = 2, |
| 728 | .reg = 0x608, |
| 729 | .bit = 0, |
| 730 | .mask = 0x7 |
| 731 | }, { |
| 732 | .num = 2, |
| 733 | .pin = 3, |
| 734 | .reg = 0x608, |
| 735 | .bit = 4, |
| 736 | .mask = 0x7 |
| 737 | }, { |
| 738 | .num = 2, |
| 739 | .pin = 16, |
| 740 | .reg = 0x610, |
| 741 | .bit = 8, |
| 742 | .mask = 0x7 |
| 743 | }, { |
| 744 | .num = 3, |
| 745 | .pin = 10, |
| 746 | .reg = 0x610, |
| 747 | .bit = 0, |
| 748 | .mask = 0x7 |
| 749 | }, { |
| 750 | .num = 3, |
| 751 | .pin = 11, |
| 752 | .reg = 0x610, |
| 753 | .bit = 4, |
| 754 | .mask = 0x7 |
| 755 | }, |
| 756 | }; |
| 757 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 758 | static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 759 | { |
| 760 | .num = 2, |
| 761 | .pin = 12, |
| 762 | .reg = 0x24, |
| 763 | .bit = 8, |
| 764 | .mask = 0x3 |
| 765 | }, { |
| 766 | .num = 2, |
| 767 | .pin = 15, |
| 768 | .reg = 0x28, |
| 769 | .bit = 0, |
| 770 | .mask = 0x7 |
| 771 | }, { |
| 772 | .num = 2, |
| 773 | .pin = 23, |
| 774 | .reg = 0x30, |
| 775 | .bit = 14, |
| 776 | .mask = 0x3 |
| 777 | }, |
| 778 | }; |
| 779 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 780 | static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, |
| 781 | int *reg, u8 *bit, int *mask) |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 782 | { |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 783 | struct rockchip_pinctrl *info = bank->drvdata; |
| 784 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
| 785 | struct rockchip_mux_recalced_data *data; |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 786 | int i; |
| 787 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 788 | for (i = 0; i < ctrl->niomux_recalced; i++) { |
| 789 | data = &ctrl->iomux_recalced[i]; |
| 790 | if (data->num == bank->bank_num && |
| 791 | data->pin == pin) |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 792 | break; |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 793 | } |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 794 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 795 | if (i >= ctrl->niomux_recalced) |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 796 | return; |
| 797 | |
| 798 | *reg = data->reg; |
| 799 | *mask = data->mask; |
| 800 | *bit = data->bit; |
| 801 | } |
| 802 | |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 803 | static struct rockchip_mux_route_data px30_mux_route_data[] = { |
| 804 | { |
| 805 | /* cif-d2m0 */ |
| 806 | .bank_num = 2, |
| 807 | .pin = 0, |
| 808 | .func = 1, |
| 809 | .route_offset = 0x184, |
| 810 | .route_val = BIT(16 + 7), |
| 811 | }, { |
| 812 | /* cif-d2m1 */ |
| 813 | .bank_num = 3, |
| 814 | .pin = 3, |
| 815 | .func = 3, |
| 816 | .route_offset = 0x184, |
| 817 | .route_val = BIT(16 + 7) | BIT(7), |
| 818 | }, { |
| 819 | /* pdm-m0 */ |
| 820 | .bank_num = 3, |
| 821 | .pin = 22, |
| 822 | .func = 2, |
| 823 | .route_offset = 0x184, |
| 824 | .route_val = BIT(16 + 8), |
| 825 | }, { |
| 826 | /* pdm-m1 */ |
| 827 | .bank_num = 2, |
| 828 | .pin = 22, |
| 829 | .func = 1, |
| 830 | .route_offset = 0x184, |
| 831 | .route_val = BIT(16 + 8) | BIT(8), |
| 832 | }, { |
| 833 | /* uart2-rxm0 */ |
| 834 | .bank_num = 1, |
| 835 | .pin = 27, |
| 836 | .func = 2, |
| 837 | .route_offset = 0x184, |
| 838 | .route_val = BIT(16 + 10), |
| 839 | }, { |
| 840 | /* uart2-rxm1 */ |
| 841 | .bank_num = 2, |
| 842 | .pin = 14, |
| 843 | .func = 2, |
| 844 | .route_offset = 0x184, |
| 845 | .route_val = BIT(16 + 10) | BIT(10), |
| 846 | }, { |
| 847 | /* uart3-rxm0 */ |
| 848 | .bank_num = 0, |
| 849 | .pin = 17, |
| 850 | .func = 2, |
| 851 | .route_offset = 0x184, |
| 852 | .route_val = BIT(16 + 9), |
| 853 | }, { |
| 854 | /* uart3-rxm1 */ |
| 855 | .bank_num = 1, |
| 856 | .pin = 15, |
| 857 | .func = 2, |
| 858 | .route_offset = 0x184, |
| 859 | .route_val = BIT(16 + 9) | BIT(9), |
| 860 | }, |
| 861 | }; |
| 862 | |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 863 | static struct rockchip_mux_route_data rk3128_mux_route_data[] = { |
| 864 | { |
| 865 | /* spi-0 */ |
| 866 | .bank_num = 1, |
| 867 | .pin = 10, |
| 868 | .func = 1, |
| 869 | .route_offset = 0x144, |
| 870 | .route_val = BIT(16 + 3) | BIT(16 + 4), |
| 871 | }, { |
| 872 | /* spi-1 */ |
| 873 | .bank_num = 1, |
| 874 | .pin = 27, |
| 875 | .func = 3, |
| 876 | .route_offset = 0x144, |
| 877 | .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3), |
| 878 | }, { |
| 879 | /* spi-2 */ |
| 880 | .bank_num = 0, |
| 881 | .pin = 13, |
| 882 | .func = 2, |
| 883 | .route_offset = 0x144, |
| 884 | .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4), |
| 885 | }, { |
| 886 | /* i2s-0 */ |
| 887 | .bank_num = 1, |
| 888 | .pin = 5, |
| 889 | .func = 1, |
| 890 | .route_offset = 0x144, |
| 891 | .route_val = BIT(16 + 5), |
| 892 | }, { |
| 893 | /* i2s-1 */ |
| 894 | .bank_num = 0, |
| 895 | .pin = 14, |
| 896 | .func = 1, |
| 897 | .route_offset = 0x144, |
| 898 | .route_val = BIT(16 + 5) | BIT(5), |
| 899 | }, { |
| 900 | /* emmc-0 */ |
| 901 | .bank_num = 1, |
| 902 | .pin = 22, |
| 903 | .func = 2, |
| 904 | .route_offset = 0x144, |
| 905 | .route_val = BIT(16 + 6), |
| 906 | }, { |
| 907 | /* emmc-1 */ |
| 908 | .bank_num = 2, |
| 909 | .pin = 4, |
| 910 | .func = 2, |
| 911 | .route_offset = 0x144, |
| 912 | .route_val = BIT(16 + 6) | BIT(6), |
| 913 | }, |
| 914 | }; |
| 915 | |
Heiko Stuebner | ada62b7 | 2018-11-11 22:00:47 +0100 | [diff] [blame] | 916 | static struct rockchip_mux_route_data rk3188_mux_route_data[] = { |
| 917 | { |
| 918 | /* non-iomuxed emmc/flash pins on flash-dqs */ |
| 919 | .bank_num = 0, |
| 920 | .pin = 24, |
| 921 | .func = 1, |
| 922 | .route_location = ROCKCHIP_ROUTE_GRF, |
| 923 | .route_offset = 0xa0, |
| 924 | .route_val = BIT(16 + 11), |
| 925 | }, { |
| 926 | /* non-iomuxed emmc/flash pins on emmc-clk */ |
| 927 | .bank_num = 0, |
| 928 | .pin = 24, |
| 929 | .func = 2, |
| 930 | .route_location = ROCKCHIP_ROUTE_GRF, |
| 931 | .route_offset = 0xa0, |
| 932 | .route_val = BIT(16 + 11) | BIT(11), |
| 933 | }, |
| 934 | }; |
| 935 | |
David Wu | d4970ee | 2017-05-26 15:20:21 +0800 | [diff] [blame] | 936 | static struct rockchip_mux_route_data rk3228_mux_route_data[] = { |
| 937 | { |
| 938 | /* pwm0-0 */ |
| 939 | .bank_num = 0, |
| 940 | .pin = 26, |
| 941 | .func = 1, |
| 942 | .route_offset = 0x50, |
| 943 | .route_val = BIT(16), |
| 944 | }, { |
| 945 | /* pwm0-1 */ |
| 946 | .bank_num = 3, |
| 947 | .pin = 21, |
| 948 | .func = 1, |
| 949 | .route_offset = 0x50, |
| 950 | .route_val = BIT(16) | BIT(0), |
| 951 | }, { |
| 952 | /* pwm1-0 */ |
| 953 | .bank_num = 0, |
| 954 | .pin = 27, |
| 955 | .func = 1, |
| 956 | .route_offset = 0x50, |
| 957 | .route_val = BIT(16 + 1), |
| 958 | }, { |
| 959 | /* pwm1-1 */ |
| 960 | .bank_num = 0, |
| 961 | .pin = 30, |
| 962 | .func = 2, |
| 963 | .route_offset = 0x50, |
| 964 | .route_val = BIT(16 + 1) | BIT(1), |
| 965 | }, { |
| 966 | /* pwm2-0 */ |
| 967 | .bank_num = 0, |
| 968 | .pin = 28, |
| 969 | .func = 1, |
| 970 | .route_offset = 0x50, |
| 971 | .route_val = BIT(16 + 2), |
| 972 | }, { |
| 973 | /* pwm2-1 */ |
| 974 | .bank_num = 1, |
| 975 | .pin = 12, |
| 976 | .func = 2, |
| 977 | .route_offset = 0x50, |
| 978 | .route_val = BIT(16 + 2) | BIT(2), |
| 979 | }, { |
| 980 | /* pwm3-0 */ |
| 981 | .bank_num = 3, |
| 982 | .pin = 26, |
| 983 | .func = 1, |
| 984 | .route_offset = 0x50, |
| 985 | .route_val = BIT(16 + 3), |
| 986 | }, { |
| 987 | /* pwm3-1 */ |
| 988 | .bank_num = 1, |
| 989 | .pin = 11, |
| 990 | .func = 2, |
| 991 | .route_offset = 0x50, |
| 992 | .route_val = BIT(16 + 3) | BIT(3), |
| 993 | }, { |
| 994 | /* sdio-0_d0 */ |
| 995 | .bank_num = 1, |
| 996 | .pin = 1, |
| 997 | .func = 1, |
| 998 | .route_offset = 0x50, |
| 999 | .route_val = BIT(16 + 4), |
| 1000 | }, { |
| 1001 | /* sdio-1_d0 */ |
| 1002 | .bank_num = 3, |
| 1003 | .pin = 2, |
| 1004 | .func = 1, |
| 1005 | .route_offset = 0x50, |
| 1006 | .route_val = BIT(16 + 4) | BIT(4), |
| 1007 | }, { |
| 1008 | /* spi-0_rx */ |
| 1009 | .bank_num = 0, |
| 1010 | .pin = 13, |
| 1011 | .func = 2, |
| 1012 | .route_offset = 0x50, |
| 1013 | .route_val = BIT(16 + 5), |
| 1014 | }, { |
| 1015 | /* spi-1_rx */ |
| 1016 | .bank_num = 2, |
| 1017 | .pin = 0, |
| 1018 | .func = 2, |
| 1019 | .route_offset = 0x50, |
| 1020 | .route_val = BIT(16 + 5) | BIT(5), |
| 1021 | }, { |
| 1022 | /* emmc-0_cmd */ |
| 1023 | .bank_num = 1, |
| 1024 | .pin = 22, |
| 1025 | .func = 2, |
| 1026 | .route_offset = 0x50, |
| 1027 | .route_val = BIT(16 + 7), |
| 1028 | }, { |
| 1029 | /* emmc-1_cmd */ |
| 1030 | .bank_num = 2, |
| 1031 | .pin = 4, |
| 1032 | .func = 2, |
| 1033 | .route_offset = 0x50, |
| 1034 | .route_val = BIT(16 + 7) | BIT(7), |
| 1035 | }, { |
| 1036 | /* uart2-0_rx */ |
| 1037 | .bank_num = 1, |
| 1038 | .pin = 19, |
| 1039 | .func = 2, |
| 1040 | .route_offset = 0x50, |
| 1041 | .route_val = BIT(16 + 8), |
| 1042 | }, { |
| 1043 | /* uart2-1_rx */ |
| 1044 | .bank_num = 1, |
| 1045 | .pin = 10, |
| 1046 | .func = 2, |
| 1047 | .route_offset = 0x50, |
| 1048 | .route_val = BIT(16 + 8) | BIT(8), |
| 1049 | }, { |
| 1050 | /* uart1-0_rx */ |
| 1051 | .bank_num = 1, |
| 1052 | .pin = 10, |
| 1053 | .func = 1, |
| 1054 | .route_offset = 0x50, |
| 1055 | .route_val = BIT(16 + 11), |
| 1056 | }, { |
| 1057 | /* uart1-1_rx */ |
| 1058 | .bank_num = 3, |
| 1059 | .pin = 13, |
| 1060 | .func = 1, |
| 1061 | .route_offset = 0x50, |
| 1062 | .route_val = BIT(16 + 11) | BIT(11), |
| 1063 | }, |
| 1064 | }; |
| 1065 | |
Heiko Stuebner | 4e96fd3 | 2017-10-21 10:53:10 +0200 | [diff] [blame] | 1066 | static struct rockchip_mux_route_data rk3288_mux_route_data[] = { |
| 1067 | { |
| 1068 | /* edphdmi_cecinoutt1 */ |
| 1069 | .bank_num = 7, |
| 1070 | .pin = 16, |
| 1071 | .func = 2, |
| 1072 | .route_offset = 0x264, |
| 1073 | .route_val = BIT(16 + 12) | BIT(12), |
| 1074 | }, { |
| 1075 | /* edphdmi_cecinout */ |
| 1076 | .bank_num = 7, |
| 1077 | .pin = 23, |
| 1078 | .func = 4, |
| 1079 | .route_offset = 0x264, |
| 1080 | .route_val = BIT(16 + 12), |
| 1081 | }, |
| 1082 | }; |
| 1083 | |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 1084 | static struct rockchip_mux_route_data rk3308_mux_route_data[] = { |
| 1085 | { |
| 1086 | /* rtc_clk */ |
| 1087 | .bank_num = 0, |
| 1088 | .pin = 19, |
| 1089 | .func = 1, |
| 1090 | .route_offset = 0x314, |
| 1091 | .route_val = BIT(16 + 0) | BIT(0), |
| 1092 | }, { |
| 1093 | /* uart2_rxm0 */ |
| 1094 | .bank_num = 1, |
| 1095 | .pin = 22, |
| 1096 | .func = 2, |
| 1097 | .route_offset = 0x314, |
| 1098 | .route_val = BIT(16 + 2) | BIT(16 + 3), |
| 1099 | }, { |
| 1100 | /* uart2_rxm1 */ |
| 1101 | .bank_num = 4, |
| 1102 | .pin = 26, |
| 1103 | .func = 2, |
| 1104 | .route_offset = 0x314, |
| 1105 | .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2), |
| 1106 | }, { |
| 1107 | /* i2c3_sdam0 */ |
| 1108 | .bank_num = 0, |
| 1109 | .pin = 15, |
| 1110 | .func = 2, |
| 1111 | .route_offset = 0x608, |
| 1112 | .route_val = BIT(16 + 8) | BIT(16 + 9), |
| 1113 | }, { |
| 1114 | /* i2c3_sdam1 */ |
| 1115 | .bank_num = 3, |
| 1116 | .pin = 12, |
| 1117 | .func = 2, |
| 1118 | .route_offset = 0x608, |
| 1119 | .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8), |
| 1120 | }, { |
| 1121 | /* i2c3_sdam2 */ |
| 1122 | .bank_num = 2, |
| 1123 | .pin = 0, |
| 1124 | .func = 3, |
| 1125 | .route_offset = 0x608, |
| 1126 | .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9), |
| 1127 | }, { |
| 1128 | /* i2s-8ch-1-sclktxm0 */ |
| 1129 | .bank_num = 1, |
| 1130 | .pin = 3, |
| 1131 | .func = 2, |
| 1132 | .route_offset = 0x308, |
| 1133 | .route_val = BIT(16 + 3), |
| 1134 | }, { |
| 1135 | /* i2s-8ch-1-sclkrxm0 */ |
| 1136 | .bank_num = 1, |
| 1137 | .pin = 4, |
| 1138 | .func = 2, |
| 1139 | .route_offset = 0x308, |
| 1140 | .route_val = BIT(16 + 3), |
| 1141 | }, { |
| 1142 | /* i2s-8ch-1-sclktxm1 */ |
| 1143 | .bank_num = 1, |
| 1144 | .pin = 13, |
| 1145 | .func = 2, |
| 1146 | .route_offset = 0x308, |
| 1147 | .route_val = BIT(16 + 3) | BIT(3), |
| 1148 | }, { |
| 1149 | /* i2s-8ch-1-sclkrxm1 */ |
| 1150 | .bank_num = 1, |
| 1151 | .pin = 14, |
| 1152 | .func = 2, |
| 1153 | .route_offset = 0x308, |
| 1154 | .route_val = BIT(16 + 3) | BIT(3), |
| 1155 | }, { |
| 1156 | /* pdm-clkm0 */ |
| 1157 | .bank_num = 1, |
| 1158 | .pin = 4, |
| 1159 | .func = 3, |
| 1160 | .route_offset = 0x308, |
| 1161 | .route_val = BIT(16 + 12) | BIT(16 + 13), |
| 1162 | }, { |
| 1163 | /* pdm-clkm1 */ |
| 1164 | .bank_num = 1, |
| 1165 | .pin = 14, |
| 1166 | .func = 4, |
| 1167 | .route_offset = 0x308, |
| 1168 | .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), |
| 1169 | }, { |
| 1170 | /* pdm-clkm2 */ |
| 1171 | .bank_num = 2, |
| 1172 | .pin = 6, |
| 1173 | .func = 2, |
| 1174 | .route_offset = 0x308, |
| 1175 | .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), |
| 1176 | }, { |
| 1177 | /* pdm-clkm-m2 */ |
| 1178 | .bank_num = 2, |
| 1179 | .pin = 4, |
| 1180 | .func = 3, |
| 1181 | .route_offset = 0x600, |
| 1182 | .route_val = BIT(16 + 2) | BIT(2), |
| 1183 | }, { |
| 1184 | /* spi1_miso */ |
| 1185 | .bank_num = 3, |
| 1186 | .pin = 10, |
| 1187 | .func = 3, |
| 1188 | .route_offset = 0x314, |
| 1189 | .route_val = BIT(16 + 9), |
| 1190 | }, { |
| 1191 | /* spi1_miso_m1 */ |
| 1192 | .bank_num = 2, |
| 1193 | .pin = 4, |
| 1194 | .func = 2, |
| 1195 | .route_offset = 0x314, |
| 1196 | .route_val = BIT(16 + 9) | BIT(9), |
| 1197 | }, { |
| 1198 | /* owire_m0 */ |
| 1199 | .bank_num = 0, |
| 1200 | .pin = 11, |
| 1201 | .func = 3, |
| 1202 | .route_offset = 0x314, |
| 1203 | .route_val = BIT(16 + 10) | BIT(16 + 11), |
| 1204 | }, { |
| 1205 | /* owire_m1 */ |
| 1206 | .bank_num = 1, |
| 1207 | .pin = 22, |
| 1208 | .func = 7, |
| 1209 | .route_offset = 0x314, |
| 1210 | .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), |
| 1211 | }, { |
| 1212 | /* owire_m2 */ |
| 1213 | .bank_num = 2, |
| 1214 | .pin = 2, |
| 1215 | .func = 5, |
| 1216 | .route_offset = 0x314, |
| 1217 | .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), |
| 1218 | }, { |
| 1219 | /* can_rxd_m0 */ |
| 1220 | .bank_num = 0, |
| 1221 | .pin = 11, |
| 1222 | .func = 2, |
| 1223 | .route_offset = 0x314, |
| 1224 | .route_val = BIT(16 + 12) | BIT(16 + 13), |
| 1225 | }, { |
| 1226 | /* can_rxd_m1 */ |
| 1227 | .bank_num = 1, |
| 1228 | .pin = 22, |
| 1229 | .func = 5, |
| 1230 | .route_offset = 0x314, |
| 1231 | .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12), |
| 1232 | }, { |
| 1233 | /* can_rxd_m2 */ |
| 1234 | .bank_num = 2, |
| 1235 | .pin = 2, |
| 1236 | .func = 4, |
| 1237 | .route_offset = 0x314, |
| 1238 | .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13), |
| 1239 | }, { |
| 1240 | /* mac_rxd0_m0 */ |
| 1241 | .bank_num = 1, |
| 1242 | .pin = 20, |
| 1243 | .func = 3, |
| 1244 | .route_offset = 0x314, |
| 1245 | .route_val = BIT(16 + 14), |
| 1246 | }, { |
| 1247 | /* mac_rxd0_m1 */ |
| 1248 | .bank_num = 4, |
| 1249 | .pin = 2, |
| 1250 | .func = 2, |
| 1251 | .route_offset = 0x314, |
| 1252 | .route_val = BIT(16 + 14) | BIT(14), |
| 1253 | }, { |
| 1254 | /* uart3_rx */ |
| 1255 | .bank_num = 3, |
| 1256 | .pin = 12, |
| 1257 | .func = 4, |
| 1258 | .route_offset = 0x314, |
| 1259 | .route_val = BIT(16 + 15), |
| 1260 | }, { |
| 1261 | /* uart3_rx_m1 */ |
| 1262 | .bank_num = 0, |
| 1263 | .pin = 17, |
| 1264 | .func = 3, |
| 1265 | .route_offset = 0x314, |
| 1266 | .route_val = BIT(16 + 15) | BIT(15), |
| 1267 | }, |
| 1268 | }; |
| 1269 | |
David Wu | cedc964 | 2017-05-26 15:20:22 +0800 | [diff] [blame] | 1270 | static struct rockchip_mux_route_data rk3328_mux_route_data[] = { |
| 1271 | { |
| 1272 | /* uart2dbg_rxm0 */ |
| 1273 | .bank_num = 1, |
| 1274 | .pin = 1, |
| 1275 | .func = 2, |
| 1276 | .route_offset = 0x50, |
| 1277 | .route_val = BIT(16) | BIT(16 + 1), |
| 1278 | }, { |
| 1279 | /* uart2dbg_rxm1 */ |
| 1280 | .bank_num = 2, |
| 1281 | .pin = 1, |
| 1282 | .func = 1, |
| 1283 | .route_offset = 0x50, |
| 1284 | .route_val = BIT(16) | BIT(16 + 1) | BIT(0), |
| 1285 | }, { |
David Wu | a976d7b | 2017-09-30 20:13:21 +0800 | [diff] [blame] | 1286 | /* gmac-m1_rxd0 */ |
David Wu | cedc964 | 2017-05-26 15:20:22 +0800 | [diff] [blame] | 1287 | .bank_num = 1, |
| 1288 | .pin = 11, |
| 1289 | .func = 2, |
| 1290 | .route_offset = 0x50, |
David Wu | a976d7b | 2017-09-30 20:13:21 +0800 | [diff] [blame] | 1291 | .route_val = BIT(16 + 2) | BIT(2), |
| 1292 | }, { |
| 1293 | /* gmac-m1-optimized_rxd3 */ |
| 1294 | .bank_num = 1, |
| 1295 | .pin = 14, |
| 1296 | .func = 2, |
| 1297 | .route_offset = 0x50, |
| 1298 | .route_val = BIT(16 + 10) | BIT(10), |
David Wu | cedc964 | 2017-05-26 15:20:22 +0800 | [diff] [blame] | 1299 | }, { |
| 1300 | /* pdm_sdi0m0 */ |
| 1301 | .bank_num = 2, |
| 1302 | .pin = 19, |
| 1303 | .func = 2, |
| 1304 | .route_offset = 0x50, |
| 1305 | .route_val = BIT(16 + 3), |
| 1306 | }, { |
| 1307 | /* pdm_sdi0m1 */ |
| 1308 | .bank_num = 1, |
| 1309 | .pin = 23, |
| 1310 | .func = 3, |
| 1311 | .route_offset = 0x50, |
| 1312 | .route_val = BIT(16 + 3) | BIT(3), |
| 1313 | }, { |
| 1314 | /* spi_rxdm2 */ |
| 1315 | .bank_num = 3, |
| 1316 | .pin = 2, |
| 1317 | .func = 4, |
| 1318 | .route_offset = 0x50, |
| 1319 | .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), |
| 1320 | }, { |
| 1321 | /* i2s2_sdim0 */ |
| 1322 | .bank_num = 1, |
| 1323 | .pin = 24, |
| 1324 | .func = 1, |
| 1325 | .route_offset = 0x50, |
| 1326 | .route_val = BIT(16 + 6), |
| 1327 | }, { |
| 1328 | /* i2s2_sdim1 */ |
| 1329 | .bank_num = 3, |
| 1330 | .pin = 2, |
| 1331 | .func = 6, |
| 1332 | .route_offset = 0x50, |
| 1333 | .route_val = BIT(16 + 6) | BIT(6), |
| 1334 | }, { |
| 1335 | /* card_iom1 */ |
| 1336 | .bank_num = 2, |
| 1337 | .pin = 22, |
| 1338 | .func = 3, |
| 1339 | .route_offset = 0x50, |
| 1340 | .route_val = BIT(16 + 7) | BIT(7), |
| 1341 | }, { |
| 1342 | /* tsp_d5m1 */ |
| 1343 | .bank_num = 2, |
| 1344 | .pin = 16, |
| 1345 | .func = 3, |
| 1346 | .route_offset = 0x50, |
| 1347 | .route_val = BIT(16 + 8) | BIT(8), |
| 1348 | }, { |
| 1349 | /* cif_data5m1 */ |
| 1350 | .bank_num = 2, |
| 1351 | .pin = 16, |
| 1352 | .func = 4, |
| 1353 | .route_offset = 0x50, |
| 1354 | .route_val = BIT(16 + 9) | BIT(9), |
| 1355 | }, |
| 1356 | }; |
| 1357 | |
David Wu | accc1ce | 2017-05-26 15:20:23 +0800 | [diff] [blame] | 1358 | static struct rockchip_mux_route_data rk3399_mux_route_data[] = { |
| 1359 | { |
| 1360 | /* uart2dbga_rx */ |
| 1361 | .bank_num = 4, |
| 1362 | .pin = 8, |
| 1363 | .func = 2, |
| 1364 | .route_offset = 0xe21c, |
| 1365 | .route_val = BIT(16 + 10) | BIT(16 + 11), |
| 1366 | }, { |
| 1367 | /* uart2dbgb_rx */ |
| 1368 | .bank_num = 4, |
| 1369 | .pin = 16, |
| 1370 | .func = 2, |
| 1371 | .route_offset = 0xe21c, |
| 1372 | .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), |
| 1373 | }, { |
| 1374 | /* uart2dbgc_rx */ |
| 1375 | .bank_num = 4, |
| 1376 | .pin = 19, |
| 1377 | .func = 1, |
| 1378 | .route_offset = 0xe21c, |
| 1379 | .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), |
| 1380 | }, { |
| 1381 | /* pcie_clkreqn */ |
| 1382 | .bank_num = 2, |
| 1383 | .pin = 26, |
| 1384 | .func = 2, |
| 1385 | .route_offset = 0xe21c, |
| 1386 | .route_val = BIT(16 + 14), |
| 1387 | }, { |
| 1388 | /* pcie_clkreqnb */ |
| 1389 | .bank_num = 4, |
| 1390 | .pin = 24, |
| 1391 | .func = 1, |
| 1392 | .route_offset = 0xe21c, |
| 1393 | .route_val = BIT(16 + 14) | BIT(14), |
| 1394 | }, |
| 1395 | }; |
| 1396 | |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 1397 | static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, |
Heiko Stuebner | 51ff47a | 2018-11-11 22:00:46 +0100 | [diff] [blame] | 1398 | int mux, u32 *loc, u32 *reg, u32 *value) |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 1399 | { |
| 1400 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1401 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
| 1402 | struct rockchip_mux_route_data *data; |
| 1403 | int i; |
| 1404 | |
| 1405 | for (i = 0; i < ctrl->niomux_routes; i++) { |
| 1406 | data = &ctrl->iomux_routes[i]; |
| 1407 | if ((data->bank_num == bank->bank_num) && |
| 1408 | (data->pin == pin) && (data->func == mux)) |
| 1409 | break; |
| 1410 | } |
| 1411 | |
| 1412 | if (i >= ctrl->niomux_routes) |
| 1413 | return false; |
| 1414 | |
Heiko Stuebner | 51ff47a | 2018-11-11 22:00:46 +0100 | [diff] [blame] | 1415 | *loc = data->route_location; |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 1416 | *reg = data->route_offset; |
| 1417 | *value = data->route_val; |
| 1418 | |
| 1419 | return true; |
| 1420 | } |
| 1421 | |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 1422 | static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) |
| 1423 | { |
| 1424 | struct rockchip_pinctrl *info = bank->drvdata; |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 1425 | int iomux_num = (pin / 8); |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 1426 | struct regmap *regmap; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1427 | unsigned int val; |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1428 | int reg, ret, mask, mux_type; |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 1429 | u8 bit; |
| 1430 | |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 1431 | if (iomux_num > 3) |
| 1432 | return -EINVAL; |
| 1433 | |
Heiko Stübner | 62f4922 | 2014-06-16 01:37:49 +0200 | [diff] [blame] | 1434 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
| 1435 | dev_err(info->dev, "pin %d is unrouted\n", pin); |
| 1436 | return -EINVAL; |
| 1437 | } |
| 1438 | |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 1439 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 1440 | return RK_FUNC_GPIO; |
| 1441 | |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 1442 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
| 1443 | ? info->regmap_pmu : info->regmap_base; |
| 1444 | |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 1445 | /* get basic quadrupel of mux registers and the correct reg inside */ |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1446 | mux_type = bank->iomux[iomux_num].type; |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 1447 | reg = bank->iomux[iomux_num].offset; |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1448 | if (mux_type & IOMUX_WIDTH_4BIT) { |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1449 | if ((pin % 8) >= 4) |
| 1450 | reg += 0x4; |
| 1451 | bit = (pin % 4) * 4; |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 1452 | mask = 0xf; |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1453 | } else if (mux_type & IOMUX_WIDTH_3BIT) { |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 1454 | if ((pin % 8) >= 5) |
| 1455 | reg += 0x4; |
| 1456 | bit = (pin % 8 % 5) * 3; |
| 1457 | mask = 0x7; |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1458 | } else { |
| 1459 | bit = (pin % 8) * 2; |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 1460 | mask = 0x3; |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1461 | } |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 1462 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 1463 | if (bank->recalced_mask & BIT(pin)) |
| 1464 | rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1465 | |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 1466 | ret = regmap_read(regmap, reg, &val); |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1467 | if (ret) |
| 1468 | return ret; |
| 1469 | |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1470 | return ((val >> bit) & mask); |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 1471 | } |
| 1472 | |
John Keeping | 05709c3 | 2017-03-23 10:59:30 +0000 | [diff] [blame] | 1473 | static int rockchip_verify_mux(struct rockchip_pin_bank *bank, |
| 1474 | int pin, int mux) |
| 1475 | { |
| 1476 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1477 | int iomux_num = (pin / 8); |
| 1478 | |
| 1479 | if (iomux_num > 3) |
| 1480 | return -EINVAL; |
| 1481 | |
| 1482 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
| 1483 | dev_err(info->dev, "pin %d is unrouted\n", pin); |
| 1484 | return -EINVAL; |
| 1485 | } |
| 1486 | |
| 1487 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { |
| 1488 | if (mux != RK_FUNC_GPIO) { |
| 1489 | dev_err(info->dev, |
| 1490 | "pin %d only supports a gpio mux\n", pin); |
| 1491 | return -ENOTSUPP; |
| 1492 | } |
| 1493 | } |
| 1494 | |
| 1495 | return 0; |
| 1496 | } |
| 1497 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1498 | /* |
| 1499 | * Set a new mux function for a pin. |
| 1500 | * |
| 1501 | * The register is divided into the upper and lower 16 bit. When changing |
| 1502 | * a value, the previous register value is not read and changed. Instead |
| 1503 | * it seems the changed bits are marked in the upper 16 bit, while the |
| 1504 | * changed value gets set in the same offset in the lower 16 bit. |
| 1505 | * All pin settings seem to be 2 bit wide in both the upper and lower |
| 1506 | * parts. |
| 1507 | * @bank: pin bank to change |
| 1508 | * @pin: pin to change |
| 1509 | * @mux: new mux function to set |
| 1510 | */ |
Heiko Stübner | 1479718 | 2014-03-26 00:57:00 +0100 | [diff] [blame] | 1511 | static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1512 | { |
| 1513 | struct rockchip_pinctrl *info = bank->drvdata; |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 1514 | int iomux_num = (pin / 8); |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 1515 | struct regmap *regmap; |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1516 | int reg, ret, mask, mux_type; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1517 | u8 bit; |
Heiko Stuebner | 51ff47a | 2018-11-11 22:00:46 +0100 | [diff] [blame] | 1518 | u32 data, rmask, route_location, route_reg, route_val; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1519 | |
John Keeping | 05709c3 | 2017-03-23 10:59:30 +0000 | [diff] [blame] | 1520 | ret = rockchip_verify_mux(bank, pin, mux); |
| 1521 | if (ret < 0) |
| 1522 | return ret; |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 1523 | |
John Keeping | 05709c3 | 2017-03-23 10:59:30 +0000 | [diff] [blame] | 1524 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) |
| 1525 | return 0; |
Heiko Stübner | c4a532de | 2014-03-26 00:57:52 +0100 | [diff] [blame] | 1526 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1527 | dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", |
| 1528 | bank->bank_num, pin, mux); |
| 1529 | |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 1530 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
| 1531 | ? info->regmap_pmu : info->regmap_base; |
| 1532 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1533 | /* get basic quadrupel of mux registers and the correct reg inside */ |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1534 | mux_type = bank->iomux[iomux_num].type; |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 1535 | reg = bank->iomux[iomux_num].offset; |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1536 | if (mux_type & IOMUX_WIDTH_4BIT) { |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1537 | if ((pin % 8) >= 4) |
| 1538 | reg += 0x4; |
| 1539 | bit = (pin % 4) * 4; |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 1540 | mask = 0xf; |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1541 | } else if (mux_type & IOMUX_WIDTH_3BIT) { |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 1542 | if ((pin % 8) >= 5) |
| 1543 | reg += 0x4; |
| 1544 | bit = (pin % 8 % 5) * 3; |
| 1545 | mask = 0x7; |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1546 | } else { |
| 1547 | bit = (pin % 8) * 2; |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 1548 | mask = 0x3; |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1549 | } |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1550 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 1551 | if (bank->recalced_mask & BIT(pin)) |
| 1552 | rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); |
david.wu | ea262ad | 2017-02-10 18:23:48 +0800 | [diff] [blame] | 1553 | |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 1554 | if (bank->route_mask & BIT(pin)) { |
Heiko Stuebner | 51ff47a | 2018-11-11 22:00:46 +0100 | [diff] [blame] | 1555 | if (rockchip_get_mux_route(bank, pin, mux, &route_location, |
| 1556 | &route_reg, &route_val)) { |
| 1557 | struct regmap *route_regmap = regmap; |
| 1558 | |
| 1559 | /* handle special locations */ |
| 1560 | switch (route_location) { |
| 1561 | case ROCKCHIP_ROUTE_PMU: |
| 1562 | route_regmap = info->regmap_pmu; |
| 1563 | break; |
| 1564 | case ROCKCHIP_ROUTE_GRF: |
| 1565 | route_regmap = info->regmap_base; |
| 1566 | break; |
| 1567 | } |
| 1568 | |
| 1569 | ret = regmap_write(route_regmap, route_reg, route_val); |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 1570 | if (ret) |
| 1571 | return ret; |
| 1572 | } |
| 1573 | } |
| 1574 | |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1575 | data = (mask << (bit + 16)); |
Sonny Rao | 99e872d | 2014-07-31 22:58:00 -0700 | [diff] [blame] | 1576 | rmask = data | (data >> 16); |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 1577 | data |= (mux & mask) << bit; |
Sonny Rao | 99e872d | 2014-07-31 22:58:00 -0700 | [diff] [blame] | 1578 | ret = regmap_update_bits(regmap, reg, rmask, data); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1579 | |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1580 | return ret; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 1581 | } |
| 1582 | |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 1583 | #define PX30_PULL_PMU_OFFSET 0x10 |
| 1584 | #define PX30_PULL_GRF_OFFSET 0x60 |
| 1585 | #define PX30_PULL_BITS_PER_PIN 2 |
| 1586 | #define PX30_PULL_PINS_PER_REG 8 |
| 1587 | #define PX30_PULL_BANK_STRIDE 16 |
| 1588 | |
| 1589 | static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1590 | int pin_num, struct regmap **regmap, |
| 1591 | int *reg, u8 *bit) |
| 1592 | { |
| 1593 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1594 | |
| 1595 | /* The first 32 pins of the first bank are located in PMU */ |
| 1596 | if (bank->bank_num == 0) { |
| 1597 | *regmap = info->regmap_pmu; |
| 1598 | *reg = PX30_PULL_PMU_OFFSET; |
| 1599 | } else { |
| 1600 | *regmap = info->regmap_base; |
| 1601 | *reg = PX30_PULL_GRF_OFFSET; |
| 1602 | |
| 1603 | /* correct the offset, as we're starting with the 2nd bank */ |
| 1604 | *reg -= 0x10; |
| 1605 | *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; |
| 1606 | } |
| 1607 | |
| 1608 | *reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4); |
| 1609 | *bit = (pin_num % PX30_PULL_PINS_PER_REG); |
| 1610 | *bit *= PX30_PULL_BITS_PER_PIN; |
| 1611 | } |
| 1612 | |
| 1613 | #define PX30_DRV_PMU_OFFSET 0x20 |
| 1614 | #define PX30_DRV_GRF_OFFSET 0xf0 |
| 1615 | #define PX30_DRV_BITS_PER_PIN 2 |
| 1616 | #define PX30_DRV_PINS_PER_REG 8 |
| 1617 | #define PX30_DRV_BANK_STRIDE 16 |
| 1618 | |
| 1619 | static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1620 | int pin_num, struct regmap **regmap, |
| 1621 | int *reg, u8 *bit) |
| 1622 | { |
| 1623 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1624 | |
| 1625 | /* The first 32 pins of the first bank are located in PMU */ |
| 1626 | if (bank->bank_num == 0) { |
| 1627 | *regmap = info->regmap_pmu; |
| 1628 | *reg = PX30_DRV_PMU_OFFSET; |
| 1629 | } else { |
| 1630 | *regmap = info->regmap_base; |
| 1631 | *reg = PX30_DRV_GRF_OFFSET; |
| 1632 | |
| 1633 | /* correct the offset, as we're starting with the 2nd bank */ |
| 1634 | *reg -= 0x10; |
| 1635 | *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; |
| 1636 | } |
| 1637 | |
| 1638 | *reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4); |
| 1639 | *bit = (pin_num % PX30_DRV_PINS_PER_REG); |
| 1640 | *bit *= PX30_DRV_BITS_PER_PIN; |
| 1641 | } |
| 1642 | |
| 1643 | #define PX30_SCHMITT_PMU_OFFSET 0x38 |
| 1644 | #define PX30_SCHMITT_GRF_OFFSET 0xc0 |
| 1645 | #define PX30_SCHMITT_PINS_PER_PMU_REG 16 |
| 1646 | #define PX30_SCHMITT_BANK_STRIDE 16 |
| 1647 | #define PX30_SCHMITT_PINS_PER_GRF_REG 8 |
| 1648 | |
| 1649 | static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1650 | int pin_num, |
| 1651 | struct regmap **regmap, |
| 1652 | int *reg, u8 *bit) |
| 1653 | { |
| 1654 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1655 | int pins_per_reg; |
| 1656 | |
| 1657 | if (bank->bank_num == 0) { |
| 1658 | *regmap = info->regmap_pmu; |
| 1659 | *reg = PX30_SCHMITT_PMU_OFFSET; |
| 1660 | pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG; |
| 1661 | } else { |
| 1662 | *regmap = info->regmap_base; |
| 1663 | *reg = PX30_SCHMITT_GRF_OFFSET; |
| 1664 | pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG; |
| 1665 | *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; |
| 1666 | } |
| 1667 | |
| 1668 | *reg += ((pin_num / pins_per_reg) * 4); |
| 1669 | *bit = pin_num % pins_per_reg; |
| 1670 | |
| 1671 | return 0; |
| 1672 | } |
| 1673 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1674 | #define RV1108_PULL_PMU_OFFSET 0x10 |
| 1675 | #define RV1108_PULL_OFFSET 0x110 |
| 1676 | #define RV1108_PULL_PINS_PER_REG 8 |
| 1677 | #define RV1108_PULL_BITS_PER_PIN 2 |
| 1678 | #define RV1108_PULL_BANK_STRIDE 16 |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1679 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1680 | static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1681 | int pin_num, struct regmap **regmap, |
| 1682 | int *reg, u8 *bit) |
| 1683 | { |
| 1684 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1685 | |
| 1686 | /* The first 24 pins of the first bank are located in PMU */ |
| 1687 | if (bank->bank_num == 0) { |
| 1688 | *regmap = info->regmap_pmu; |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1689 | *reg = RV1108_PULL_PMU_OFFSET; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1690 | } else { |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1691 | *reg = RV1108_PULL_OFFSET; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1692 | *regmap = info->regmap_base; |
| 1693 | /* correct the offset, as we're starting with the 2nd bank */ |
| 1694 | *reg -= 0x10; |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1695 | *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1696 | } |
| 1697 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1698 | *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4); |
| 1699 | *bit = (pin_num % RV1108_PULL_PINS_PER_REG); |
| 1700 | *bit *= RV1108_PULL_BITS_PER_PIN; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1701 | } |
| 1702 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1703 | #define RV1108_DRV_PMU_OFFSET 0x20 |
| 1704 | #define RV1108_DRV_GRF_OFFSET 0x210 |
| 1705 | #define RV1108_DRV_BITS_PER_PIN 2 |
| 1706 | #define RV1108_DRV_PINS_PER_REG 8 |
| 1707 | #define RV1108_DRV_BANK_STRIDE 16 |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1708 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1709 | static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1710 | int pin_num, struct regmap **regmap, |
| 1711 | int *reg, u8 *bit) |
| 1712 | { |
| 1713 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1714 | |
| 1715 | /* The first 24 pins of the first bank are located in PMU */ |
| 1716 | if (bank->bank_num == 0) { |
| 1717 | *regmap = info->regmap_pmu; |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1718 | *reg = RV1108_DRV_PMU_OFFSET; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1719 | } else { |
| 1720 | *regmap = info->regmap_base; |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1721 | *reg = RV1108_DRV_GRF_OFFSET; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1722 | |
| 1723 | /* correct the offset, as we're starting with the 2nd bank */ |
| 1724 | *reg -= 0x10; |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1725 | *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1726 | } |
| 1727 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 1728 | *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4); |
| 1729 | *bit = pin_num % RV1108_DRV_PINS_PER_REG; |
| 1730 | *bit *= RV1108_DRV_BITS_PER_PIN; |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 1731 | } |
| 1732 | |
Andy Yan | 5caff7e | 2017-07-31 18:10:22 +0800 | [diff] [blame] | 1733 | #define RV1108_SCHMITT_PMU_OFFSET 0x30 |
| 1734 | #define RV1108_SCHMITT_GRF_OFFSET 0x388 |
| 1735 | #define RV1108_SCHMITT_BANK_STRIDE 8 |
| 1736 | #define RV1108_SCHMITT_PINS_PER_GRF_REG 16 |
| 1737 | #define RV1108_SCHMITT_PINS_PER_PMU_REG 8 |
| 1738 | |
| 1739 | static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1740 | int pin_num, |
| 1741 | struct regmap **regmap, |
| 1742 | int *reg, u8 *bit) |
| 1743 | { |
| 1744 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1745 | int pins_per_reg; |
| 1746 | |
| 1747 | if (bank->bank_num == 0) { |
| 1748 | *regmap = info->regmap_pmu; |
| 1749 | *reg = RV1108_SCHMITT_PMU_OFFSET; |
| 1750 | pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG; |
| 1751 | } else { |
| 1752 | *regmap = info->regmap_base; |
| 1753 | *reg = RV1108_SCHMITT_GRF_OFFSET; |
| 1754 | pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG; |
| 1755 | *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; |
| 1756 | } |
| 1757 | *reg += ((pin_num / pins_per_reg) * 4); |
| 1758 | *bit = pin_num % pins_per_reg; |
| 1759 | |
| 1760 | return 0; |
| 1761 | } |
| 1762 | |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 1763 | #define RK3308_SCHMITT_PINS_PER_REG 8 |
| 1764 | #define RK3308_SCHMITT_BANK_STRIDE 16 |
| 1765 | #define RK3308_SCHMITT_GRF_OFFSET 0x1a0 |
| 1766 | |
| 1767 | static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1768 | int pin_num, struct regmap **regmap, |
| 1769 | int *reg, u8 *bit) |
| 1770 | { |
| 1771 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1772 | |
| 1773 | *regmap = info->regmap_base; |
| 1774 | *reg = RK3308_SCHMITT_GRF_OFFSET; |
| 1775 | |
| 1776 | *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; |
| 1777 | *reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4); |
| 1778 | *bit = pin_num % RK3308_SCHMITT_PINS_PER_REG; |
| 1779 | |
| 1780 | return 0; |
| 1781 | } |
| 1782 | |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 1783 | #define RK2928_PULL_OFFSET 0x118 |
| 1784 | #define RK2928_PULL_PINS_PER_REG 16 |
| 1785 | #define RK2928_PULL_BANK_STRIDE 8 |
| 1786 | |
| 1787 | static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1788 | int pin_num, struct regmap **regmap, |
| 1789 | int *reg, u8 *bit) |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 1790 | { |
| 1791 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1792 | |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1793 | *regmap = info->regmap_base; |
| 1794 | *reg = RK2928_PULL_OFFSET; |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 1795 | *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; |
| 1796 | *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; |
| 1797 | |
| 1798 | *bit = pin_num % RK2928_PULL_PINS_PER_REG; |
| 1799 | }; |
| 1800 | |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 1801 | #define RK3128_PULL_OFFSET 0x118 |
| 1802 | |
| 1803 | static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1804 | int pin_num, struct regmap **regmap, |
| 1805 | int *reg, u8 *bit) |
| 1806 | { |
| 1807 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1808 | |
| 1809 | *regmap = info->regmap_base; |
| 1810 | *reg = RK3128_PULL_OFFSET; |
| 1811 | *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; |
| 1812 | *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4); |
| 1813 | |
| 1814 | *bit = pin_num % RK2928_PULL_PINS_PER_REG; |
| 1815 | } |
| 1816 | |
Heiko Stübner | bfc7a42 | 2014-05-05 13:58:00 +0200 | [diff] [blame] | 1817 | #define RK3188_PULL_OFFSET 0x164 |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 1818 | #define RK3188_PULL_BITS_PER_PIN 2 |
| 1819 | #define RK3188_PULL_PINS_PER_REG 8 |
| 1820 | #define RK3188_PULL_BANK_STRIDE 16 |
Heiko Stübner | 14dee86 | 2014-05-05 13:59:09 +0200 | [diff] [blame] | 1821 | #define RK3188_PULL_PMU_OFFSET 0x64 |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 1822 | |
| 1823 | static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1824 | int pin_num, struct regmap **regmap, |
| 1825 | int *reg, u8 *bit) |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 1826 | { |
| 1827 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1828 | |
| 1829 | /* The first 12 pins of the first bank are located elsewhere */ |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 1830 | if (bank->bank_num == 0 && pin_num < 12) { |
Heiko Stübner | 14dee86 | 2014-05-05 13:59:09 +0200 | [diff] [blame] | 1831 | *regmap = info->regmap_pmu ? info->regmap_pmu |
| 1832 | : bank->regmap_pull; |
| 1833 | *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1834 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 1835 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
| 1836 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 1837 | } else { |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 1838 | *regmap = info->regmap_pull ? info->regmap_pull |
| 1839 | : info->regmap_base; |
| 1840 | *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; |
| 1841 | |
Heiko Stübner | bfc7a42 | 2014-05-05 13:58:00 +0200 | [diff] [blame] | 1842 | /* correct the offset, as it is the 2nd pull register */ |
| 1843 | *reg -= 4; |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 1844 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
| 1845 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 1846 | |
| 1847 | /* |
| 1848 | * The bits in these registers have an inverse ordering |
| 1849 | * with the lowest pin being in bits 15:14 and the highest |
| 1850 | * pin in bits 1:0 |
| 1851 | */ |
| 1852 | *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); |
| 1853 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 1854 | } |
| 1855 | } |
| 1856 | |
Heiko Stübner | 304f077 | 2014-06-16 01:38:14 +0200 | [diff] [blame] | 1857 | #define RK3288_PULL_OFFSET 0x140 |
| 1858 | static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1859 | int pin_num, struct regmap **regmap, |
| 1860 | int *reg, u8 *bit) |
| 1861 | { |
| 1862 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1863 | |
| 1864 | /* The first 24 pins of the first bank are located in PMU */ |
| 1865 | if (bank->bank_num == 0) { |
| 1866 | *regmap = info->regmap_pmu; |
| 1867 | *reg = RK3188_PULL_PMU_OFFSET; |
| 1868 | |
| 1869 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 1870 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
| 1871 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 1872 | } else { |
| 1873 | *regmap = info->regmap_base; |
| 1874 | *reg = RK3288_PULL_OFFSET; |
| 1875 | |
| 1876 | /* correct the offset, as we're starting with the 2nd bank */ |
| 1877 | *reg -= 0x10; |
| 1878 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
| 1879 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 1880 | |
| 1881 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); |
| 1882 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 1883 | } |
| 1884 | } |
| 1885 | |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 1886 | #define RK3288_DRV_PMU_OFFSET 0x70 |
| 1887 | #define RK3288_DRV_GRF_OFFSET 0x1c0 |
| 1888 | #define RK3288_DRV_BITS_PER_PIN 2 |
| 1889 | #define RK3288_DRV_PINS_PER_REG 8 |
| 1890 | #define RK3288_DRV_BANK_STRIDE 16 |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 1891 | |
| 1892 | static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1893 | int pin_num, struct regmap **regmap, |
| 1894 | int *reg, u8 *bit) |
| 1895 | { |
| 1896 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1897 | |
| 1898 | /* The first 24 pins of the first bank are located in PMU */ |
| 1899 | if (bank->bank_num == 0) { |
| 1900 | *regmap = info->regmap_pmu; |
| 1901 | *reg = RK3288_DRV_PMU_OFFSET; |
| 1902 | |
| 1903 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); |
| 1904 | *bit = pin_num % RK3288_DRV_PINS_PER_REG; |
| 1905 | *bit *= RK3288_DRV_BITS_PER_PIN; |
| 1906 | } else { |
| 1907 | *regmap = info->regmap_base; |
| 1908 | *reg = RK3288_DRV_GRF_OFFSET; |
| 1909 | |
| 1910 | /* correct the offset, as we're starting with the 2nd bank */ |
| 1911 | *reg -= 0x10; |
| 1912 | *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; |
| 1913 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); |
| 1914 | |
| 1915 | *bit = (pin_num % RK3288_DRV_PINS_PER_REG); |
| 1916 | *bit *= RK3288_DRV_BITS_PER_PIN; |
| 1917 | } |
| 1918 | } |
| 1919 | |
Jeffy Chen | fea0fe6 | 2015-12-09 17:04:06 +0800 | [diff] [blame] | 1920 | #define RK3228_PULL_OFFSET 0x100 |
| 1921 | |
| 1922 | static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1923 | int pin_num, struct regmap **regmap, |
| 1924 | int *reg, u8 *bit) |
| 1925 | { |
| 1926 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1927 | |
| 1928 | *regmap = info->regmap_base; |
| 1929 | *reg = RK3228_PULL_OFFSET; |
| 1930 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
| 1931 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 1932 | |
| 1933 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); |
| 1934 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 1935 | } |
| 1936 | |
| 1937 | #define RK3228_DRV_GRF_OFFSET 0x200 |
| 1938 | |
| 1939 | static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1940 | int pin_num, struct regmap **regmap, |
| 1941 | int *reg, u8 *bit) |
| 1942 | { |
| 1943 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1944 | |
| 1945 | *regmap = info->regmap_base; |
| 1946 | *reg = RK3228_DRV_GRF_OFFSET; |
| 1947 | *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; |
| 1948 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); |
| 1949 | |
| 1950 | *bit = (pin_num % RK3288_DRV_PINS_PER_REG); |
| 1951 | *bit *= RK3288_DRV_BITS_PER_PIN; |
| 1952 | } |
| 1953 | |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 1954 | #define RK3308_PULL_OFFSET 0xa0 |
| 1955 | |
| 1956 | static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1957 | int pin_num, struct regmap **regmap, |
| 1958 | int *reg, u8 *bit) |
| 1959 | { |
| 1960 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1961 | |
| 1962 | *regmap = info->regmap_base; |
| 1963 | *reg = RK3308_PULL_OFFSET; |
| 1964 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
| 1965 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 1966 | |
| 1967 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); |
| 1968 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 1969 | } |
| 1970 | |
| 1971 | #define RK3308_DRV_GRF_OFFSET 0x100 |
| 1972 | |
| 1973 | static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1974 | int pin_num, struct regmap **regmap, |
| 1975 | int *reg, u8 *bit) |
| 1976 | { |
| 1977 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1978 | |
| 1979 | *regmap = info->regmap_base; |
| 1980 | *reg = RK3308_DRV_GRF_OFFSET; |
| 1981 | *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; |
| 1982 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); |
| 1983 | |
| 1984 | *bit = (pin_num % RK3288_DRV_PINS_PER_REG); |
| 1985 | *bit *= RK3288_DRV_BITS_PER_PIN; |
| 1986 | } |
| 1987 | |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 1988 | #define RK3368_PULL_GRF_OFFSET 0x100 |
| 1989 | #define RK3368_PULL_PMU_OFFSET 0x10 |
| 1990 | |
| 1991 | static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 1992 | int pin_num, struct regmap **regmap, |
| 1993 | int *reg, u8 *bit) |
| 1994 | { |
| 1995 | struct rockchip_pinctrl *info = bank->drvdata; |
| 1996 | |
| 1997 | /* The first 32 pins of the first bank are located in PMU */ |
| 1998 | if (bank->bank_num == 0) { |
| 1999 | *regmap = info->regmap_pmu; |
| 2000 | *reg = RK3368_PULL_PMU_OFFSET; |
| 2001 | |
| 2002 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 2003 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
| 2004 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 2005 | } else { |
| 2006 | *regmap = info->regmap_base; |
| 2007 | *reg = RK3368_PULL_GRF_OFFSET; |
| 2008 | |
| 2009 | /* correct the offset, as we're starting with the 2nd bank */ |
| 2010 | *reg -= 0x10; |
| 2011 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
| 2012 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 2013 | |
| 2014 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); |
| 2015 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 2016 | } |
| 2017 | } |
| 2018 | |
| 2019 | #define RK3368_DRV_PMU_OFFSET 0x20 |
| 2020 | #define RK3368_DRV_GRF_OFFSET 0x200 |
| 2021 | |
| 2022 | static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
| 2023 | int pin_num, struct regmap **regmap, |
| 2024 | int *reg, u8 *bit) |
| 2025 | { |
| 2026 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2027 | |
| 2028 | /* The first 32 pins of the first bank are located in PMU */ |
| 2029 | if (bank->bank_num == 0) { |
| 2030 | *regmap = info->regmap_pmu; |
| 2031 | *reg = RK3368_DRV_PMU_OFFSET; |
| 2032 | |
| 2033 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); |
| 2034 | *bit = pin_num % RK3288_DRV_PINS_PER_REG; |
| 2035 | *bit *= RK3288_DRV_BITS_PER_PIN; |
| 2036 | } else { |
| 2037 | *regmap = info->regmap_base; |
| 2038 | *reg = RK3368_DRV_GRF_OFFSET; |
| 2039 | |
| 2040 | /* correct the offset, as we're starting with the 2nd bank */ |
| 2041 | *reg -= 0x10; |
| 2042 | *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; |
| 2043 | *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4); |
| 2044 | |
| 2045 | *bit = (pin_num % RK3288_DRV_PINS_PER_REG); |
| 2046 | *bit *= RK3288_DRV_BITS_PER_PIN; |
| 2047 | } |
| 2048 | } |
| 2049 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2050 | #define RK3399_PULL_GRF_OFFSET 0xe040 |
| 2051 | #define RK3399_PULL_PMU_OFFSET 0x40 |
| 2052 | #define RK3399_DRV_3BITS_PER_PIN 3 |
| 2053 | |
| 2054 | static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, |
| 2055 | int pin_num, struct regmap **regmap, |
| 2056 | int *reg, u8 *bit) |
| 2057 | { |
| 2058 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2059 | |
| 2060 | /* The bank0:16 and bank1:32 pins are located in PMU */ |
| 2061 | if ((bank->bank_num == 0) || (bank->bank_num == 1)) { |
| 2062 | *regmap = info->regmap_pmu; |
| 2063 | *reg = RK3399_PULL_PMU_OFFSET; |
| 2064 | |
| 2065 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
| 2066 | |
| 2067 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 2068 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
| 2069 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 2070 | } else { |
| 2071 | *regmap = info->regmap_base; |
| 2072 | *reg = RK3399_PULL_GRF_OFFSET; |
| 2073 | |
| 2074 | /* correct the offset, as we're starting with the 3rd bank */ |
| 2075 | *reg -= 0x20; |
| 2076 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
| 2077 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
| 2078 | |
| 2079 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); |
| 2080 | *bit *= RK3188_PULL_BITS_PER_PIN; |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2084 | static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, |
| 2085 | int pin_num, struct regmap **regmap, |
| 2086 | int *reg, u8 *bit) |
| 2087 | { |
| 2088 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2089 | int drv_num = (pin_num / 8); |
| 2090 | |
| 2091 | /* The bank0:16 and bank1:32 pins are located in PMU */ |
| 2092 | if ((bank->bank_num == 0) || (bank->bank_num == 1)) |
| 2093 | *regmap = info->regmap_pmu; |
| 2094 | else |
| 2095 | *regmap = info->regmap_base; |
| 2096 | |
| 2097 | *reg = bank->drv[drv_num].offset; |
| 2098 | if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || |
| 2099 | (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) |
| 2100 | *bit = (pin_num % 8) * 3; |
| 2101 | else |
| 2102 | *bit = (pin_num % 8) * 2; |
| 2103 | } |
| 2104 | |
| 2105 | static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { |
| 2106 | { 2, 4, 8, 12, -1, -1, -1, -1 }, |
| 2107 | { 3, 6, 9, 12, -1, -1, -1, -1 }, |
| 2108 | { 5, 10, 15, 20, -1, -1, -1, -1 }, |
| 2109 | { 4, 6, 8, 10, 12, 14, 16, 18 }, |
| 2110 | { 4, 7, 10, 13, 16, 19, 22, 26 } |
| 2111 | }; |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2112 | |
| 2113 | static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank, |
| 2114 | int pin_num) |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2115 | { |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2116 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2117 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2118 | struct regmap *regmap; |
| 2119 | int reg, ret; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2120 | u32 data, temp, rmask_bits; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2121 | u8 bit; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2122 | int drv_type = bank->drv[pin_num / 8].drv_type; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2123 | |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2124 | ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2125 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2126 | switch (drv_type) { |
| 2127 | case DRV_TYPE_IO_1V8_3V0_AUTO: |
| 2128 | case DRV_TYPE_IO_3V3_ONLY: |
| 2129 | rmask_bits = RK3399_DRV_3BITS_PER_PIN; |
| 2130 | switch (bit) { |
| 2131 | case 0 ... 12: |
| 2132 | /* regular case, nothing to do */ |
| 2133 | break; |
| 2134 | case 15: |
| 2135 | /* |
| 2136 | * drive-strength offset is special, as it is |
| 2137 | * spread over 2 registers |
| 2138 | */ |
| 2139 | ret = regmap_read(regmap, reg, &data); |
| 2140 | if (ret) |
| 2141 | return ret; |
| 2142 | |
| 2143 | ret = regmap_read(regmap, reg + 0x4, &temp); |
| 2144 | if (ret) |
| 2145 | return ret; |
| 2146 | |
| 2147 | /* |
| 2148 | * the bit data[15] contains bit 0 of the value |
| 2149 | * while temp[1:0] contains bits 2 and 1 |
| 2150 | */ |
| 2151 | data >>= 15; |
| 2152 | temp &= 0x3; |
| 2153 | temp <<= 1; |
| 2154 | data |= temp; |
| 2155 | |
| 2156 | return rockchip_perpin_drv_list[drv_type][data]; |
| 2157 | case 18 ... 21: |
| 2158 | /* setting fully enclosed in the second register */ |
| 2159 | reg += 4; |
| 2160 | bit -= 16; |
| 2161 | break; |
| 2162 | default: |
| 2163 | dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", |
| 2164 | bit, drv_type); |
| 2165 | return -EINVAL; |
| 2166 | } |
| 2167 | |
| 2168 | break; |
| 2169 | case DRV_TYPE_IO_DEFAULT: |
| 2170 | case DRV_TYPE_IO_1V8_OR_3V0: |
| 2171 | case DRV_TYPE_IO_1V8_ONLY: |
| 2172 | rmask_bits = RK3288_DRV_BITS_PER_PIN; |
| 2173 | break; |
| 2174 | default: |
| 2175 | dev_err(info->dev, "unsupported pinctrl drive type: %d\n", |
| 2176 | drv_type); |
| 2177 | return -EINVAL; |
| 2178 | } |
| 2179 | |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2180 | ret = regmap_read(regmap, reg, &data); |
| 2181 | if (ret) |
| 2182 | return ret; |
| 2183 | |
| 2184 | data >>= bit; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2185 | data &= (1 << rmask_bits) - 1; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2186 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2187 | return rockchip_perpin_drv_list[drv_type][data]; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2188 | } |
| 2189 | |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2190 | static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank, |
| 2191 | int pin_num, int strength) |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2192 | { |
| 2193 | struct rockchip_pinctrl *info = bank->drvdata; |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2194 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2195 | struct regmap *regmap; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2196 | int reg, ret, i; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2197 | u32 data, rmask, rmask_bits, temp; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2198 | u8 bit; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2199 | int drv_type = bank->drv[pin_num / 8].drv_type; |
| 2200 | |
| 2201 | dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", |
| 2202 | bank->bank_num, pin_num, strength); |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2203 | |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2204 | ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2205 | |
| 2206 | ret = -EINVAL; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2207 | for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) { |
| 2208 | if (rockchip_perpin_drv_list[drv_type][i] == strength) { |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2209 | ret = i; |
| 2210 | break; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2211 | } else if (rockchip_perpin_drv_list[drv_type][i] < 0) { |
| 2212 | ret = rockchip_perpin_drv_list[drv_type][i]; |
| 2213 | break; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2214 | } |
| 2215 | } |
| 2216 | |
| 2217 | if (ret < 0) { |
| 2218 | dev_err(info->dev, "unsupported driver strength %d\n", |
| 2219 | strength); |
| 2220 | return ret; |
| 2221 | } |
| 2222 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2223 | switch (drv_type) { |
| 2224 | case DRV_TYPE_IO_1V8_3V0_AUTO: |
| 2225 | case DRV_TYPE_IO_3V3_ONLY: |
| 2226 | rmask_bits = RK3399_DRV_3BITS_PER_PIN; |
| 2227 | switch (bit) { |
| 2228 | case 0 ... 12: |
| 2229 | /* regular case, nothing to do */ |
| 2230 | break; |
| 2231 | case 15: |
| 2232 | /* |
| 2233 | * drive-strength offset is special, as it is spread |
| 2234 | * over 2 registers, the bit data[15] contains bit 0 |
| 2235 | * of the value while temp[1:0] contains bits 2 and 1 |
| 2236 | */ |
| 2237 | data = (ret & 0x1) << 15; |
| 2238 | temp = (ret >> 0x1) & 0x3; |
| 2239 | |
| 2240 | rmask = BIT(15) | BIT(31); |
| 2241 | data |= BIT(31); |
| 2242 | ret = regmap_update_bits(regmap, reg, rmask, data); |
John Keeping | f07bedc | 2017-03-23 10:59:28 +0000 | [diff] [blame] | 2243 | if (ret) |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2244 | return ret; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2245 | |
| 2246 | rmask = 0x3 | (0x3 << 16); |
| 2247 | temp |= (0x3 << 16); |
| 2248 | reg += 0x4; |
| 2249 | ret = regmap_update_bits(regmap, reg, rmask, temp); |
| 2250 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2251 | return ret; |
| 2252 | case 18 ... 21: |
| 2253 | /* setting fully enclosed in the second register */ |
| 2254 | reg += 4; |
| 2255 | bit -= 16; |
| 2256 | break; |
| 2257 | default: |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2258 | dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", |
| 2259 | bit, drv_type); |
| 2260 | return -EINVAL; |
| 2261 | } |
| 2262 | break; |
| 2263 | case DRV_TYPE_IO_DEFAULT: |
| 2264 | case DRV_TYPE_IO_1V8_OR_3V0: |
| 2265 | case DRV_TYPE_IO_1V8_ONLY: |
| 2266 | rmask_bits = RK3288_DRV_BITS_PER_PIN; |
| 2267 | break; |
| 2268 | default: |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2269 | dev_err(info->dev, "unsupported pinctrl drive type: %d\n", |
| 2270 | drv_type); |
| 2271 | return -EINVAL; |
| 2272 | } |
| 2273 | |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2274 | /* enable the write to the equivalent lower bits */ |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2275 | data = ((1 << rmask_bits) - 1) << (bit + 16); |
Sonny Rao | 99e872d | 2014-07-31 22:58:00 -0700 | [diff] [blame] | 2276 | rmask = data | (data >> 16); |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2277 | data |= (ret << bit); |
| 2278 | |
Sonny Rao | 99e872d | 2014-07-31 22:58:00 -0700 | [diff] [blame] | 2279 | ret = regmap_update_bits(regmap, reg, rmask, data); |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2280 | |
| 2281 | return ret; |
| 2282 | } |
| 2283 | |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 2284 | static int rockchip_pull_list[PULL_TYPE_MAX][4] = { |
| 2285 | { |
| 2286 | PIN_CONFIG_BIAS_DISABLE, |
| 2287 | PIN_CONFIG_BIAS_PULL_UP, |
| 2288 | PIN_CONFIG_BIAS_PULL_DOWN, |
| 2289 | PIN_CONFIG_BIAS_BUS_HOLD |
| 2290 | }, |
| 2291 | { |
| 2292 | PIN_CONFIG_BIAS_DISABLE, |
| 2293 | PIN_CONFIG_BIAS_PULL_DOWN, |
| 2294 | PIN_CONFIG_BIAS_DISABLE, |
| 2295 | PIN_CONFIG_BIAS_PULL_UP |
| 2296 | }, |
| 2297 | }; |
| 2298 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2299 | static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) |
| 2300 | { |
| 2301 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2302 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2303 | struct regmap *regmap; |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 2304 | int reg, ret, pull_type; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2305 | u8 bit; |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2306 | u32 data; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2307 | |
| 2308 | /* rk3066b does support any pulls */ |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2309 | if (ctrl->type == RK3066B) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2310 | return PIN_CONFIG_BIAS_DISABLE; |
| 2311 | |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2312 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
| 2313 | |
| 2314 | ret = regmap_read(regmap, reg, &data); |
| 2315 | if (ret) |
| 2316 | return ret; |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2317 | |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2318 | switch (ctrl->type) { |
| 2319 | case RK2928: |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 2320 | case RK3128: |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2321 | return !(data & BIT(bit)) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2322 | ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT |
| 2323 | : PIN_CONFIG_BIAS_DISABLE; |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 2324 | case PX30: |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 2325 | case RV1108: |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2326 | case RK3188: |
Heiko Stübner | 66d750e | 2014-07-20 01:49:17 +0200 | [diff] [blame] | 2327 | case RK3288: |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 2328 | case RK3308: |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 2329 | case RK3368: |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2330 | case RK3399: |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 2331 | pull_type = bank->pull_type[pin_num / 8]; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2332 | data >>= bit; |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2333 | data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; |
| 2334 | |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 2335 | return rockchip_pull_list[pull_type][data]; |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2336 | default: |
| 2337 | dev_err(info->dev, "unsupported pinctrl type\n"); |
| 2338 | return -EINVAL; |
| 2339 | }; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2340 | } |
| 2341 | |
| 2342 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, |
| 2343 | int pin_num, int pull) |
| 2344 | { |
| 2345 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2346 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2347 | struct regmap *regmap; |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 2348 | int reg, ret, i, pull_type; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2349 | u8 bit; |
Sonny Rao | 99e872d | 2014-07-31 22:58:00 -0700 | [diff] [blame] | 2350 | u32 data, rmask; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2351 | |
| 2352 | dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", |
| 2353 | bank->bank_num, pin_num, pull); |
| 2354 | |
| 2355 | /* rk3066b does support any pulls */ |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2356 | if (ctrl->type == RK3066B) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2357 | return pull ? -EINVAL : 0; |
| 2358 | |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2359 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2360 | |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2361 | switch (ctrl->type) { |
| 2362 | case RK2928: |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 2363 | case RK3128: |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2364 | data = BIT(bit + 16); |
| 2365 | if (pull == PIN_CONFIG_BIAS_DISABLE) |
| 2366 | data |= BIT(bit); |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2367 | ret = regmap_write(regmap, reg, data); |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2368 | break; |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 2369 | case PX30: |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 2370 | case RV1108: |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2371 | case RK3188: |
Heiko Stübner | 66d750e | 2014-07-20 01:49:17 +0200 | [diff] [blame] | 2372 | case RK3288: |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 2373 | case RK3308: |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 2374 | case RK3368: |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2375 | case RK3399: |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 2376 | pull_type = bank->pull_type[pin_num / 8]; |
| 2377 | ret = -EINVAL; |
| 2378 | for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]); |
| 2379 | i++) { |
| 2380 | if (rockchip_pull_list[pull_type][i] == pull) { |
| 2381 | ret = i; |
| 2382 | break; |
| 2383 | } |
| 2384 | } |
| 2385 | |
| 2386 | if (ret < 0) { |
| 2387 | dev_err(info->dev, "unsupported pull setting %d\n", |
| 2388 | pull); |
| 2389 | return ret; |
| 2390 | } |
| 2391 | |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2392 | /* enable the write to the equivalent lower bits */ |
| 2393 | data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); |
Sonny Rao | 99e872d | 2014-07-31 22:58:00 -0700 | [diff] [blame] | 2394 | rmask = data | (data >> 16); |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 2395 | data |= (ret << bit); |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2396 | |
Sonny Rao | 99e872d | 2014-07-31 22:58:00 -0700 | [diff] [blame] | 2397 | ret = regmap_update_bits(regmap, reg, rmask, data); |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2398 | break; |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2399 | default: |
| 2400 | dev_err(info->dev, "unsupported pinctrl type\n"); |
| 2401 | return -EINVAL; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2402 | } |
| 2403 | |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 2404 | return ret; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2405 | } |
| 2406 | |
david.wu | 728d3f5 | 2017-03-02 15:11:24 +0800 | [diff] [blame] | 2407 | #define RK3328_SCHMITT_BITS_PER_PIN 1 |
| 2408 | #define RK3328_SCHMITT_PINS_PER_REG 16 |
| 2409 | #define RK3328_SCHMITT_BANK_STRIDE 8 |
| 2410 | #define RK3328_SCHMITT_GRF_OFFSET 0x380 |
| 2411 | |
| 2412 | static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, |
| 2413 | int pin_num, |
| 2414 | struct regmap **regmap, |
| 2415 | int *reg, u8 *bit) |
| 2416 | { |
| 2417 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2418 | |
| 2419 | *regmap = info->regmap_base; |
| 2420 | *reg = RK3328_SCHMITT_GRF_OFFSET; |
| 2421 | |
| 2422 | *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; |
| 2423 | *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4); |
| 2424 | *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG; |
| 2425 | |
| 2426 | return 0; |
| 2427 | } |
| 2428 | |
david.wu | e3b357d | 2017-03-02 15:11:23 +0800 | [diff] [blame] | 2429 | static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num) |
| 2430 | { |
| 2431 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2432 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
| 2433 | struct regmap *regmap; |
| 2434 | int reg, ret; |
| 2435 | u8 bit; |
| 2436 | u32 data; |
| 2437 | |
| 2438 | ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); |
| 2439 | if (ret) |
| 2440 | return ret; |
| 2441 | |
| 2442 | ret = regmap_read(regmap, reg, &data); |
| 2443 | if (ret) |
| 2444 | return ret; |
| 2445 | |
| 2446 | data >>= bit; |
| 2447 | return data & 0x1; |
| 2448 | } |
| 2449 | |
| 2450 | static int rockchip_set_schmitt(struct rockchip_pin_bank *bank, |
| 2451 | int pin_num, int enable) |
| 2452 | { |
| 2453 | struct rockchip_pinctrl *info = bank->drvdata; |
| 2454 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
| 2455 | struct regmap *regmap; |
| 2456 | int reg, ret; |
david.wu | e3b357d | 2017-03-02 15:11:23 +0800 | [diff] [blame] | 2457 | u8 bit; |
| 2458 | u32 data, rmask; |
| 2459 | |
| 2460 | dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", |
| 2461 | bank->bank_num, pin_num, enable); |
| 2462 | |
| 2463 | ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); |
| 2464 | if (ret) |
| 2465 | return ret; |
| 2466 | |
david.wu | e3b357d | 2017-03-02 15:11:23 +0800 | [diff] [blame] | 2467 | /* enable the write to the equivalent lower bits */ |
| 2468 | data = BIT(bit + 16) | (enable << bit); |
| 2469 | rmask = BIT(bit + 16) | BIT(bit); |
| 2470 | |
John Keeping | f07bedc | 2017-03-23 10:59:28 +0000 | [diff] [blame] | 2471 | return regmap_update_bits(regmap, reg, rmask, data); |
david.wu | e3b357d | 2017-03-02 15:11:23 +0800 | [diff] [blame] | 2472 | } |
| 2473 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2474 | /* |
| 2475 | * Pinmux_ops handling |
| 2476 | */ |
| 2477 | |
| 2478 | static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) |
| 2479 | { |
| 2480 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 2481 | |
| 2482 | return info->nfunctions; |
| 2483 | } |
| 2484 | |
| 2485 | static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, |
| 2486 | unsigned selector) |
| 2487 | { |
| 2488 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 2489 | |
| 2490 | return info->functions[selector].name; |
| 2491 | } |
| 2492 | |
| 2493 | static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, |
| 2494 | unsigned selector, const char * const **groups, |
| 2495 | unsigned * const num_groups) |
| 2496 | { |
| 2497 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 2498 | |
| 2499 | *groups = info->functions[selector].groups; |
| 2500 | *num_groups = info->functions[selector].ngroups; |
| 2501 | |
| 2502 | return 0; |
| 2503 | } |
| 2504 | |
Linus Walleij | 03e9f0c | 2014-09-03 13:02:56 +0200 | [diff] [blame] | 2505 | static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, |
| 2506 | unsigned group) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2507 | { |
| 2508 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 2509 | const unsigned int *pins = info->groups[group].pins; |
| 2510 | const struct rockchip_pin_config *data = info->groups[group].data; |
| 2511 | struct rockchip_pin_bank *bank; |
Heiko Stübner | 1479718 | 2014-03-26 00:57:00 +0100 | [diff] [blame] | 2512 | int cnt, ret = 0; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2513 | |
| 2514 | dev_dbg(info->dev, "enable function %s group %s\n", |
| 2515 | info->functions[selector].name, info->groups[group].name); |
| 2516 | |
| 2517 | /* |
Markus Elfring | 85dc397 | 2017-12-23 22:22:54 +0100 | [diff] [blame] | 2518 | * for each pin in the pin group selected, program the corresponding |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2519 | * pin function number in the config register. |
| 2520 | */ |
| 2521 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { |
| 2522 | bank = pin_to_bank(info, pins[cnt]); |
Heiko Stübner | 1479718 | 2014-03-26 00:57:00 +0100 | [diff] [blame] | 2523 | ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, |
| 2524 | data[cnt].func); |
| 2525 | if (ret) |
| 2526 | break; |
| 2527 | } |
| 2528 | |
| 2529 | if (ret) { |
| 2530 | /* revert the already done pin settings */ |
| 2531 | for (cnt--; cnt >= 0; cnt--) |
| 2532 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); |
| 2533 | |
| 2534 | return ret; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2535 | } |
| 2536 | |
| 2537 | return 0; |
| 2538 | } |
| 2539 | |
Caesar Wang | 6ba20a0 | 2016-03-15 15:55:45 +0800 | [diff] [blame] | 2540 | static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
| 2541 | { |
| 2542 | struct rockchip_pin_bank *bank = gpiochip_get_data(chip); |
| 2543 | u32 data; |
Brian Norris | 5c9d8c4 | 2017-12-12 09:43:43 -0800 | [diff] [blame] | 2544 | int ret; |
Caesar Wang | 6ba20a0 | 2016-03-15 15:55:45 +0800 | [diff] [blame] | 2545 | |
Brian Norris | 5c9d8c4 | 2017-12-12 09:43:43 -0800 | [diff] [blame] | 2546 | ret = clk_enable(bank->clk); |
| 2547 | if (ret < 0) { |
| 2548 | dev_err(bank->drvdata->dev, |
| 2549 | "failed to enable clock for bank %s\n", bank->name); |
| 2550 | return ret; |
| 2551 | } |
Caesar Wang | 6ba20a0 | 2016-03-15 15:55:45 +0800 | [diff] [blame] | 2552 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
Brian Norris | 5c9d8c4 | 2017-12-12 09:43:43 -0800 | [diff] [blame] | 2553 | clk_disable(bank->clk); |
Caesar Wang | 6ba20a0 | 2016-03-15 15:55:45 +0800 | [diff] [blame] | 2554 | |
Matti Vaittinen | 3c82787 | 2020-02-14 15:57:12 +0200 | [diff] [blame] | 2555 | if (data & BIT(offset)) |
| 2556 | return GPIO_LINE_DIRECTION_OUT; |
| 2557 | |
| 2558 | return GPIO_LINE_DIRECTION_IN; |
Caesar Wang | 6ba20a0 | 2016-03-15 15:55:45 +0800 | [diff] [blame] | 2559 | } |
| 2560 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2561 | /* |
| 2562 | * The calls to gpio_direction_output() and gpio_direction_input() |
| 2563 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() |
| 2564 | * function called from the gpiolib interface). |
| 2565 | */ |
Doug Anderson | e5c2c9d | 2014-10-21 10:47:33 -0700 | [diff] [blame] | 2566 | static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, |
| 2567 | int pin, bool input) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2568 | { |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2569 | struct rockchip_pin_bank *bank; |
Doug Anderson | e5c2c9d | 2014-10-21 10:47:33 -0700 | [diff] [blame] | 2570 | int ret; |
Doug Anderson | fab262f | 2014-10-21 10:47:35 -0700 | [diff] [blame] | 2571 | unsigned long flags; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2572 | u32 data; |
| 2573 | |
Linus Walleij | 03bf81f | 2015-12-08 09:39:13 +0100 | [diff] [blame] | 2574 | bank = gpiochip_get_data(chip); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2575 | |
Heiko Stübner | 1479718 | 2014-03-26 00:57:00 +0100 | [diff] [blame] | 2576 | ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); |
| 2577 | if (ret < 0) |
| 2578 | return ret; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2579 | |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 2580 | clk_enable(bank->clk); |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 2581 | raw_spin_lock_irqsave(&bank->slock, flags); |
Doug Anderson | fab262f | 2014-10-21 10:47:35 -0700 | [diff] [blame] | 2582 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2583 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
| 2584 | /* set bit to 1 for output, 0 for input */ |
| 2585 | if (!input) |
| 2586 | data |= BIT(pin); |
| 2587 | else |
| 2588 | data &= ~BIT(pin); |
| 2589 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); |
| 2590 | |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 2591 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 2592 | clk_disable(bank->clk); |
Doug Anderson | fab262f | 2014-10-21 10:47:35 -0700 | [diff] [blame] | 2593 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2594 | return 0; |
| 2595 | } |
| 2596 | |
Doug Anderson | e5c2c9d | 2014-10-21 10:47:33 -0700 | [diff] [blame] | 2597 | static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, |
| 2598 | struct pinctrl_gpio_range *range, |
| 2599 | unsigned offset, bool input) |
| 2600 | { |
| 2601 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 2602 | struct gpio_chip *chip; |
| 2603 | int pin; |
| 2604 | |
| 2605 | chip = range->gc; |
| 2606 | pin = offset - chip->base; |
| 2607 | dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", |
| 2608 | offset, range->name, pin, input ? "input" : "output"); |
| 2609 | |
| 2610 | return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, |
| 2611 | input); |
| 2612 | } |
| 2613 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2614 | static const struct pinmux_ops rockchip_pmx_ops = { |
| 2615 | .get_functions_count = rockchip_pmx_get_funcs_count, |
| 2616 | .get_function_name = rockchip_pmx_get_func_name, |
| 2617 | .get_function_groups = rockchip_pmx_get_groups, |
Linus Walleij | 03e9f0c | 2014-09-03 13:02:56 +0200 | [diff] [blame] | 2618 | .set_mux = rockchip_pmx_set, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2619 | .gpio_set_direction = rockchip_pmx_gpio_set_direction, |
| 2620 | }; |
| 2621 | |
| 2622 | /* |
| 2623 | * Pinconf_ops handling |
| 2624 | */ |
| 2625 | |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2626 | static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, |
| 2627 | enum pin_config_param pull) |
| 2628 | { |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2629 | switch (ctrl->type) { |
| 2630 | case RK2928: |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 2631 | case RK3128: |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2632 | return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || |
| 2633 | pull == PIN_CONFIG_BIAS_DISABLE); |
| 2634 | case RK3066B: |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2635 | return pull ? false : true; |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 2636 | case PX30: |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 2637 | case RV1108: |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2638 | case RK3188: |
Heiko Stübner | 66d750e | 2014-07-20 01:49:17 +0200 | [diff] [blame] | 2639 | case RK3288: |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 2640 | case RK3308: |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 2641 | case RK3368: |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 2642 | case RK3399: |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2643 | return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2644 | } |
| 2645 | |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 2646 | return false; |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2647 | } |
| 2648 | |
Doug Anderson | e5c2c9d | 2014-10-21 10:47:33 -0700 | [diff] [blame] | 2649 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value); |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 2650 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); |
| 2651 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2652 | /* set the pin config settings for a specified pin */ |
| 2653 | static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 2654 | unsigned long *configs, unsigned num_configs) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2655 | { |
| 2656 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 2657 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 2658 | enum pin_config_param param; |
Mika Westerberg | 58957d2 | 2017-01-23 15:34:32 +0300 | [diff] [blame] | 2659 | u32 arg; |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 2660 | int i; |
| 2661 | int rc; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2662 | |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 2663 | for (i = 0; i < num_configs; i++) { |
| 2664 | param = pinconf_to_config_param(configs[i]); |
| 2665 | arg = pinconf_to_config_argument(configs[i]); |
| 2666 | |
| 2667 | switch (param) { |
| 2668 | case PIN_CONFIG_BIAS_DISABLE: |
| 2669 | rc = rockchip_set_pull(bank, pin - bank->pin_base, |
| 2670 | param); |
| 2671 | if (rc) |
| 2672 | return rc; |
| 2673 | break; |
| 2674 | case PIN_CONFIG_BIAS_PULL_UP: |
| 2675 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 2676 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2677 | case PIN_CONFIG_BIAS_BUS_HOLD: |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 2678 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
| 2679 | return -ENOTSUPP; |
| 2680 | |
| 2681 | if (!arg) |
| 2682 | return -EINVAL; |
| 2683 | |
| 2684 | rc = rockchip_set_pull(bank, pin - bank->pin_base, |
| 2685 | param); |
| 2686 | if (rc) |
| 2687 | return rc; |
| 2688 | break; |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 2689 | case PIN_CONFIG_OUTPUT: |
Doug Anderson | e5c2c9d | 2014-10-21 10:47:33 -0700 | [diff] [blame] | 2690 | rockchip_gpio_set(&bank->gpio_chip, |
| 2691 | pin - bank->pin_base, arg); |
| 2692 | rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, |
| 2693 | pin - bank->pin_base, false); |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 2694 | if (rc) |
| 2695 | return rc; |
| 2696 | break; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2697 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 2698 | /* rk3288 is the first with per-pin drive-strength */ |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2699 | if (!info->ctrl->drv_calc_reg) |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2700 | return -ENOTSUPP; |
| 2701 | |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2702 | rc = rockchip_set_drive_perpin(bank, |
| 2703 | pin - bank->pin_base, arg); |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2704 | if (rc < 0) |
| 2705 | return rc; |
| 2706 | break; |
david.wu | e3b357d | 2017-03-02 15:11:23 +0800 | [diff] [blame] | 2707 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
| 2708 | if (!info->ctrl->schmitt_calc_reg) |
| 2709 | return -ENOTSUPP; |
| 2710 | |
| 2711 | rc = rockchip_set_schmitt(bank, |
| 2712 | pin - bank->pin_base, arg); |
| 2713 | if (rc < 0) |
| 2714 | return rc; |
| 2715 | break; |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 2716 | default: |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2717 | return -ENOTSUPP; |
Sherman Yin | 03b054e | 2013-08-27 11:32:12 -0700 | [diff] [blame] | 2718 | break; |
| 2719 | } |
| 2720 | } /* for each config */ |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2721 | |
| 2722 | return 0; |
| 2723 | } |
| 2724 | |
| 2725 | /* get the pin config settings for a specified pin */ |
| 2726 | static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, |
| 2727 | unsigned long *config) |
| 2728 | { |
| 2729 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); |
| 2730 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); |
| 2731 | enum pin_config_param param = pinconf_to_config_param(*config); |
Heiko Stübner | dab3eba | 2014-04-23 14:27:51 +0200 | [diff] [blame] | 2732 | u16 arg; |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 2733 | int rc; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2734 | |
| 2735 | switch (param) { |
| 2736 | case PIN_CONFIG_BIAS_DISABLE: |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2737 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2738 | return -EINVAL; |
| 2739 | |
Heiko Stübner | dab3eba | 2014-04-23 14:27:51 +0200 | [diff] [blame] | 2740 | arg = 0; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2741 | break; |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2742 | case PIN_CONFIG_BIAS_PULL_UP: |
| 2743 | case PIN_CONFIG_BIAS_PULL_DOWN: |
| 2744 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2745 | case PIN_CONFIG_BIAS_BUS_HOLD: |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2746 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
| 2747 | return -ENOTSUPP; |
| 2748 | |
| 2749 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
| 2750 | return -EINVAL; |
| 2751 | |
Heiko Stübner | dab3eba | 2014-04-23 14:27:51 +0200 | [diff] [blame] | 2752 | arg = 1; |
Heiko Stübner | 44b6d93 | 2013-06-16 17:41:16 +0200 | [diff] [blame] | 2753 | break; |
Heiko Stübner | a076e2e | 2014-04-23 14:28:59 +0200 | [diff] [blame] | 2754 | case PIN_CONFIG_OUTPUT: |
| 2755 | rc = rockchip_get_mux(bank, pin - bank->pin_base); |
| 2756 | if (rc != RK_FUNC_GPIO) |
| 2757 | return -EINVAL; |
| 2758 | |
| 2759 | rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); |
| 2760 | if (rc < 0) |
| 2761 | return rc; |
| 2762 | |
| 2763 | arg = rc ? 1 : 0; |
| 2764 | break; |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2765 | case PIN_CONFIG_DRIVE_STRENGTH: |
| 2766 | /* rk3288 is the first with per-pin drive-strength */ |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2767 | if (!info->ctrl->drv_calc_reg) |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2768 | return -ENOTSUPP; |
| 2769 | |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 2770 | rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); |
Heiko Stübner | b547c80 | 2014-07-20 01:50:11 +0200 | [diff] [blame] | 2771 | if (rc < 0) |
| 2772 | return rc; |
| 2773 | |
| 2774 | arg = rc; |
| 2775 | break; |
david.wu | e3b357d | 2017-03-02 15:11:23 +0800 | [diff] [blame] | 2776 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: |
| 2777 | if (!info->ctrl->schmitt_calc_reg) |
| 2778 | return -ENOTSUPP; |
| 2779 | |
| 2780 | rc = rockchip_get_schmitt(bank, pin - bank->pin_base); |
| 2781 | if (rc < 0) |
| 2782 | return rc; |
| 2783 | |
| 2784 | arg = rc; |
| 2785 | break; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2786 | default: |
| 2787 | return -ENOTSUPP; |
| 2788 | break; |
| 2789 | } |
| 2790 | |
Heiko Stübner | dab3eba | 2014-04-23 14:27:51 +0200 | [diff] [blame] | 2791 | *config = pinconf_to_config_packed(param, arg); |
| 2792 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2793 | return 0; |
| 2794 | } |
| 2795 | |
| 2796 | static const struct pinconf_ops rockchip_pinconf_ops = { |
| 2797 | .pin_config_get = rockchip_pinconf_get, |
| 2798 | .pin_config_set = rockchip_pinconf_set, |
Heiko Stübner | ed62f2f | 2014-07-20 01:48:45 +0200 | [diff] [blame] | 2799 | .is_generic = true, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2800 | }; |
| 2801 | |
Heiko Stübner | 65fca61 | 2013-10-16 01:07:49 +0200 | [diff] [blame] | 2802 | static const struct of_device_id rockchip_bank_match[] = { |
| 2803 | { .compatible = "rockchip,gpio-bank" }, |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 2804 | { .compatible = "rockchip,rk3188-gpio-bank0" }, |
Heiko Stübner | 65fca61 | 2013-10-16 01:07:49 +0200 | [diff] [blame] | 2805 | {}, |
| 2806 | }; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2807 | |
| 2808 | static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, |
| 2809 | struct device_node *np) |
| 2810 | { |
| 2811 | struct device_node *child; |
| 2812 | |
| 2813 | for_each_child_of_node(np, child) { |
Heiko Stübner | 65fca61 | 2013-10-16 01:07:49 +0200 | [diff] [blame] | 2814 | if (of_match_node(rockchip_bank_match, child)) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2815 | continue; |
| 2816 | |
| 2817 | info->nfunctions++; |
| 2818 | info->ngroups += of_get_child_count(child); |
| 2819 | } |
| 2820 | } |
| 2821 | |
| 2822 | static int rockchip_pinctrl_parse_groups(struct device_node *np, |
| 2823 | struct rockchip_pin_group *grp, |
| 2824 | struct rockchip_pinctrl *info, |
| 2825 | u32 index) |
| 2826 | { |
| 2827 | struct rockchip_pin_bank *bank; |
| 2828 | int size; |
| 2829 | const __be32 *list; |
| 2830 | int num; |
| 2831 | int i, j; |
| 2832 | int ret; |
| 2833 | |
Rob Herring | 94f4e54 | 2018-08-27 20:52:41 -0500 | [diff] [blame] | 2834 | dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2835 | |
| 2836 | /* Initialise group */ |
| 2837 | grp->name = np->name; |
| 2838 | |
| 2839 | /* |
| 2840 | * the binding format is rockchip,pins = <bank pin mux CONFIG>, |
| 2841 | * do sanity check and calculate pins number |
| 2842 | */ |
| 2843 | list = of_get_property(np, "rockchip,pins", &size); |
| 2844 | /* we do not check return since it's safe node passed down */ |
| 2845 | size /= sizeof(*list); |
| 2846 | if (!size || size % 4) { |
| 2847 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); |
| 2848 | return -EINVAL; |
| 2849 | } |
| 2850 | |
| 2851 | grp->npins = size / 4; |
| 2852 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 2853 | grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2854 | GFP_KERNEL); |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 2855 | grp->data = devm_kcalloc(info->dev, |
| 2856 | grp->npins, |
| 2857 | sizeof(struct rockchip_pin_config), |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2858 | GFP_KERNEL); |
| 2859 | if (!grp->pins || !grp->data) |
| 2860 | return -ENOMEM; |
| 2861 | |
| 2862 | for (i = 0, j = 0; i < size; i += 4, j++) { |
| 2863 | const __be32 *phandle; |
| 2864 | struct device_node *np_config; |
| 2865 | |
| 2866 | num = be32_to_cpu(*list++); |
| 2867 | bank = bank_num_to_bank(info, num); |
| 2868 | if (IS_ERR(bank)) |
| 2869 | return PTR_ERR(bank); |
| 2870 | |
| 2871 | grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); |
| 2872 | grp->data[j].func = be32_to_cpu(*list++); |
| 2873 | |
| 2874 | phandle = list++; |
| 2875 | if (!phandle) |
| 2876 | return -EINVAL; |
| 2877 | |
| 2878 | np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); |
Soren Brinkmann | dd4d01f | 2015-01-09 07:43:46 -0800 | [diff] [blame] | 2879 | ret = pinconf_generic_parse_dt_config(np_config, NULL, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2880 | &grp->data[j].configs, &grp->data[j].nconfigs); |
| 2881 | if (ret) |
| 2882 | return ret; |
| 2883 | } |
| 2884 | |
| 2885 | return 0; |
| 2886 | } |
| 2887 | |
| 2888 | static int rockchip_pinctrl_parse_functions(struct device_node *np, |
| 2889 | struct rockchip_pinctrl *info, |
| 2890 | u32 index) |
| 2891 | { |
| 2892 | struct device_node *child; |
| 2893 | struct rockchip_pmx_func *func; |
| 2894 | struct rockchip_pin_group *grp; |
| 2895 | int ret; |
| 2896 | static u32 grp_index; |
| 2897 | u32 i = 0; |
| 2898 | |
Rob Herring | 94f4e54 | 2018-08-27 20:52:41 -0500 | [diff] [blame] | 2899 | dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2900 | |
| 2901 | func = &info->functions[index]; |
| 2902 | |
| 2903 | /* Initialise function */ |
| 2904 | func->name = np->name; |
| 2905 | func->ngroups = of_get_child_count(np); |
| 2906 | if (func->ngroups <= 0) |
| 2907 | return 0; |
| 2908 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 2909 | func->groups = devm_kcalloc(info->dev, |
| 2910 | func->ngroups, sizeof(char *), GFP_KERNEL); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2911 | if (!func->groups) |
| 2912 | return -ENOMEM; |
| 2913 | |
| 2914 | for_each_child_of_node(np, child) { |
| 2915 | func->groups[i] = child->name; |
| 2916 | grp = &info->groups[grp_index++]; |
| 2917 | ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); |
Julia Lawall | f7a81b7 | 2015-12-21 17:39:47 +0100 | [diff] [blame] | 2918 | if (ret) { |
| 2919 | of_node_put(child); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2920 | return ret; |
Julia Lawall | f7a81b7 | 2015-12-21 17:39:47 +0100 | [diff] [blame] | 2921 | } |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2922 | } |
| 2923 | |
| 2924 | return 0; |
| 2925 | } |
| 2926 | |
| 2927 | static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, |
| 2928 | struct rockchip_pinctrl *info) |
| 2929 | { |
| 2930 | struct device *dev = &pdev->dev; |
| 2931 | struct device_node *np = dev->of_node; |
| 2932 | struct device_node *child; |
| 2933 | int ret; |
| 2934 | int i; |
| 2935 | |
| 2936 | rockchip_pinctrl_child_count(info, np); |
| 2937 | |
| 2938 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); |
| 2939 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); |
| 2940 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 2941 | info->functions = devm_kcalloc(dev, |
| 2942 | info->nfunctions, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2943 | sizeof(struct rockchip_pmx_func), |
| 2944 | GFP_KERNEL); |
Markus Elfring | 98c8ee7 | 2017-12-23 22:02:47 +0100 | [diff] [blame] | 2945 | if (!info->functions) |
Dafna Hirschfeld | c4f333b | 2020-05-06 12:14:24 +0200 | [diff] [blame] | 2946 | return -ENOMEM; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2947 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 2948 | info->groups = devm_kcalloc(dev, |
| 2949 | info->ngroups, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2950 | sizeof(struct rockchip_pin_group), |
| 2951 | GFP_KERNEL); |
Markus Elfring | 98c8ee7 | 2017-12-23 22:02:47 +0100 | [diff] [blame] | 2952 | if (!info->groups) |
Dafna Hirschfeld | c4f333b | 2020-05-06 12:14:24 +0200 | [diff] [blame] | 2953 | return -ENOMEM; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2954 | |
| 2955 | i = 0; |
| 2956 | |
| 2957 | for_each_child_of_node(np, child) { |
Heiko Stübner | 65fca61 | 2013-10-16 01:07:49 +0200 | [diff] [blame] | 2958 | if (of_match_node(rockchip_bank_match, child)) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2959 | continue; |
Heiko Stübner | 65fca61 | 2013-10-16 01:07:49 +0200 | [diff] [blame] | 2960 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2961 | ret = rockchip_pinctrl_parse_functions(child, info, i++); |
| 2962 | if (ret) { |
| 2963 | dev_err(&pdev->dev, "failed to parse function\n"); |
Julia Lawall | f7a81b7 | 2015-12-21 17:39:47 +0100 | [diff] [blame] | 2964 | of_node_put(child); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2965 | return ret; |
| 2966 | } |
| 2967 | } |
| 2968 | |
| 2969 | return 0; |
| 2970 | } |
| 2971 | |
| 2972 | static int rockchip_pinctrl_register(struct platform_device *pdev, |
| 2973 | struct rockchip_pinctrl *info) |
| 2974 | { |
| 2975 | struct pinctrl_desc *ctrldesc = &info->pctl; |
| 2976 | struct pinctrl_pin_desc *pindesc, *pdesc; |
| 2977 | struct rockchip_pin_bank *pin_bank; |
| 2978 | int pin, bank, ret; |
| 2979 | int k; |
| 2980 | |
| 2981 | ctrldesc->name = "rockchip-pinctrl"; |
| 2982 | ctrldesc->owner = THIS_MODULE; |
| 2983 | ctrldesc->pctlops = &rockchip_pctrl_ops; |
| 2984 | ctrldesc->pmxops = &rockchip_pmx_ops; |
| 2985 | ctrldesc->confops = &rockchip_pinconf_ops; |
| 2986 | |
Kees Cook | a86854d | 2018-06-12 14:07:58 -0700 | [diff] [blame] | 2987 | pindesc = devm_kcalloc(&pdev->dev, |
| 2988 | info->ctrl->nr_pins, sizeof(*pindesc), |
| 2989 | GFP_KERNEL); |
Markus Elfring | 98c8ee7 | 2017-12-23 22:02:47 +0100 | [diff] [blame] | 2990 | if (!pindesc) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2991 | return -ENOMEM; |
Markus Elfring | 98c8ee7 | 2017-12-23 22:02:47 +0100 | [diff] [blame] | 2992 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 2993 | ctrldesc->pins = pindesc; |
| 2994 | ctrldesc->npins = info->ctrl->nr_pins; |
| 2995 | |
| 2996 | pdesc = pindesc; |
| 2997 | for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { |
| 2998 | pin_bank = &info->ctrl->pin_banks[bank]; |
| 2999 | for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { |
| 3000 | pdesc->number = k; |
| 3001 | pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", |
| 3002 | pin_bank->name, pin); |
| 3003 | pdesc++; |
| 3004 | } |
| 3005 | } |
| 3006 | |
Doug Anderson | 0fb7dcb | 2014-10-21 10:47:34 -0700 | [diff] [blame] | 3007 | ret = rockchip_pinctrl_parse_dt(pdev, info); |
| 3008 | if (ret) |
| 3009 | return ret; |
| 3010 | |
Laxman Dewangan | 0085a2b | 2016-02-24 14:44:07 +0530 | [diff] [blame] | 3011 | info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 3012 | if (IS_ERR(info->pctl_dev)) { |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3013 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); |
Masahiro Yamada | 323de9e | 2015-06-09 13:01:16 +0900 | [diff] [blame] | 3014 | return PTR_ERR(info->pctl_dev); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3015 | } |
| 3016 | |
| 3017 | for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { |
| 3018 | pin_bank = &info->ctrl->pin_banks[bank]; |
| 3019 | pin_bank->grange.name = pin_bank->name; |
| 3020 | pin_bank->grange.id = bank; |
| 3021 | pin_bank->grange.pin_base = pin_bank->pin_base; |
| 3022 | pin_bank->grange.base = pin_bank->gpio_chip.base; |
| 3023 | pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; |
| 3024 | pin_bank->grange.gc = &pin_bank->gpio_chip; |
| 3025 | pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); |
| 3026 | } |
| 3027 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3028 | return 0; |
| 3029 | } |
| 3030 | |
| 3031 | /* |
| 3032 | * GPIO handling |
| 3033 | */ |
| 3034 | |
| 3035 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) |
| 3036 | { |
Linus Walleij | 03bf81f | 2015-12-08 09:39:13 +0100 | [diff] [blame] | 3037 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3038 | void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; |
| 3039 | unsigned long flags; |
| 3040 | u32 data; |
| 3041 | |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3042 | clk_enable(bank->clk); |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3043 | raw_spin_lock_irqsave(&bank->slock, flags); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3044 | |
| 3045 | data = readl(reg); |
| 3046 | data &= ~BIT(offset); |
| 3047 | if (value) |
| 3048 | data |= BIT(offset); |
| 3049 | writel(data, reg); |
| 3050 | |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3051 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3052 | clk_disable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3053 | } |
| 3054 | |
| 3055 | /* |
| 3056 | * Returns the level of the pin for input direction and setting of the DR |
| 3057 | * register for output gpios. |
| 3058 | */ |
| 3059 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) |
| 3060 | { |
Linus Walleij | 03bf81f | 2015-12-08 09:39:13 +0100 | [diff] [blame] | 3061 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3062 | u32 data; |
| 3063 | |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3064 | clk_enable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3065 | data = readl(bank->reg_base + GPIO_EXT_PORT); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3066 | clk_disable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3067 | data >>= offset; |
| 3068 | data &= 1; |
| 3069 | return data; |
| 3070 | } |
| 3071 | |
| 3072 | /* |
| 3073 | * gpiolib gpio_direction_input callback function. The setting of the pin |
Markus Elfring | 85dc397 | 2017-12-23 22:22:54 +0100 | [diff] [blame] | 3074 | * mux function as 'gpio input' will be handled by the pinctrl subsystem |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3075 | * interface. |
| 3076 | */ |
| 3077 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) |
| 3078 | { |
| 3079 | return pinctrl_gpio_direction_input(gc->base + offset); |
| 3080 | } |
| 3081 | |
| 3082 | /* |
| 3083 | * gpiolib gpio_direction_output callback function. The setting of the pin |
Markus Elfring | 85dc397 | 2017-12-23 22:22:54 +0100 | [diff] [blame] | 3084 | * mux function as 'gpio output' will be handled by the pinctrl subsystem |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3085 | * interface. |
| 3086 | */ |
| 3087 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, |
| 3088 | unsigned offset, int value) |
| 3089 | { |
| 3090 | rockchip_gpio_set(gc, offset, value); |
| 3091 | return pinctrl_gpio_direction_output(gc->base + offset); |
| 3092 | } |
| 3093 | |
Shawn Lin | b97038a | 2018-05-03 16:04:42 +0800 | [diff] [blame] | 3094 | static void rockchip_gpio_set_debounce(struct gpio_chip *gc, |
| 3095 | unsigned int offset, bool enable) |
| 3096 | { |
| 3097 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); |
| 3098 | void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; |
| 3099 | unsigned long flags; |
| 3100 | u32 data; |
| 3101 | |
| 3102 | clk_enable(bank->clk); |
| 3103 | raw_spin_lock_irqsave(&bank->slock, flags); |
| 3104 | |
| 3105 | data = readl(reg); |
| 3106 | if (enable) |
| 3107 | data |= BIT(offset); |
| 3108 | else |
| 3109 | data &= ~BIT(offset); |
| 3110 | writel(data, reg); |
| 3111 | |
| 3112 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
| 3113 | clk_disable(bank->clk); |
| 3114 | } |
| 3115 | |
| 3116 | /* |
| 3117 | * gpiolib set_config callback function. The setting of the pin |
| 3118 | * mux function as 'gpio output' will be handled by the pinctrl subsystem |
| 3119 | * interface. |
| 3120 | */ |
| 3121 | static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, |
| 3122 | unsigned long config) |
| 3123 | { |
| 3124 | enum pin_config_param param = pinconf_to_config_param(config); |
| 3125 | |
| 3126 | switch (param) { |
| 3127 | case PIN_CONFIG_INPUT_DEBOUNCE: |
| 3128 | rockchip_gpio_set_debounce(gc, offset, true); |
| 3129 | /* |
| 3130 | * Rockchip's gpio could only support up to one period |
| 3131 | * of the debounce clock(pclk), which is far away from |
| 3132 | * satisftying the requirement, as pclk is usually near |
| 3133 | * 100MHz shared by all peripherals. So the fact is it |
| 3134 | * has crippled debounce capability could only be useful |
| 3135 | * to prevent any spurious glitches from waking up the system |
| 3136 | * if the gpio is conguired as wakeup interrupt source. Let's |
| 3137 | * still return -ENOTSUPP as before, to make sure the caller |
| 3138 | * of gpiod_set_debounce won't change its behaviour. |
| 3139 | */ |
Anders Roxell | cd927f1 | 2019-07-26 13:28:12 +0200 | [diff] [blame] | 3140 | return -ENOTSUPP; |
Shawn Lin | b97038a | 2018-05-03 16:04:42 +0800 | [diff] [blame] | 3141 | default: |
| 3142 | return -ENOTSUPP; |
| 3143 | } |
| 3144 | } |
| 3145 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3146 | /* |
| 3147 | * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin |
| 3148 | * and a virtual IRQ, if not already present. |
| 3149 | */ |
| 3150 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) |
| 3151 | { |
Linus Walleij | 03bf81f | 2015-12-08 09:39:13 +0100 | [diff] [blame] | 3152 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3153 | unsigned int virq; |
| 3154 | |
| 3155 | if (!bank->domain) |
| 3156 | return -ENXIO; |
| 3157 | |
| 3158 | virq = irq_create_mapping(bank->domain, offset); |
| 3159 | |
| 3160 | return (virq) ? : -ENXIO; |
| 3161 | } |
| 3162 | |
| 3163 | static const struct gpio_chip rockchip_gpiolib_chip = { |
Jonas Gorski | 98c85d5 | 2015-10-11 17:34:19 +0200 | [diff] [blame] | 3164 | .request = gpiochip_generic_request, |
| 3165 | .free = gpiochip_generic_free, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3166 | .set = rockchip_gpio_set, |
| 3167 | .get = rockchip_gpio_get, |
Caesar Wang | 6ba20a0 | 2016-03-15 15:55:45 +0800 | [diff] [blame] | 3168 | .get_direction = rockchip_gpio_get_direction, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3169 | .direction_input = rockchip_gpio_direction_input, |
| 3170 | .direction_output = rockchip_gpio_direction_output, |
Shawn Lin | b97038a | 2018-05-03 16:04:42 +0800 | [diff] [blame] | 3171 | .set_config = rockchip_gpio_set_config, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3172 | .to_irq = rockchip_gpio_to_irq, |
| 3173 | .owner = THIS_MODULE, |
| 3174 | }; |
| 3175 | |
| 3176 | /* |
| 3177 | * Interrupt handling |
| 3178 | */ |
| 3179 | |
Thomas Gleixner | bd0b9ac | 2015-09-14 10:42:37 +0200 | [diff] [blame] | 3180 | static void rockchip_irq_demux(struct irq_desc *desc) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3181 | { |
Jiang Liu | 5663bb2 | 2015-06-04 12:13:16 +0800 | [diff] [blame] | 3182 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 3183 | struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3184 | u32 pend; |
| 3185 | |
| 3186 | dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); |
| 3187 | |
| 3188 | chained_irq_enter(chip, desc); |
| 3189 | |
| 3190 | pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); |
| 3191 | |
| 3192 | while (pend) { |
Thomas Gleixner | 415f748 | 2015-07-13 01:52:00 +0200 | [diff] [blame] | 3193 | unsigned int irq, virq; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3194 | |
| 3195 | irq = __ffs(pend); |
| 3196 | pend &= ~BIT(irq); |
| 3197 | virq = irq_linear_revmap(bank->domain, irq); |
| 3198 | |
| 3199 | if (!virq) { |
| 3200 | dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); |
| 3201 | continue; |
| 3202 | } |
| 3203 | |
| 3204 | dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); |
| 3205 | |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3206 | /* |
| 3207 | * Triggering IRQ on both rising and falling edge |
| 3208 | * needs manual intervention. |
| 3209 | */ |
| 3210 | if (bank->toggle_edge_mode & BIT(irq)) { |
Doug Anderson | 53b1bfc | 2014-12-22 10:47:29 -0800 | [diff] [blame] | 3211 | u32 data, data_old, polarity; |
| 3212 | unsigned long flags; |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3213 | |
Doug Anderson | 53b1bfc | 2014-12-22 10:47:29 -0800 | [diff] [blame] | 3214 | data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); |
| 3215 | do { |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3216 | raw_spin_lock_irqsave(&bank->slock, flags); |
Doug Anderson | 53b1bfc | 2014-12-22 10:47:29 -0800 | [diff] [blame] | 3217 | |
| 3218 | polarity = readl_relaxed(bank->reg_base + |
| 3219 | GPIO_INT_POLARITY); |
| 3220 | if (data & BIT(irq)) |
| 3221 | polarity &= ~BIT(irq); |
| 3222 | else |
| 3223 | polarity |= BIT(irq); |
| 3224 | writel(polarity, |
| 3225 | bank->reg_base + GPIO_INT_POLARITY); |
| 3226 | |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3227 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
Doug Anderson | 53b1bfc | 2014-12-22 10:47:29 -0800 | [diff] [blame] | 3228 | |
| 3229 | data_old = data; |
| 3230 | data = readl_relaxed(bank->reg_base + |
| 3231 | GPIO_EXT_PORT); |
| 3232 | } while ((data & BIT(irq)) != (data_old & BIT(irq))); |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3233 | } |
| 3234 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3235 | generic_handle_irq(virq); |
| 3236 | } |
| 3237 | |
| 3238 | chained_irq_exit(chip, desc); |
| 3239 | } |
| 3240 | |
| 3241 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) |
| 3242 | { |
| 3243 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 3244 | struct rockchip_pin_bank *bank = gc->private; |
| 3245 | u32 mask = BIT(d->hwirq); |
| 3246 | u32 polarity; |
| 3247 | u32 level; |
| 3248 | u32 data; |
Doug Anderson | fab262f | 2014-10-21 10:47:35 -0700 | [diff] [blame] | 3249 | unsigned long flags; |
Heiko Stübner | 1479718 | 2014-03-26 00:57:00 +0100 | [diff] [blame] | 3250 | int ret; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3251 | |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3252 | /* make sure the pin is configured as gpio input */ |
Brian Norris | 1d80df9 | 2017-06-23 13:59:11 -0700 | [diff] [blame] | 3253 | ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); |
Heiko Stübner | 1479718 | 2014-03-26 00:57:00 +0100 | [diff] [blame] | 3254 | if (ret < 0) |
| 3255 | return ret; |
| 3256 | |
Brian Norris | 1d80df9 | 2017-06-23 13:59:11 -0700 | [diff] [blame] | 3257 | clk_enable(bank->clk); |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3258 | raw_spin_lock_irqsave(&bank->slock, flags); |
Doug Anderson | fab262f | 2014-10-21 10:47:35 -0700 | [diff] [blame] | 3259 | |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3260 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
| 3261 | data &= ~mask; |
| 3262 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); |
| 3263 | |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3264 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
Doug Anderson | fab262f | 2014-10-21 10:47:35 -0700 | [diff] [blame] | 3265 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3266 | if (type & IRQ_TYPE_EDGE_BOTH) |
Thomas Gleixner | 2dbf1bc | 2015-06-23 15:52:50 +0200 | [diff] [blame] | 3267 | irq_set_handler_locked(d, handle_edge_irq); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3268 | else |
Thomas Gleixner | 2dbf1bc | 2015-06-23 15:52:50 +0200 | [diff] [blame] | 3269 | irq_set_handler_locked(d, handle_level_irq); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3270 | |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3271 | raw_spin_lock_irqsave(&bank->slock, flags); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3272 | irq_gc_lock(gc); |
| 3273 | |
| 3274 | level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); |
| 3275 | polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); |
| 3276 | |
| 3277 | switch (type) { |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3278 | case IRQ_TYPE_EDGE_BOTH: |
| 3279 | bank->toggle_edge_mode |= mask; |
| 3280 | level |= mask; |
| 3281 | |
| 3282 | /* |
| 3283 | * Determine gpio state. If 1 next interrupt should be falling |
| 3284 | * otherwise rising. |
| 3285 | */ |
| 3286 | data = readl(bank->reg_base + GPIO_EXT_PORT); |
| 3287 | if (data & mask) |
| 3288 | polarity &= ~mask; |
| 3289 | else |
| 3290 | polarity |= mask; |
| 3291 | break; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3292 | case IRQ_TYPE_EDGE_RISING: |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3293 | bank->toggle_edge_mode &= ~mask; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3294 | level |= mask; |
| 3295 | polarity |= mask; |
| 3296 | break; |
| 3297 | case IRQ_TYPE_EDGE_FALLING: |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3298 | bank->toggle_edge_mode &= ~mask; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3299 | level |= mask; |
| 3300 | polarity &= ~mask; |
| 3301 | break; |
| 3302 | case IRQ_TYPE_LEVEL_HIGH: |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3303 | bank->toggle_edge_mode &= ~mask; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3304 | level &= ~mask; |
| 3305 | polarity |= mask; |
| 3306 | break; |
| 3307 | case IRQ_TYPE_LEVEL_LOW: |
Heiko Stübner | 5a92750 | 2013-10-16 01:09:08 +0200 | [diff] [blame] | 3308 | bank->toggle_edge_mode &= ~mask; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3309 | level &= ~mask; |
| 3310 | polarity &= ~mask; |
| 3311 | break; |
| 3312 | default: |
Axel Lin | 7cc5f97 | 2013-06-23 08:48:34 +0800 | [diff] [blame] | 3313 | irq_gc_unlock(gc); |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3314 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
Brian Norris | 1d80df9 | 2017-06-23 13:59:11 -0700 | [diff] [blame] | 3315 | clk_disable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3316 | return -EINVAL; |
| 3317 | } |
| 3318 | |
| 3319 | writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); |
| 3320 | writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); |
| 3321 | |
| 3322 | irq_gc_unlock(gc); |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3323 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
Brian Norris | 1d80df9 | 2017-06-23 13:59:11 -0700 | [diff] [blame] | 3324 | clk_disable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3325 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3326 | return 0; |
| 3327 | } |
| 3328 | |
Doug Anderson | 68bda47 | 2014-11-19 14:51:32 -0800 | [diff] [blame] | 3329 | static void rockchip_irq_suspend(struct irq_data *d) |
| 3330 | { |
| 3331 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 3332 | struct rockchip_pin_bank *bank = gc->private; |
| 3333 | |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3334 | clk_enable(bank->clk); |
Doug Anderson | 5ae0c7a | 2015-01-26 08:24:03 -0800 | [diff] [blame] | 3335 | bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); |
| 3336 | irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3337 | clk_disable(bank->clk); |
Doug Anderson | 68bda47 | 2014-11-19 14:51:32 -0800 | [diff] [blame] | 3338 | } |
| 3339 | |
| 3340 | static void rockchip_irq_resume(struct irq_data *d) |
| 3341 | { |
| 3342 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 3343 | struct rockchip_pin_bank *bank = gc->private; |
| 3344 | |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3345 | clk_enable(bank->clk); |
Doug Anderson | 5ae0c7a | 2015-01-26 08:24:03 -0800 | [diff] [blame] | 3346 | irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3347 | clk_disable(bank->clk); |
| 3348 | } |
| 3349 | |
Jeffy Chen | d468289 | 2017-03-02 13:56:52 +0800 | [diff] [blame] | 3350 | static void rockchip_irq_enable(struct irq_data *d) |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3351 | { |
| 3352 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 3353 | struct rockchip_pin_bank *bank = gc->private; |
| 3354 | |
| 3355 | clk_enable(bank->clk); |
| 3356 | irq_gc_mask_clr_bit(d); |
| 3357 | } |
| 3358 | |
Jeffy Chen | d468289 | 2017-03-02 13:56:52 +0800 | [diff] [blame] | 3359 | static void rockchip_irq_disable(struct irq_data *d) |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3360 | { |
| 3361 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
| 3362 | struct rockchip_pin_bank *bank = gc->private; |
| 3363 | |
| 3364 | irq_gc_mask_set_bit(d); |
| 3365 | clk_disable(bank->clk); |
Doug Anderson | f2dd028 | 2014-11-19 14:51:33 -0800 | [diff] [blame] | 3366 | } |
| 3367 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3368 | static int rockchip_interrupts_register(struct platform_device *pdev, |
| 3369 | struct rockchip_pinctrl *info) |
| 3370 | { |
| 3371 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
| 3372 | struct rockchip_pin_bank *bank = ctrl->pin_banks; |
| 3373 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
| 3374 | struct irq_chip_generic *gc; |
| 3375 | int ret; |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3376 | int i, j; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3377 | |
| 3378 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
| 3379 | if (!bank->valid) { |
| 3380 | dev_warn(&pdev->dev, "bank %s is not valid\n", |
| 3381 | bank->name); |
| 3382 | continue; |
| 3383 | } |
| 3384 | |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3385 | ret = clk_enable(bank->clk); |
| 3386 | if (ret) { |
| 3387 | dev_err(&pdev->dev, "failed to enable clock for bank %s\n", |
| 3388 | bank->name); |
| 3389 | continue; |
| 3390 | } |
| 3391 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3392 | bank->domain = irq_domain_add_linear(bank->of_node, 32, |
| 3393 | &irq_generic_chip_ops, NULL); |
| 3394 | if (!bank->domain) { |
| 3395 | dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", |
| 3396 | bank->name); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3397 | clk_disable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3398 | continue; |
| 3399 | } |
| 3400 | |
| 3401 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, |
| 3402 | "rockchip_gpio_irq", handle_level_irq, |
| 3403 | clr, 0, IRQ_GC_INIT_MASK_CACHE); |
| 3404 | if (ret) { |
| 3405 | dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", |
| 3406 | bank->name); |
| 3407 | irq_domain_remove(bank->domain); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3408 | clk_disable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3409 | continue; |
| 3410 | } |
| 3411 | |
Doug Anderson | 5ae0c7a | 2015-01-26 08:24:03 -0800 | [diff] [blame] | 3412 | /* |
| 3413 | * Linux assumes that all interrupts start out disabled/masked. |
| 3414 | * Our driver only uses the concept of masked and always keeps |
| 3415 | * things enabled, so for us that's all masked and all enabled. |
| 3416 | */ |
| 3417 | writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); |
| 3418 | writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); |
| 3419 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3420 | gc = irq_get_domain_generic_chip(bank->domain, 0); |
| 3421 | gc->reg_base = bank->reg_base; |
| 3422 | gc->private = bank; |
Doug Anderson | f2dd028 | 2014-11-19 14:51:33 -0800 | [diff] [blame] | 3423 | gc->chip_types[0].regs.mask = GPIO_INTMASK; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3424 | gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; |
| 3425 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; |
Jeffy Chen | d468289 | 2017-03-02 13:56:52 +0800 | [diff] [blame] | 3426 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; |
| 3427 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; |
| 3428 | gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; |
| 3429 | gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3430 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; |
Doug Anderson | 68bda47 | 2014-11-19 14:51:32 -0800 | [diff] [blame] | 3431 | gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; |
| 3432 | gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3433 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; |
Doug Anderson | 876d716 | 2014-10-21 10:47:32 -0700 | [diff] [blame] | 3434 | gc->wake_enabled = IRQ_MSK(bank->nr_pins); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3435 | |
Thomas Gleixner | 03051bc | 2015-06-21 21:11:06 +0200 | [diff] [blame] | 3436 | irq_set_chained_handler_and_data(bank->irq, |
| 3437 | rockchip_irq_demux, bank); |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3438 | |
| 3439 | /* map the gpio irqs here, when the clock is still running */ |
| 3440 | for (j = 0 ; j < 32 ; j++) |
| 3441 | irq_create_mapping(bank->domain, j); |
| 3442 | |
| 3443 | clk_disable(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3444 | } |
| 3445 | |
| 3446 | return 0; |
| 3447 | } |
| 3448 | |
| 3449 | static int rockchip_gpiolib_register(struct platform_device *pdev, |
| 3450 | struct rockchip_pinctrl *info) |
| 3451 | { |
| 3452 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
| 3453 | struct rockchip_pin_bank *bank = ctrl->pin_banks; |
| 3454 | struct gpio_chip *gc; |
| 3455 | int ret; |
| 3456 | int i; |
| 3457 | |
| 3458 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
| 3459 | if (!bank->valid) { |
| 3460 | dev_warn(&pdev->dev, "bank %s is not valid\n", |
| 3461 | bank->name); |
| 3462 | continue; |
| 3463 | } |
| 3464 | |
| 3465 | bank->gpio_chip = rockchip_gpiolib_chip; |
| 3466 | |
| 3467 | gc = &bank->gpio_chip; |
| 3468 | gc->base = bank->pin_base; |
| 3469 | gc->ngpio = bank->nr_pins; |
Linus Walleij | 58383c78 | 2015-11-04 09:56:26 +0100 | [diff] [blame] | 3470 | gc->parent = &pdev->dev; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3471 | gc->of_node = bank->of_node; |
| 3472 | gc->label = bank->name; |
| 3473 | |
Linus Walleij | 03bf81f | 2015-12-08 09:39:13 +0100 | [diff] [blame] | 3474 | ret = gpiochip_add_data(gc, bank); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3475 | if (ret) { |
| 3476 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", |
| 3477 | gc->label, ret); |
| 3478 | goto fail; |
| 3479 | } |
| 3480 | } |
| 3481 | |
| 3482 | rockchip_interrupts_register(pdev, info); |
| 3483 | |
| 3484 | return 0; |
| 3485 | |
| 3486 | fail: |
| 3487 | for (--i, --bank; i >= 0; --i, --bank) { |
| 3488 | if (!bank->valid) |
| 3489 | continue; |
abdoulaye berthe | b4e7c55 | 2014-07-12 22:30:13 +0200 | [diff] [blame] | 3490 | gpiochip_remove(&bank->gpio_chip); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3491 | } |
| 3492 | return ret; |
| 3493 | } |
| 3494 | |
| 3495 | static int rockchip_gpiolib_unregister(struct platform_device *pdev, |
| 3496 | struct rockchip_pinctrl *info) |
| 3497 | { |
| 3498 | struct rockchip_pin_ctrl *ctrl = info->ctrl; |
| 3499 | struct rockchip_pin_bank *bank = ctrl->pin_banks; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3500 | int i; |
| 3501 | |
abdoulaye berthe | b4e7c55 | 2014-07-12 22:30:13 +0200 | [diff] [blame] | 3502 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3503 | if (!bank->valid) |
| 3504 | continue; |
abdoulaye berthe | b4e7c55 | 2014-07-12 22:30:13 +0200 | [diff] [blame] | 3505 | gpiochip_remove(&bank->gpio_chip); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3506 | } |
| 3507 | |
abdoulaye berthe | b4e7c55 | 2014-07-12 22:30:13 +0200 | [diff] [blame] | 3508 | return 0; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3509 | } |
| 3510 | |
| 3511 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, |
Heiko Stübner | 622f323 | 2014-05-05 13:58:46 +0200 | [diff] [blame] | 3512 | struct rockchip_pinctrl *info) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3513 | { |
| 3514 | struct resource res; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 3515 | void __iomem *base; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3516 | |
| 3517 | if (of_address_to_resource(bank->of_node, 0, &res)) { |
Heiko Stübner | 622f323 | 2014-05-05 13:58:46 +0200 | [diff] [blame] | 3518 | dev_err(info->dev, "cannot find IO resource for bank\n"); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3519 | return -ENOENT; |
| 3520 | } |
| 3521 | |
Heiko Stübner | 622f323 | 2014-05-05 13:58:46 +0200 | [diff] [blame] | 3522 | bank->reg_base = devm_ioremap_resource(info->dev, &res); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3523 | if (IS_ERR(bank->reg_base)) |
| 3524 | return PTR_ERR(bank->reg_base); |
| 3525 | |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 3526 | /* |
| 3527 | * special case, where parts of the pull setting-registers are |
| 3528 | * part of the PMU register space |
| 3529 | */ |
| 3530 | if (of_device_is_compatible(bank->of_node, |
| 3531 | "rockchip,rk3188-gpio-bank0")) { |
Heiko Stübner | a658efa | 2014-05-05 13:59:30 +0200 | [diff] [blame] | 3532 | struct device_node *node; |
Heiko Stübner | bfc7a42 | 2014-05-05 13:58:00 +0200 | [diff] [blame] | 3533 | |
Heiko Stübner | a658efa | 2014-05-05 13:59:30 +0200 | [diff] [blame] | 3534 | node = of_parse_phandle(bank->of_node->parent, |
| 3535 | "rockchip,pmu", 0); |
| 3536 | if (!node) { |
| 3537 | if (of_address_to_resource(bank->of_node, 1, &res)) { |
| 3538 | dev_err(info->dev, "cannot find IO resource for bank\n"); |
| 3539 | return -ENOENT; |
| 3540 | } |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 3541 | |
Heiko Stübner | a658efa | 2014-05-05 13:59:30 +0200 | [diff] [blame] | 3542 | base = devm_ioremap_resource(info->dev, &res); |
| 3543 | if (IS_ERR(base)) |
| 3544 | return PTR_ERR(base); |
| 3545 | rockchip_regmap_config.max_register = |
| 3546 | resource_size(&res) - 4; |
| 3547 | rockchip_regmap_config.name = |
| 3548 | "rockchip,rk3188-gpio-bank0-pull"; |
| 3549 | bank->regmap_pull = devm_regmap_init_mmio(info->dev, |
| 3550 | base, |
| 3551 | &rockchip_regmap_config); |
| 3552 | } |
Wen Yang | 3c89c70 | 2019-04-15 14:24:02 +0800 | [diff] [blame] | 3553 | of_node_put(node); |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 3554 | } |
Heiko Stübner | 65fca61 | 2013-10-16 01:07:49 +0200 | [diff] [blame] | 3555 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3556 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); |
| 3557 | |
| 3558 | bank->clk = of_clk_get(bank->of_node, 0); |
| 3559 | if (IS_ERR(bank->clk)) |
| 3560 | return PTR_ERR(bank->clk); |
| 3561 | |
Lin Huang | 07a06ae | 2015-08-11 18:12:04 +0800 | [diff] [blame] | 3562 | return clk_prepare(bank->clk); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3563 | } |
| 3564 | |
| 3565 | static const struct of_device_id rockchip_pinctrl_dt_match[]; |
| 3566 | |
| 3567 | /* retrieve the soc specific data */ |
| 3568 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( |
| 3569 | struct rockchip_pinctrl *d, |
| 3570 | struct platform_device *pdev) |
| 3571 | { |
| 3572 | const struct of_device_id *match; |
| 3573 | struct device_node *node = pdev->dev.of_node; |
| 3574 | struct device_node *np; |
| 3575 | struct rockchip_pin_ctrl *ctrl; |
| 3576 | struct rockchip_pin_bank *bank; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3577 | int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3578 | |
| 3579 | match = of_match_node(rockchip_pinctrl_dt_match, node); |
| 3580 | ctrl = (struct rockchip_pin_ctrl *)match->data; |
| 3581 | |
| 3582 | for_each_child_of_node(node, np) { |
| 3583 | if (!of_find_property(np, "gpio-controller", NULL)) |
| 3584 | continue; |
| 3585 | |
| 3586 | bank = ctrl->pin_banks; |
| 3587 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
| 3588 | if (!strcmp(bank->name, np->name)) { |
| 3589 | bank->of_node = np; |
| 3590 | |
Heiko Stübner | 622f323 | 2014-05-05 13:58:46 +0200 | [diff] [blame] | 3591 | if (!rockchip_get_bank_data(bank, d)) |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3592 | bank->valid = true; |
| 3593 | |
| 3594 | break; |
| 3595 | } |
| 3596 | } |
| 3597 | } |
| 3598 | |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3599 | grf_offs = ctrl->grf_mux_offset; |
| 3600 | pmu_offs = ctrl->pmu_mux_offset; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3601 | drv_pmu_offs = ctrl->pmu_drv_offset; |
| 3602 | drv_grf_offs = ctrl->grf_drv_offset; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3603 | bank = ctrl->pin_banks; |
| 3604 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3605 | int bank_pins = 0; |
| 3606 | |
John Keeping | 70b7aa7 | 2017-03-23 10:59:29 +0000 | [diff] [blame] | 3607 | raw_spin_lock_init(&bank->slock); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3608 | bank->drvdata = d; |
| 3609 | bank->pin_base = ctrl->nr_pins; |
| 3610 | ctrl->nr_pins += bank->nr_pins; |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3611 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3612 | /* calculate iomux and drv offsets */ |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3613 | for (j = 0; j < 4; j++) { |
| 3614 | struct rockchip_iomux *iom = &bank->iomux[j]; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3615 | struct rockchip_drv *drv = &bank->drv[j]; |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 3616 | int inc; |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3617 | |
| 3618 | if (bank_pins >= bank->nr_pins) |
| 3619 | break; |
| 3620 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3621 | /* preset iomux offset value, set new start value */ |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3622 | if (iom->offset >= 0) { |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3623 | if (iom->type & IOMUX_SOURCE_PMU) |
| 3624 | pmu_offs = iom->offset; |
| 3625 | else |
| 3626 | grf_offs = iom->offset; |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3627 | } else { /* set current iomux offset */ |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3628 | iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? |
| 3629 | pmu_offs : grf_offs; |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3630 | } |
| 3631 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3632 | /* preset drv offset value, set new start value */ |
| 3633 | if (drv->offset >= 0) { |
| 3634 | if (iom->type & IOMUX_SOURCE_PMU) |
| 3635 | drv_pmu_offs = drv->offset; |
| 3636 | else |
| 3637 | drv_grf_offs = drv->offset; |
| 3638 | } else { /* set current drv offset */ |
| 3639 | drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? |
| 3640 | drv_pmu_offs : drv_grf_offs; |
| 3641 | } |
| 3642 | |
| 3643 | dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", |
| 3644 | i, j, iom->offset, drv->offset); |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3645 | |
| 3646 | /* |
| 3647 | * Increase offset according to iomux width. |
Heiko Stübner | 03716e1 | 2014-06-16 01:36:57 +0200 | [diff] [blame] | 3648 | * 4bit iomux'es are spread over two registers. |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3649 | */ |
david.wu | 8b6c6f9 | 2017-02-10 18:23:47 +0800 | [diff] [blame] | 3650 | inc = (iom->type & (IOMUX_WIDTH_4BIT | |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 3651 | IOMUX_WIDTH_3BIT | |
| 3652 | IOMUX_WIDTH_2BIT)) ? 8 : 4; |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3653 | if (iom->type & IOMUX_SOURCE_PMU) |
| 3654 | pmu_offs += inc; |
| 3655 | else |
| 3656 | grf_offs += inc; |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3657 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 3658 | /* |
| 3659 | * Increase offset according to drv width. |
| 3660 | * 3bit drive-strenth'es are spread over two registers. |
| 3661 | */ |
| 3662 | if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || |
| 3663 | (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) |
| 3664 | inc = 8; |
| 3665 | else |
| 3666 | inc = 4; |
| 3667 | |
| 3668 | if (iom->type & IOMUX_SOURCE_PMU) |
| 3669 | drv_pmu_offs += inc; |
| 3670 | else |
| 3671 | drv_grf_offs += inc; |
| 3672 | |
Heiko Stübner | 6bc0d12 | 2014-06-16 01:36:33 +0200 | [diff] [blame] | 3673 | bank_pins += 8; |
| 3674 | } |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 3675 | |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 3676 | /* calculate the per-bank recalced_mask */ |
| 3677 | for (j = 0; j < ctrl->niomux_recalced; j++) { |
| 3678 | int pin = 0; |
| 3679 | |
| 3680 | if (ctrl->iomux_recalced[j].num == bank->bank_num) { |
| 3681 | pin = ctrl->iomux_recalced[j].pin; |
| 3682 | bank->recalced_mask |= BIT(pin); |
| 3683 | } |
| 3684 | } |
| 3685 | |
David Wu | bd35b9b | 2017-05-26 15:20:20 +0800 | [diff] [blame] | 3686 | /* calculate the per-bank route_mask */ |
| 3687 | for (j = 0; j < ctrl->niomux_routes; j++) { |
| 3688 | int pin = 0; |
| 3689 | |
| 3690 | if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { |
| 3691 | pin = ctrl->iomux_routes[j].pin; |
| 3692 | bank->route_mask |= BIT(pin); |
| 3693 | } |
| 3694 | } |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3695 | } |
| 3696 | |
| 3697 | return ctrl; |
| 3698 | } |
| 3699 | |
Chris Zhong | 8dca933 | 2014-10-29 19:52:00 +0800 | [diff] [blame] | 3700 | #define RK3288_GRF_GPIO6C_IOMUX 0x64 |
| 3701 | #define GPIO6C6_SEL_WRITE_ENABLE BIT(28) |
| 3702 | |
| 3703 | static u32 rk3288_grf_gpio6c_iomux; |
| 3704 | |
Chris Zhong | 9198f50 | 2014-10-29 19:51:59 +0800 | [diff] [blame] | 3705 | static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev) |
| 3706 | { |
| 3707 | struct rockchip_pinctrl *info = dev_get_drvdata(dev); |
Chris Zhong | 8dca933 | 2014-10-29 19:52:00 +0800 | [diff] [blame] | 3708 | int ret = pinctrl_force_sleep(info->pctl_dev); |
Chris Zhong | 9198f50 | 2014-10-29 19:51:59 +0800 | [diff] [blame] | 3709 | |
Chris Zhong | 8dca933 | 2014-10-29 19:52:00 +0800 | [diff] [blame] | 3710 | if (ret) |
| 3711 | return ret; |
| 3712 | |
| 3713 | /* |
| 3714 | * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save |
| 3715 | * the setting here, and restore it at resume. |
| 3716 | */ |
| 3717 | if (info->ctrl->type == RK3288) { |
| 3718 | ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, |
| 3719 | &rk3288_grf_gpio6c_iomux); |
| 3720 | if (ret) { |
| 3721 | pinctrl_force_default(info->pctl_dev); |
| 3722 | return ret; |
| 3723 | } |
| 3724 | } |
| 3725 | |
| 3726 | return 0; |
Chris Zhong | 9198f50 | 2014-10-29 19:51:59 +0800 | [diff] [blame] | 3727 | } |
| 3728 | |
| 3729 | static int __maybe_unused rockchip_pinctrl_resume(struct device *dev) |
| 3730 | { |
| 3731 | struct rockchip_pinctrl *info = dev_get_drvdata(dev); |
Chris Zhong | 8dca933 | 2014-10-29 19:52:00 +0800 | [diff] [blame] | 3732 | int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, |
| 3733 | rk3288_grf_gpio6c_iomux | |
| 3734 | GPIO6C6_SEL_WRITE_ENABLE); |
| 3735 | |
| 3736 | if (ret) |
| 3737 | return ret; |
Chris Zhong | 9198f50 | 2014-10-29 19:51:59 +0800 | [diff] [blame] | 3738 | |
| 3739 | return pinctrl_force_default(info->pctl_dev); |
| 3740 | } |
| 3741 | |
| 3742 | static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend, |
| 3743 | rockchip_pinctrl_resume); |
| 3744 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3745 | static int rockchip_pinctrl_probe(struct platform_device *pdev) |
| 3746 | { |
| 3747 | struct rockchip_pinctrl *info; |
| 3748 | struct device *dev = &pdev->dev; |
| 3749 | struct rockchip_pin_ctrl *ctrl; |
Heiko Stübner | 14dee86 | 2014-05-05 13:59:09 +0200 | [diff] [blame] | 3750 | struct device_node *np = pdev->dev.of_node, *node; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3751 | struct resource *res; |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 3752 | void __iomem *base; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3753 | int ret; |
| 3754 | |
| 3755 | if (!dev->of_node) { |
| 3756 | dev_err(dev, "device tree node not found\n"); |
| 3757 | return -ENODEV; |
| 3758 | } |
| 3759 | |
Markus Elfring | 283b7ac | 2017-12-23 22:07:30 +0100 | [diff] [blame] | 3760 | info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3761 | if (!info) |
| 3762 | return -ENOMEM; |
| 3763 | |
Heiko Stübner | 622f323 | 2014-05-05 13:58:46 +0200 | [diff] [blame] | 3764 | info->dev = dev; |
| 3765 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3766 | ctrl = rockchip_pinctrl_get_soc_data(info, pdev); |
| 3767 | if (!ctrl) { |
| 3768 | dev_err(dev, "driver data not available\n"); |
| 3769 | return -EINVAL; |
| 3770 | } |
| 3771 | info->ctrl = ctrl; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3772 | |
Heiko Stübner | 1e747e5 | 2014-05-05 13:59:51 +0200 | [diff] [blame] | 3773 | node = of_parse_phandle(np, "rockchip,grf", 0); |
| 3774 | if (node) { |
| 3775 | info->regmap_base = syscon_node_to_regmap(node); |
| 3776 | if (IS_ERR(info->regmap_base)) |
| 3777 | return PTR_ERR(info->regmap_base); |
| 3778 | } else { |
| 3779 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Heiko Stübner | 751a99a | 2014-05-05 13:58:20 +0200 | [diff] [blame] | 3780 | base = devm_ioremap_resource(&pdev->dev, res); |
| 3781 | if (IS_ERR(base)) |
| 3782 | return PTR_ERR(base); |
| 3783 | |
| 3784 | rockchip_regmap_config.max_register = resource_size(res) - 4; |
Heiko Stübner | 1e747e5 | 2014-05-05 13:59:51 +0200 | [diff] [blame] | 3785 | rockchip_regmap_config.name = "rockchip,pinctrl"; |
| 3786 | info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, |
| 3787 | &rockchip_regmap_config); |
| 3788 | |
| 3789 | /* to check for the old dt-bindings */ |
| 3790 | info->reg_size = resource_size(res); |
| 3791 | |
| 3792 | /* Honor the old binding, with pull registers as 2nd resource */ |
| 3793 | if (ctrl->type == RK3188 && info->reg_size < 0x200) { |
| 3794 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 3795 | base = devm_ioremap_resource(&pdev->dev, res); |
| 3796 | if (IS_ERR(base)) |
| 3797 | return PTR_ERR(base); |
| 3798 | |
| 3799 | rockchip_regmap_config.max_register = |
| 3800 | resource_size(res) - 4; |
| 3801 | rockchip_regmap_config.name = "rockchip,pinctrl-pull"; |
| 3802 | info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, |
| 3803 | base, |
| 3804 | &rockchip_regmap_config); |
| 3805 | } |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 3806 | } |
| 3807 | |
Heiko Stübner | 14dee86 | 2014-05-05 13:59:09 +0200 | [diff] [blame] | 3808 | /* try to find the optional reference to the pmu syscon */ |
| 3809 | node = of_parse_phandle(np, "rockchip,pmu", 0); |
| 3810 | if (node) { |
| 3811 | info->regmap_pmu = syscon_node_to_regmap(node); |
| 3812 | if (IS_ERR(info->regmap_pmu)) |
| 3813 | return PTR_ERR(info->regmap_pmu); |
| 3814 | } |
| 3815 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3816 | ret = rockchip_gpiolib_register(pdev, info); |
| 3817 | if (ret) |
| 3818 | return ret; |
| 3819 | |
| 3820 | ret = rockchip_pinctrl_register(pdev, info); |
| 3821 | if (ret) { |
| 3822 | rockchip_gpiolib_unregister(pdev, info); |
| 3823 | return ret; |
| 3824 | } |
| 3825 | |
| 3826 | platform_set_drvdata(pdev, info); |
| 3827 | |
| 3828 | return 0; |
| 3829 | } |
| 3830 | |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 3831 | static struct rockchip_pin_bank px30_pin_banks[] = { |
| 3832 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, |
| 3833 | IOMUX_SOURCE_PMU, |
| 3834 | IOMUX_SOURCE_PMU, |
| 3835 | IOMUX_SOURCE_PMU |
| 3836 | ), |
| 3837 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, |
| 3838 | IOMUX_WIDTH_4BIT, |
| 3839 | IOMUX_WIDTH_4BIT, |
| 3840 | IOMUX_WIDTH_4BIT |
| 3841 | ), |
| 3842 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, |
| 3843 | IOMUX_WIDTH_4BIT, |
| 3844 | IOMUX_WIDTH_4BIT, |
| 3845 | IOMUX_WIDTH_4BIT |
| 3846 | ), |
| 3847 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, |
| 3848 | IOMUX_WIDTH_4BIT, |
| 3849 | IOMUX_WIDTH_4BIT, |
| 3850 | IOMUX_WIDTH_4BIT |
| 3851 | ), |
| 3852 | }; |
| 3853 | |
| 3854 | static struct rockchip_pin_ctrl px30_pin_ctrl = { |
| 3855 | .pin_banks = px30_pin_banks, |
| 3856 | .nr_banks = ARRAY_SIZE(px30_pin_banks), |
| 3857 | .label = "PX30-GPIO", |
| 3858 | .type = PX30, |
| 3859 | .grf_mux_offset = 0x0, |
| 3860 | .pmu_mux_offset = 0x0, |
| 3861 | .iomux_routes = px30_mux_route_data, |
| 3862 | .niomux_routes = ARRAY_SIZE(px30_mux_route_data), |
| 3863 | .pull_calc_reg = px30_calc_pull_reg_and_bit, |
| 3864 | .drv_calc_reg = px30_calc_drv_reg_and_bit, |
| 3865 | .schmitt_calc_reg = px30_calc_schmitt_reg_and_bit, |
| 3866 | }; |
| 3867 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 3868 | static struct rockchip_pin_bank rv1108_pin_banks[] = { |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 3869 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, |
| 3870 | IOMUX_SOURCE_PMU, |
| 3871 | IOMUX_SOURCE_PMU, |
| 3872 | IOMUX_SOURCE_PMU), |
| 3873 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), |
| 3874 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0), |
| 3875 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0), |
| 3876 | }; |
| 3877 | |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 3878 | static struct rockchip_pin_ctrl rv1108_pin_ctrl = { |
| 3879 | .pin_banks = rv1108_pin_banks, |
| 3880 | .nr_banks = ARRAY_SIZE(rv1108_pin_banks), |
| 3881 | .label = "RV1108-GPIO", |
| 3882 | .type = RV1108, |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 3883 | .grf_mux_offset = 0x10, |
| 3884 | .pmu_mux_offset = 0x0, |
David Wu | 12b8f01 | 2017-08-23 16:00:07 +0800 | [diff] [blame] | 3885 | .iomux_recalced = rv1108_mux_recalced_data, |
| 3886 | .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data), |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 3887 | .pull_calc_reg = rv1108_calc_pull_reg_and_bit, |
| 3888 | .drv_calc_reg = rv1108_calc_drv_reg_and_bit, |
Andy Yan | 5caff7e | 2017-07-31 18:10:22 +0800 | [diff] [blame] | 3889 | .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit, |
Andy Yan | 688daf2 | 2016-11-15 18:02:43 +0800 | [diff] [blame] | 3890 | }; |
| 3891 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3892 | static struct rockchip_pin_bank rk2928_pin_banks[] = { |
| 3893 | PIN_BANK(0, 32, "gpio0"), |
| 3894 | PIN_BANK(1, 32, "gpio1"), |
| 3895 | PIN_BANK(2, 32, "gpio2"), |
| 3896 | PIN_BANK(3, 32, "gpio3"), |
| 3897 | }; |
| 3898 | |
| 3899 | static struct rockchip_pin_ctrl rk2928_pin_ctrl = { |
| 3900 | .pin_banks = rk2928_pin_banks, |
| 3901 | .nr_banks = ARRAY_SIZE(rk2928_pin_banks), |
| 3902 | .label = "RK2928-GPIO", |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 3903 | .type = RK2928, |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3904 | .grf_mux_offset = 0xa8, |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 3905 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3906 | }; |
| 3907 | |
Xing Zheng | c5ce767 | 2015-08-28 13:46:47 +0800 | [diff] [blame] | 3908 | static struct rockchip_pin_bank rk3036_pin_banks[] = { |
| 3909 | PIN_BANK(0, 32, "gpio0"), |
| 3910 | PIN_BANK(1, 32, "gpio1"), |
| 3911 | PIN_BANK(2, 32, "gpio2"), |
| 3912 | }; |
| 3913 | |
| 3914 | static struct rockchip_pin_ctrl rk3036_pin_ctrl = { |
| 3915 | .pin_banks = rk3036_pin_banks, |
| 3916 | .nr_banks = ARRAY_SIZE(rk3036_pin_banks), |
| 3917 | .label = "RK3036-GPIO", |
| 3918 | .type = RK2928, |
| 3919 | .grf_mux_offset = 0xa8, |
| 3920 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
| 3921 | }; |
| 3922 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3923 | static struct rockchip_pin_bank rk3066a_pin_banks[] = { |
| 3924 | PIN_BANK(0, 32, "gpio0"), |
| 3925 | PIN_BANK(1, 32, "gpio1"), |
| 3926 | PIN_BANK(2, 32, "gpio2"), |
| 3927 | PIN_BANK(3, 32, "gpio3"), |
| 3928 | PIN_BANK(4, 32, "gpio4"), |
| 3929 | PIN_BANK(6, 16, "gpio6"), |
| 3930 | }; |
| 3931 | |
| 3932 | static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { |
| 3933 | .pin_banks = rk3066a_pin_banks, |
| 3934 | .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), |
| 3935 | .label = "RK3066a-GPIO", |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 3936 | .type = RK2928, |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3937 | .grf_mux_offset = 0xa8, |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 3938 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3939 | }; |
| 3940 | |
| 3941 | static struct rockchip_pin_bank rk3066b_pin_banks[] = { |
| 3942 | PIN_BANK(0, 32, "gpio0"), |
| 3943 | PIN_BANK(1, 32, "gpio1"), |
| 3944 | PIN_BANK(2, 32, "gpio2"), |
| 3945 | PIN_BANK(3, 32, "gpio3"), |
| 3946 | }; |
| 3947 | |
| 3948 | static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { |
| 3949 | .pin_banks = rk3066b_pin_banks, |
| 3950 | .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), |
| 3951 | .label = "RK3066b-GPIO", |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 3952 | .type = RK3066B, |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3953 | .grf_mux_offset = 0x60, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3954 | }; |
| 3955 | |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 3956 | static struct rockchip_pin_bank rk3128_pin_banks[] = { |
| 3957 | PIN_BANK(0, 32, "gpio0"), |
| 3958 | PIN_BANK(1, 32, "gpio1"), |
| 3959 | PIN_BANK(2, 32, "gpio2"), |
| 3960 | PIN_BANK(3, 32, "gpio3"), |
| 3961 | }; |
| 3962 | |
| 3963 | static struct rockchip_pin_ctrl rk3128_pin_ctrl = { |
| 3964 | .pin_banks = rk3128_pin_banks, |
| 3965 | .nr_banks = ARRAY_SIZE(rk3128_pin_banks), |
| 3966 | .label = "RK3128-GPIO", |
| 3967 | .type = RK3128, |
| 3968 | .grf_mux_offset = 0xa8, |
| 3969 | .iomux_recalced = rk3128_mux_recalced_data, |
| 3970 | .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data), |
| 3971 | .iomux_routes = rk3128_mux_route_data, |
| 3972 | .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data), |
| 3973 | .pull_calc_reg = rk3128_calc_pull_reg_and_bit, |
| 3974 | }; |
| 3975 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3976 | static struct rockchip_pin_bank rk3188_pin_banks[] = { |
Heiko Stübner | fc72c92 | 2014-06-16 01:36:05 +0200 | [diff] [blame] | 3977 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3978 | PIN_BANK(1, 32, "gpio1"), |
| 3979 | PIN_BANK(2, 32, "gpio2"), |
| 3980 | PIN_BANK(3, 32, "gpio3"), |
| 3981 | }; |
| 3982 | |
| 3983 | static struct rockchip_pin_ctrl rk3188_pin_ctrl = { |
| 3984 | .pin_banks = rk3188_pin_banks, |
| 3985 | .nr_banks = ARRAY_SIZE(rk3188_pin_banks), |
| 3986 | .label = "RK3188-GPIO", |
Heiko Stübner | a282926 | 2013-10-16 01:07:20 +0200 | [diff] [blame] | 3987 | .type = RK3188, |
Heiko Stübner | 95ec8ae | 2014-06-16 01:37:23 +0200 | [diff] [blame] | 3988 | .grf_mux_offset = 0x60, |
Heiko Stuebner | ada62b7 | 2018-11-11 22:00:47 +0100 | [diff] [blame] | 3989 | .iomux_routes = rk3188_mux_route_data, |
| 3990 | .niomux_routes = ARRAY_SIZE(rk3188_mux_route_data), |
Heiko Stübner | 6ca5274 | 2013-10-16 01:08:42 +0200 | [diff] [blame] | 3991 | .pull_calc_reg = rk3188_calc_pull_reg_and_bit, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 3992 | }; |
| 3993 | |
Jeffy Chen | fea0fe6 | 2015-12-09 17:04:06 +0800 | [diff] [blame] | 3994 | static struct rockchip_pin_bank rk3228_pin_banks[] = { |
| 3995 | PIN_BANK(0, 32, "gpio0"), |
| 3996 | PIN_BANK(1, 32, "gpio1"), |
| 3997 | PIN_BANK(2, 32, "gpio2"), |
| 3998 | PIN_BANK(3, 32, "gpio3"), |
| 3999 | }; |
| 4000 | |
| 4001 | static struct rockchip_pin_ctrl rk3228_pin_ctrl = { |
| 4002 | .pin_banks = rk3228_pin_banks, |
| 4003 | .nr_banks = ARRAY_SIZE(rk3228_pin_banks), |
| 4004 | .label = "RK3228-GPIO", |
| 4005 | .type = RK3288, |
| 4006 | .grf_mux_offset = 0x0, |
David Wu | d4970ee | 2017-05-26 15:20:21 +0800 | [diff] [blame] | 4007 | .iomux_routes = rk3228_mux_route_data, |
| 4008 | .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), |
Jeffy Chen | fea0fe6 | 2015-12-09 17:04:06 +0800 | [diff] [blame] | 4009 | .pull_calc_reg = rk3228_calc_pull_reg_and_bit, |
| 4010 | .drv_calc_reg = rk3228_calc_drv_reg_and_bit, |
| 4011 | }; |
| 4012 | |
Heiko Stübner | 304f077 | 2014-06-16 01:38:14 +0200 | [diff] [blame] | 4013 | static struct rockchip_pin_bank rk3288_pin_banks[] = { |
| 4014 | PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, |
| 4015 | IOMUX_SOURCE_PMU, |
| 4016 | IOMUX_SOURCE_PMU, |
| 4017 | IOMUX_UNROUTED |
| 4018 | ), |
| 4019 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, |
| 4020 | IOMUX_UNROUTED, |
| 4021 | IOMUX_UNROUTED, |
| 4022 | 0 |
| 4023 | ), |
| 4024 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), |
| 4025 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), |
| 4026 | PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, |
| 4027 | IOMUX_WIDTH_4BIT, |
| 4028 | 0, |
| 4029 | 0 |
| 4030 | ), |
| 4031 | PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, |
| 4032 | 0, |
| 4033 | 0, |
| 4034 | IOMUX_UNROUTED |
| 4035 | ), |
| 4036 | PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), |
| 4037 | PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, |
| 4038 | 0, |
| 4039 | IOMUX_WIDTH_4BIT, |
| 4040 | IOMUX_UNROUTED |
| 4041 | ), |
| 4042 | PIN_BANK(8, 16, "gpio8"), |
| 4043 | }; |
| 4044 | |
| 4045 | static struct rockchip_pin_ctrl rk3288_pin_ctrl = { |
| 4046 | .pin_banks = rk3288_pin_banks, |
| 4047 | .nr_banks = ARRAY_SIZE(rk3288_pin_banks), |
| 4048 | .label = "RK3288-GPIO", |
Heiko Stübner | 66d750e | 2014-07-20 01:49:17 +0200 | [diff] [blame] | 4049 | .type = RK3288, |
Heiko Stübner | 304f077 | 2014-06-16 01:38:14 +0200 | [diff] [blame] | 4050 | .grf_mux_offset = 0x0, |
| 4051 | .pmu_mux_offset = 0x84, |
Heiko Stuebner | 4e96fd3 | 2017-10-21 10:53:10 +0200 | [diff] [blame] | 4052 | .iomux_routes = rk3288_mux_route_data, |
| 4053 | .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data), |
Heiko Stübner | 304f077 | 2014-06-16 01:38:14 +0200 | [diff] [blame] | 4054 | .pull_calc_reg = rk3288_calc_pull_reg_and_bit, |
Heiko Stübner | ef17f69 | 2015-06-12 23:50:11 +0200 | [diff] [blame] | 4055 | .drv_calc_reg = rk3288_calc_drv_reg_and_bit, |
Heiko Stübner | 304f077 | 2014-06-16 01:38:14 +0200 | [diff] [blame] | 4056 | }; |
| 4057 | |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 4058 | static struct rockchip_pin_bank rk3308_pin_banks[] = { |
| 4059 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_2BIT, |
| 4060 | IOMUX_WIDTH_2BIT, |
| 4061 | IOMUX_WIDTH_2BIT, |
| 4062 | IOMUX_WIDTH_2BIT), |
| 4063 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_2BIT, |
| 4064 | IOMUX_WIDTH_2BIT, |
| 4065 | IOMUX_WIDTH_2BIT, |
| 4066 | IOMUX_WIDTH_2BIT), |
| 4067 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_2BIT, |
| 4068 | IOMUX_WIDTH_2BIT, |
| 4069 | IOMUX_WIDTH_2BIT, |
| 4070 | IOMUX_WIDTH_2BIT), |
| 4071 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_2BIT, |
| 4072 | IOMUX_WIDTH_2BIT, |
| 4073 | IOMUX_WIDTH_2BIT, |
| 4074 | IOMUX_WIDTH_2BIT), |
| 4075 | PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_2BIT, |
| 4076 | IOMUX_WIDTH_2BIT, |
| 4077 | IOMUX_WIDTH_2BIT, |
| 4078 | IOMUX_WIDTH_2BIT), |
| 4079 | }; |
| 4080 | |
| 4081 | static struct rockchip_pin_ctrl rk3308_pin_ctrl = { |
| 4082 | .pin_banks = rk3308_pin_banks, |
| 4083 | .nr_banks = ARRAY_SIZE(rk3308_pin_banks), |
| 4084 | .label = "RK3308-GPIO", |
| 4085 | .type = RK3308, |
| 4086 | .grf_mux_offset = 0x0, |
| 4087 | .iomux_recalced = rk3308_mux_recalced_data, |
| 4088 | .niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data), |
| 4089 | .iomux_routes = rk3308_mux_route_data, |
| 4090 | .niomux_routes = ARRAY_SIZE(rk3308_mux_route_data), |
| 4091 | .pull_calc_reg = rk3308_calc_pull_reg_and_bit, |
| 4092 | .drv_calc_reg = rk3308_calc_drv_reg_and_bit, |
| 4093 | .schmitt_calc_reg = rk3308_calc_schmitt_reg_and_bit, |
| 4094 | }; |
| 4095 | |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 4096 | static struct rockchip_pin_bank rk3328_pin_banks[] = { |
| 4097 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), |
| 4098 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), |
| 4099 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 4100 | IOMUX_WIDTH_3BIT, |
| 4101 | IOMUX_WIDTH_3BIT, |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 4102 | 0), |
| 4103 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", |
| 4104 | IOMUX_WIDTH_3BIT, |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 4105 | IOMUX_WIDTH_3BIT, |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 4106 | 0, |
| 4107 | 0), |
| 4108 | }; |
| 4109 | |
| 4110 | static struct rockchip_pin_ctrl rk3328_pin_ctrl = { |
| 4111 | .pin_banks = rk3328_pin_banks, |
| 4112 | .nr_banks = ARRAY_SIZE(rk3328_pin_banks), |
| 4113 | .label = "RK3328-GPIO", |
| 4114 | .type = RK3288, |
| 4115 | .grf_mux_offset = 0x0, |
David Wu | c04c3fa | 2017-07-21 14:27:14 +0800 | [diff] [blame] | 4116 | .iomux_recalced = rk3328_mux_recalced_data, |
| 4117 | .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), |
David Wu | cedc964 | 2017-05-26 15:20:22 +0800 | [diff] [blame] | 4118 | .iomux_routes = rk3328_mux_route_data, |
| 4119 | .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 4120 | .pull_calc_reg = rk3228_calc_pull_reg_and_bit, |
| 4121 | .drv_calc_reg = rk3228_calc_drv_reg_and_bit, |
david.wu | 728d3f5 | 2017-03-02 15:11:24 +0800 | [diff] [blame] | 4122 | .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit, |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 4123 | }; |
| 4124 | |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 4125 | static struct rockchip_pin_bank rk3368_pin_banks[] = { |
| 4126 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, |
| 4127 | IOMUX_SOURCE_PMU, |
| 4128 | IOMUX_SOURCE_PMU, |
| 4129 | IOMUX_SOURCE_PMU |
| 4130 | ), |
| 4131 | PIN_BANK(1, 32, "gpio1"), |
| 4132 | PIN_BANK(2, 32, "gpio2"), |
| 4133 | PIN_BANK(3, 32, "gpio3"), |
| 4134 | }; |
| 4135 | |
| 4136 | static struct rockchip_pin_ctrl rk3368_pin_ctrl = { |
| 4137 | .pin_banks = rk3368_pin_banks, |
| 4138 | .nr_banks = ARRAY_SIZE(rk3368_pin_banks), |
| 4139 | .label = "RK3368-GPIO", |
| 4140 | .type = RK3368, |
| 4141 | .grf_mux_offset = 0x0, |
| 4142 | .pmu_mux_offset = 0x0, |
| 4143 | .pull_calc_reg = rk3368_calc_pull_reg_and_bit, |
| 4144 | .drv_calc_reg = rk3368_calc_drv_reg_and_bit, |
| 4145 | }; |
| 4146 | |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 4147 | static struct rockchip_pin_bank rk3399_pin_banks[] = { |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 4148 | PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0", |
| 4149 | IOMUX_SOURCE_PMU, |
| 4150 | IOMUX_SOURCE_PMU, |
| 4151 | IOMUX_SOURCE_PMU, |
| 4152 | IOMUX_SOURCE_PMU, |
| 4153 | DRV_TYPE_IO_1V8_ONLY, |
| 4154 | DRV_TYPE_IO_1V8_ONLY, |
| 4155 | DRV_TYPE_IO_DEFAULT, |
| 4156 | DRV_TYPE_IO_DEFAULT, |
David Wu | c437f65 | 2017-09-30 20:13:20 +0800 | [diff] [blame] | 4157 | 0x80, |
| 4158 | 0x88, |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 4159 | -1, |
| 4160 | -1, |
| 4161 | PULL_TYPE_IO_1V8_ONLY, |
| 4162 | PULL_TYPE_IO_1V8_ONLY, |
| 4163 | PULL_TYPE_IO_DEFAULT, |
| 4164 | PULL_TYPE_IO_DEFAULT |
| 4165 | ), |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 4166 | PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU, |
| 4167 | IOMUX_SOURCE_PMU, |
| 4168 | IOMUX_SOURCE_PMU, |
| 4169 | IOMUX_SOURCE_PMU, |
| 4170 | DRV_TYPE_IO_1V8_OR_3V0, |
| 4171 | DRV_TYPE_IO_1V8_OR_3V0, |
| 4172 | DRV_TYPE_IO_1V8_OR_3V0, |
| 4173 | DRV_TYPE_IO_1V8_OR_3V0, |
David Wu | c437f65 | 2017-09-30 20:13:20 +0800 | [diff] [blame] | 4174 | 0xa0, |
| 4175 | 0xa8, |
| 4176 | 0xb0, |
| 4177 | 0xb8 |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 4178 | ), |
David Wu | 3ba6767 | 2016-05-11 11:39:28 +0800 | [diff] [blame] | 4179 | PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, |
| 4180 | DRV_TYPE_IO_1V8_OR_3V0, |
| 4181 | DRV_TYPE_IO_1V8_ONLY, |
| 4182 | DRV_TYPE_IO_1V8_ONLY, |
| 4183 | PULL_TYPE_IO_DEFAULT, |
| 4184 | PULL_TYPE_IO_DEFAULT, |
| 4185 | PULL_TYPE_IO_1V8_ONLY, |
| 4186 | PULL_TYPE_IO_1V8_ONLY |
| 4187 | ), |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 4188 | PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY, |
| 4189 | DRV_TYPE_IO_3V3_ONLY, |
| 4190 | DRV_TYPE_IO_3V3_ONLY, |
| 4191 | DRV_TYPE_IO_1V8_OR_3V0 |
| 4192 | ), |
| 4193 | PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0, |
| 4194 | DRV_TYPE_IO_1V8_3V0_AUTO, |
| 4195 | DRV_TYPE_IO_1V8_OR_3V0, |
| 4196 | DRV_TYPE_IO_1V8_OR_3V0 |
| 4197 | ), |
| 4198 | }; |
| 4199 | |
| 4200 | static struct rockchip_pin_ctrl rk3399_pin_ctrl = { |
| 4201 | .pin_banks = rk3399_pin_banks, |
| 4202 | .nr_banks = ARRAY_SIZE(rk3399_pin_banks), |
| 4203 | .label = "RK3399-GPIO", |
| 4204 | .type = RK3399, |
| 4205 | .grf_mux_offset = 0xe000, |
| 4206 | .pmu_mux_offset = 0x0, |
| 4207 | .grf_drv_offset = 0xe100, |
| 4208 | .pmu_drv_offset = 0x80, |
David Wu | accc1ce | 2017-05-26 15:20:23 +0800 | [diff] [blame] | 4209 | .iomux_routes = rk3399_mux_route_data, |
| 4210 | .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 4211 | .pull_calc_reg = rk3399_calc_pull_reg_and_bit, |
| 4212 | .drv_calc_reg = rk3399_calc_drv_reg_and_bit, |
| 4213 | }; |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 4214 | |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4215 | static const struct of_device_id rockchip_pinctrl_dt_match[] = { |
David Wu | 87065ca | 2018-05-14 19:59:51 +0800 | [diff] [blame] | 4216 | { .compatible = "rockchip,px30-pinctrl", |
| 4217 | .data = &px30_pin_ctrl }, |
Andy Yan | b9c6dca | 2017-03-17 18:18:36 +0100 | [diff] [blame] | 4218 | { .compatible = "rockchip,rv1108-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4219 | .data = &rv1108_pin_ctrl }, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4220 | { .compatible = "rockchip,rk2928-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4221 | .data = &rk2928_pin_ctrl }, |
Xing Zheng | c5ce767 | 2015-08-28 13:46:47 +0800 | [diff] [blame] | 4222 | { .compatible = "rockchip,rk3036-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4223 | .data = &rk3036_pin_ctrl }, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4224 | { .compatible = "rockchip,rk3066a-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4225 | .data = &rk3066a_pin_ctrl }, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4226 | { .compatible = "rockchip,rk3066b-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4227 | .data = &rk3066b_pin_ctrl }, |
David Wu | d23c66d | 2017-07-21 14:27:15 +0800 | [diff] [blame] | 4228 | { .compatible = "rockchip,rk3128-pinctrl", |
| 4229 | .data = (void *)&rk3128_pin_ctrl }, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4230 | { .compatible = "rockchip,rk3188-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4231 | .data = &rk3188_pin_ctrl }, |
Jeffy Chen | fea0fe6 | 2015-12-09 17:04:06 +0800 | [diff] [blame] | 4232 | { .compatible = "rockchip,rk3228-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4233 | .data = &rk3228_pin_ctrl }, |
Heiko Stübner | 304f077 | 2014-06-16 01:38:14 +0200 | [diff] [blame] | 4234 | { .compatible = "rockchip,rk3288-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4235 | .data = &rk3288_pin_ctrl }, |
Jianqun Xu | 7825aeb | 2019-10-15 17:17:08 +0800 | [diff] [blame] | 4236 | { .compatible = "rockchip,rk3308-pinctrl", |
| 4237 | .data = &rk3308_pin_ctrl }, |
david.wu | 3818e4a | 2017-02-10 18:23:49 +0800 | [diff] [blame] | 4238 | { .compatible = "rockchip,rk3328-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4239 | .data = &rk3328_pin_ctrl }, |
Heiko Stübner | daecdc6 | 2015-06-12 23:51:01 +0200 | [diff] [blame] | 4240 | { .compatible = "rockchip,rk3368-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4241 | .data = &rk3368_pin_ctrl }, |
David Wu | b6c2327 | 2016-02-01 10:58:21 +0800 | [diff] [blame] | 4242 | { .compatible = "rockchip,rk3399-pinctrl", |
Masahiro Yamada | cdbbd26 | 2017-04-28 21:50:35 +0900 | [diff] [blame] | 4243 | .data = &rk3399_pin_ctrl }, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4244 | {}, |
| 4245 | }; |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4246 | |
| 4247 | static struct platform_driver rockchip_pinctrl_driver = { |
| 4248 | .probe = rockchip_pinctrl_probe, |
| 4249 | .driver = { |
| 4250 | .name = "rockchip-pinctrl", |
Chris Zhong | 9198f50 | 2014-10-29 19:51:59 +0800 | [diff] [blame] | 4251 | .pm = &rockchip_pinctrl_dev_pm_ops, |
Axel Lin | 0be9e70 | 2013-08-23 14:27:53 +0800 | [diff] [blame] | 4252 | .of_match_table = rockchip_pinctrl_dt_match, |
Heiko Stübner | d3e5116 | 2013-06-10 22:16:22 +0200 | [diff] [blame] | 4253 | }, |
| 4254 | }; |
| 4255 | |
| 4256 | static int __init rockchip_pinctrl_drv_register(void) |
| 4257 | { |
| 4258 | return platform_driver_register(&rockchip_pinctrl_driver); |
| 4259 | } |
| 4260 | postcore_initcall(rockchip_pinctrl_drv_register); |