| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | if BF561 |
| 2 | |
| 3 | menu "BF561 Specific Configuration" |
| 4 | |
| 5 | comment "Core B Support" |
| 6 | |
| 7 | menu "Core B Support" |
| 8 | |
| 9 | config BF561_COREB |
| 10 | bool "Enable Core B support" |
| 11 | default y |
| 12 | |
| 13 | config BF561_COREB_RESET |
| 14 | bool "Enable Core B reset support" |
| 15 | default n |
| 16 | help |
| 17 | This requires code in the application that is loaded |
| 18 | into Core B. In order to reset, the application needs |
| 19 | to install an interrupt handler for Supplemental |
| 20 | Interrupt 0, that sets RETI to 0xff600000 and writes |
| 21 | bit 11 of SICB_SYSCR when bit 5 of SICA_SYSCR is 0. |
| 22 | This causes Core B to stall when Supplemental Interrupt |
| 23 | 0 is set, and will reset PC to 0xff600000 when |
| 24 | COREB_SRAM_INIT is cleared. |
| 25 | |
| 26 | endmenu |
| 27 | |
| 28 | comment "Interrupt Priority Assignment" |
| 29 | |
| 30 | menu "Priority" |
| 31 | |
| 32 | config IRQ_PLL_WAKEUP |
| 33 | int "PLL Wakeup Interrupt" |
| 34 | default 7 |
| 35 | config IRQ_DMA1_ERROR |
| 36 | int "DMA1 Error (generic)" |
| 37 | default 7 |
| 38 | config IRQ_DMA2_ERROR |
| 39 | int "DMA2 Error (generic)" |
| 40 | default 7 |
| 41 | config IRQ_IMDMA_ERROR |
| 42 | int "IMDMA Error (generic)" |
| 43 | default 7 |
| 44 | config IRQ_PPI0_ERROR |
| 45 | int "PPI0 Error Interrupt" |
| 46 | default 7 |
| 47 | config IRQ_PPI1_ERROR |
| 48 | int "PPI1 Error Interrupt" |
| 49 | default 7 |
| 50 | config IRQ_SPORT0_ERROR |
| 51 | int "SPORT0 Error Interrupt" |
| 52 | default 7 |
| 53 | config IRQ_SPORT1_ERROR |
| 54 | int "SPORT1 Error Interrupt" |
| 55 | default 7 |
| 56 | config IRQ_SPI_ERROR |
| 57 | int "SPI Error Interrupt" |
| 58 | default 7 |
| 59 | config IRQ_UART_ERROR |
| 60 | int "UART Error Interrupt" |
| 61 | default 7 |
| 62 | config IRQ_RESERVED_ERROR |
| 63 | int "Reserved Interrupt" |
| 64 | default 7 |
| 65 | config IRQ_DMA1_0 |
| 66 | int "DMA1 0 Interrupt(PPI1)" |
| 67 | default 8 |
| 68 | config IRQ_DMA1_1 |
| 69 | int "DMA1 1 Interrupt(PPI2)" |
| 70 | default 8 |
| 71 | config IRQ_DMA1_2 |
| 72 | int "DMA1 2 Interrupt" |
| 73 | default 8 |
| 74 | config IRQ_DMA1_3 |
| 75 | int "DMA1 3 Interrupt" |
| 76 | default 8 |
| 77 | config IRQ_DMA1_4 |
| 78 | int "DMA1 4 Interrupt" |
| 79 | default 8 |
| 80 | config IRQ_DMA1_5 |
| 81 | int "DMA1 5 Interrupt" |
| 82 | default 8 |
| 83 | config IRQ_DMA1_6 |
| 84 | int "DMA1 6 Interrupt" |
| 85 | default 8 |
| 86 | config IRQ_DMA1_7 |
| 87 | int "DMA1 7 Interrupt" |
| 88 | default 8 |
| 89 | config IRQ_DMA1_8 |
| 90 | int "DMA1 8 Interrupt" |
| 91 | default 8 |
| 92 | config IRQ_DMA1_9 |
| 93 | int "DMA1 9 Interrupt" |
| 94 | default 8 |
| 95 | config IRQ_DMA1_10 |
| 96 | int "DMA1 10 Interrupt" |
| 97 | default 8 |
| 98 | config IRQ_DMA1_11 |
| 99 | int "DMA1 11 Interrupt" |
| 100 | default 8 |
| 101 | config IRQ_DMA2_0 |
| 102 | int "DMA2 0 (SPORT0 RX)" |
| 103 | default 9 |
| 104 | config IRQ_DMA2_1 |
| 105 | int "DMA2 1 (SPORT0 TX)" |
| 106 | default 9 |
| 107 | config IRQ_DMA2_2 |
| 108 | int "DMA2 2 (SPORT1 RX)" |
| 109 | default 9 |
| 110 | config IRQ_DMA2_3 |
| 111 | int "DMA2 3 (SPORT2 TX)" |
| 112 | default 9 |
| 113 | config IRQ_DMA2_4 |
| 114 | int "DMA2 4 (SPI)" |
| 115 | default 9 |
| 116 | config IRQ_DMA2_5 |
| 117 | int "DMA2 5 (UART RX)" |
| 118 | default 9 |
| 119 | config IRQ_DMA2_6 |
| 120 | int "DMA2 6 (UART TX)" |
| 121 | default 9 |
| 122 | config IRQ_DMA2_7 |
| 123 | int "DMA2 7 Interrupt" |
| 124 | default 9 |
| 125 | config IRQ_DMA2_8 |
| 126 | int "DMA2 8 Interrupt" |
| 127 | default 9 |
| 128 | config IRQ_DMA2_9 |
| 129 | int "DMA2 9 Interrupt" |
| 130 | default 9 |
| 131 | config IRQ_DMA2_10 |
| 132 | int "DMA2 10 Interrupt" |
| 133 | default 9 |
| 134 | config IRQ_DMA2_11 |
| 135 | int "DMA2 11 Interrupt" |
| 136 | default 9 |
| 137 | config IRQ_TIMER0 |
| 138 | int "TIMER 0 Interrupt" |
| 139 | default 10 |
| 140 | config IRQ_TIMER1 |
| 141 | int "TIMER 1 Interrupt" |
| 142 | default 10 |
| 143 | config IRQ_TIMER2 |
| 144 | int "TIMER 2 Interrupt" |
| 145 | default 10 |
| 146 | config IRQ_TIMER3 |
| 147 | int "TIMER 3 Interrupt" |
| 148 | default 10 |
| 149 | config IRQ_TIMER4 |
| 150 | int "TIMER 4 Interrupt" |
| 151 | default 10 |
| 152 | config IRQ_TIMER5 |
| 153 | int "TIMER 5 Interrupt" |
| 154 | default 10 |
| 155 | config IRQ_TIMER6 |
| 156 | int "TIMER 6 Interrupt" |
| 157 | default 10 |
| 158 | config IRQ_TIMER7 |
| 159 | int "TIMER 7 Interrupt" |
| 160 | default 10 |
| 161 | config IRQ_TIMER8 |
| 162 | int "TIMER 8 Interrupt" |
| 163 | default 10 |
| 164 | config IRQ_TIMER9 |
| 165 | int "TIMER 9 Interrupt" |
| 166 | default 10 |
| 167 | config IRQ_TIMER10 |
| 168 | int "TIMER 10 Interrupt" |
| 169 | default 10 |
| 170 | config IRQ_TIMER11 |
| 171 | int "TIMER 11 Interrupt" |
| 172 | default 10 |
| 173 | config IRQ_PROG0_INTA |
| 174 | int "Programmable Flags0 A (8)" |
| 175 | default 11 |
| 176 | config IRQ_PROG0_INTB |
| 177 | int "Programmable Flags0 B (8)" |
| 178 | default 11 |
| 179 | config IRQ_PROG1_INTA |
| 180 | int "Programmable Flags1 A (8)" |
| 181 | default 11 |
| 182 | config IRQ_PROG1_INTB |
| 183 | int "Programmable Flags1 B (8)" |
| 184 | default 11 |
| 185 | config IRQ_PROG2_INTA |
| 186 | int "Programmable Flags2 A (8)" |
| 187 | default 11 |
| 188 | config IRQ_PROG2_INTB |
| 189 | int "Programmable Flags2 B (8)" |
| 190 | default 11 |
| 191 | config IRQ_DMA1_WRRD0 |
| 192 | int "MDMA1 0 write/read INT" |
| 193 | default 8 |
| 194 | config IRQ_DMA1_WRRD1 |
| 195 | int "MDMA1 1 write/read INT" |
| 196 | default 8 |
| 197 | config IRQ_DMA2_WRRD0 |
| 198 | int "MDMA2 0 write/read INT" |
| 199 | default 9 |
| 200 | config IRQ_DMA2_WRRD1 |
| 201 | int "MDMA2 1 write/read INT" |
| 202 | default 9 |
| 203 | config IRQ_IMDMA_WRRD0 |
| 204 | int "IMDMA 0 write/read INT" |
| 205 | default 12 |
| 206 | config IRQ_IMDMA_WRRD1 |
| 207 | int "IMDMA 1 write/read INT" |
| 208 | default 12 |
| 209 | config IRQ_WDTIMER |
| 210 | int "Watch Dog Timer" |
| 211 | default 13 |
| 212 | |
| 213 | help |
| 214 | Enter the priority numbers between 7-13 ONLY. Others are Reserved. |
| 215 | This applies to all the above. It is not recommended to assign the |
| 216 | highest priority number 7 to UART or any other device. |
| 217 | |
| 218 | endmenu |
| 219 | |
| 220 | endmenu |
| 221 | |
| 222 | endif |