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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / a134be34065d52cde948f4ab13d0c1f3d4462c40 / . / arch / arm / boot / dts / omap2430.dtsi
blob: 477b120243ca509df71c53926942afe3b69aea62 [file] [log] [blame]
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]1/*
2 * Device Tree Source for OMAP243x SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2430", "ti,omap2";
15
16 ocp {
Jon Hunter510c0ff2012-10-25 14:24:14 -0500[diff] [blame]17 counter32k: counter@49020000 {
18 compatible = "ti,omap-counter32k";
19 reg = <0x49020000 0x20>;
20 ti,hwmods = "counter_32k";
21 };
22
Tony Lindgren679e3312012-09-10 10:34:51 -0700[diff] [blame]23 omap2430_pmx: pinmux@49002030 {
24 compatible = "ti,omap2430-padconf", "pinctrl-single";
25 reg = <0x49002030 0x0154>;
26 #address-cells = <1>;
27 #size-cells = <0>;
28 pinctrl-single,register-width = <8>;
29 pinctrl-single,function-mask = <0x3f>;
30 };
31
Jon Hunter423182e2013-02-28 15:32:00 -0600[diff] [blame]32 gpio1: gpio@4900c000 {
33 compatible = "ti,omap2-gpio";
34 reg = <0x4900c000 0x200>;
35 interrupts = <29>;
36 ti,hwmods = "gpio1";
37 #gpio-cells = <2>;
38 gpio-controller;
39 #interrupt-cells = <2>;
40 interrupt-controller;
41 };
42
43 gpio2: gpio@4900e000 {
44 compatible = "ti,omap2-gpio";
45 reg = <0x4900e000 0x200>;
46 interrupts = <30>;
47 ti,hwmods = "gpio2";
48 #gpio-cells = <2>;
49 gpio-controller;
50 #interrupt-cells = <2>;
51 interrupt-controller;
52 };
53
54 gpio3: gpio@49010000 {
55 compatible = "ti,omap2-gpio";
56 reg = <0x49010000 0x200>;
57 interrupts = <31>;
58 ti,hwmods = "gpio3";
59 #gpio-cells = <2>;
60 gpio-controller;
61 #interrupt-cells = <2>;
62 interrupt-controller;
63 };
64
65 gpio4: gpio@49012000 {
66 compatible = "ti,omap2-gpio";
67 reg = <0x49012000 0x200>;
68 interrupts = <32>;
69 ti,hwmods = "gpio4";
70 #gpio-cells = <2>;
71 gpio-controller;
72 #interrupt-cells = <2>;
73 interrupt-controller;
74 };
75
76 gpio5: gpio@480b6000 {
77 compatible = "ti,omap2-gpio";
78 reg = <0x480b6000 0x200>;
79 interrupts = <33>;
80 ti,hwmods = "gpio5";
81 #gpio-cells = <2>;
82 gpio-controller;
83 #interrupt-cells = <2>;
84 interrupt-controller;
85 };
86
Jon Hunter1c7dbb52013-02-22 15:33:31 -0600[diff] [blame]87 gpmc: gpmc@6e000000 {
88 compatible = "ti,omap2430-gpmc";
89 reg = <0x6e000000 0x1000>;
90 #address-cells = <2>;
91 #size-cells = <1>;
92 interrupts = <20>;
93 gpmc,num-cs = <8>;
94 gpmc,num-waitpins = <4>;
95 ti,hwmods = "gpmc";
96 };
97
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]98 mcbsp1: mcbsp@48074000 {
99 compatible = "ti,omap2430-mcbsp";
100 reg = <0x48074000 0xff>;
101 reg-names = "mpu";
102 interrupts = <64>, /* OCP compliant interrupt */
103 <59>, /* TX interrupt */
104 <60>, /* RX interrupt */
105 <61>; /* RX overflow interrupt */
106 interrupt-names = "common", "tx", "rx", "rx_overflow";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]107 ti,buffer-size = <128>;
108 ti,hwmods = "mcbsp1";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]109 dmas = <&sdma 31>,
110 <&sdma 32>;
111 dma-names = "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]112 };
113
114 mcbsp2: mcbsp@48076000 {
115 compatible = "ti,omap2430-mcbsp";
116 reg = <0x48076000 0xff>;
117 reg-names = "mpu";
118 interrupts = <16>, /* OCP compliant interrupt */
119 <62>, /* TX interrupt */
120 <63>; /* RX interrupt */
121 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]122 ti,buffer-size = <128>;
123 ti,hwmods = "mcbsp2";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]124 dmas = <&sdma 33>,
125 <&sdma 34>;
126 dma-names = "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]127 };
128
129 mcbsp3: mcbsp@4808c000 {
130 compatible = "ti,omap2430-mcbsp";
131 reg = <0x4808c000 0xff>;
132 reg-names = "mpu";
133 interrupts = <17>, /* OCP compliant interrupt */
134 <89>, /* TX interrupt */
135 <90>; /* RX interrupt */
136 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]137 ti,buffer-size = <128>;
138 ti,hwmods = "mcbsp3";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]139 dmas = <&sdma 17>,
140 <&sdma 18>;
141 dma-names = "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]142 };
143
144 mcbsp4: mcbsp@4808e000 {
145 compatible = "ti,omap2430-mcbsp";
146 reg = <0x4808e000 0xff>;
147 reg-names = "mpu";
148 interrupts = <18>, /* OCP compliant interrupt */
149 <54>, /* TX interrupt */
150 <55>; /* RX interrupt */
151 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]152 ti,buffer-size = <128>;
153 ti,hwmods = "mcbsp4";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]154 dmas = <&sdma 19>,
155 <&sdma 20>;
156 dma-names = "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]157 };
158
159 mcbsp5: mcbsp@48096000 {
160 compatible = "ti,omap2430-mcbsp";
161 reg = <0x48096000 0xff>;
162 reg-names = "mpu";
163 interrupts = <19>, /* OCP compliant interrupt */
164 <81>, /* TX interrupt */
165 <82>; /* RX interrupt */
166 interrupt-names = "common", "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]167 ti,buffer-size = <128>;
168 ti,hwmods = "mcbsp5";
Sebastien Guiriec4e4ead72013-03-11 08:50:21 +0100[diff] [blame]169 dmas = <&sdma 21>,
170 <&sdma 22>;
171 dma-names = "tx", "rx";
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]172 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]173
174 timer1: timer@49018000 {
175 compatible = "ti,omap2-timer";
176 reg = <0x49018000 0x400>;
177 interrupts = <37>;
178 ti,hwmods = "timer1";
179 ti,timer-alwon;
180 };
Peter Ujfalusi3f187f82012-07-26 17:01:32 +0300[diff] [blame]181 };
182};