Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> |
| 4 | * Copyright (C) 2013 John Crispin <blogic@openwrt.org> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/err.h> |
| 8 | #include <linux/gpio/driver.h> |
| 9 | #include <linux/interrupt.h> |
| 10 | #include <linux/io.h> |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/of_irq.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/spinlock.h> |
| 15 | |
| 16 | #define MTK_BANK_CNT 3 |
| 17 | #define MTK_BANK_WIDTH 32 |
| 18 | |
| 19 | #define GPIO_BANK_STRIDE 0x04 |
| 20 | #define GPIO_REG_CTRL 0x00 |
| 21 | #define GPIO_REG_POL 0x10 |
| 22 | #define GPIO_REG_DATA 0x20 |
| 23 | #define GPIO_REG_DSET 0x30 |
| 24 | #define GPIO_REG_DCLR 0x40 |
| 25 | #define GPIO_REG_REDGE 0x50 |
| 26 | #define GPIO_REG_FEDGE 0x60 |
| 27 | #define GPIO_REG_HLVL 0x70 |
| 28 | #define GPIO_REG_LLVL 0x80 |
| 29 | #define GPIO_REG_STAT 0x90 |
| 30 | #define GPIO_REG_EDGE 0xA0 |
| 31 | |
| 32 | struct mtk_gc { |
| 33 | struct gpio_chip chip; |
| 34 | spinlock_t lock; |
| 35 | int bank; |
| 36 | u32 rising; |
| 37 | u32 falling; |
| 38 | u32 hlevel; |
| 39 | u32 llevel; |
| 40 | }; |
| 41 | |
| 42 | /** |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 43 | * struct mtk - state container for |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 44 | * data of the platform driver. It is 3 |
| 45 | * separate gpio-chip each one with its |
| 46 | * own irq_chip. |
| 47 | * @dev: device instance |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 48 | * @base: memory base address |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 49 | * @gpio_irq: irq number from the device tree |
| 50 | * @gc_map: array of the gpio chips |
| 51 | */ |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 52 | struct mtk { |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 53 | struct device *dev; |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 54 | void __iomem *base; |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 55 | int gpio_irq; |
| 56 | struct mtk_gc gc_map[MTK_BANK_CNT]; |
| 57 | }; |
| 58 | |
| 59 | static inline struct mtk_gc * |
| 60 | to_mediatek_gpio(struct gpio_chip *chip) |
| 61 | { |
| 62 | return container_of(chip, struct mtk_gc, chip); |
| 63 | } |
| 64 | |
| 65 | static inline void |
| 66 | mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) |
| 67 | { |
| 68 | struct gpio_chip *gc = &rg->chip; |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 69 | struct mtk *mtk = gpiochip_get_data(gc); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 70 | |
| 71 | offset = (rg->bank * GPIO_BANK_STRIDE) + offset; |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 72 | gc->write_reg(mtk->base + offset, val); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | static inline u32 |
| 76 | mtk_gpio_r32(struct mtk_gc *rg, u32 offset) |
| 77 | { |
| 78 | struct gpio_chip *gc = &rg->chip; |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 79 | struct mtk *mtk = gpiochip_get_data(gc); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 80 | |
| 81 | offset = (rg->bank * GPIO_BANK_STRIDE) + offset; |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 82 | return gc->read_reg(mtk->base + offset); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | static irqreturn_t |
| 86 | mediatek_gpio_irq_handler(int irq, void *data) |
| 87 | { |
| 88 | struct gpio_chip *gc = data; |
| 89 | struct mtk_gc *rg = to_mediatek_gpio(gc); |
| 90 | irqreturn_t ret = IRQ_NONE; |
| 91 | unsigned long pending; |
| 92 | int bit; |
| 93 | |
| 94 | pending = mtk_gpio_r32(rg, GPIO_REG_STAT); |
| 95 | |
| 96 | for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { |
| 97 | u32 map = irq_find_mapping(gc->irq.domain, bit); |
| 98 | |
| 99 | generic_handle_irq(map); |
| 100 | mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); |
| 101 | ret |= IRQ_HANDLED; |
| 102 | } |
| 103 | |
| 104 | return ret; |
| 105 | } |
| 106 | |
| 107 | static void |
| 108 | mediatek_gpio_irq_unmask(struct irq_data *d) |
| 109 | { |
| 110 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 111 | struct mtk_gc *rg = to_mediatek_gpio(gc); |
| 112 | int pin = d->hwirq; |
| 113 | unsigned long flags; |
| 114 | u32 rise, fall, high, low; |
| 115 | |
| 116 | spin_lock_irqsave(&rg->lock, flags); |
| 117 | rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); |
| 118 | fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); |
| 119 | high = mtk_gpio_r32(rg, GPIO_REG_HLVL); |
| 120 | low = mtk_gpio_r32(rg, GPIO_REG_LLVL); |
| 121 | mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising)); |
| 122 | mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); |
| 123 | mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); |
| 124 | mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); |
| 125 | spin_unlock_irqrestore(&rg->lock, flags); |
| 126 | } |
| 127 | |
| 128 | static void |
| 129 | mediatek_gpio_irq_mask(struct irq_data *d) |
| 130 | { |
| 131 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 132 | struct mtk_gc *rg = to_mediatek_gpio(gc); |
| 133 | int pin = d->hwirq; |
| 134 | unsigned long flags; |
| 135 | u32 rise, fall, high, low; |
| 136 | |
| 137 | spin_lock_irqsave(&rg->lock, flags); |
| 138 | rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); |
| 139 | fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); |
| 140 | high = mtk_gpio_r32(rg, GPIO_REG_HLVL); |
| 141 | low = mtk_gpio_r32(rg, GPIO_REG_LLVL); |
| 142 | mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); |
| 143 | mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); |
| 144 | mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); |
| 145 | mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); |
| 146 | spin_unlock_irqrestore(&rg->lock, flags); |
| 147 | } |
| 148 | |
| 149 | static int |
| 150 | mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) |
| 151 | { |
| 152 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
| 153 | struct mtk_gc *rg = to_mediatek_gpio(gc); |
| 154 | int pin = d->hwirq; |
| 155 | u32 mask = BIT(pin); |
| 156 | |
| 157 | if (type == IRQ_TYPE_PROBE) { |
| 158 | if ((rg->rising | rg->falling | |
| 159 | rg->hlevel | rg->llevel) & mask) |
| 160 | return 0; |
| 161 | |
| 162 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 163 | } |
| 164 | |
| 165 | rg->rising &= ~mask; |
| 166 | rg->falling &= ~mask; |
| 167 | rg->hlevel &= ~mask; |
| 168 | rg->llevel &= ~mask; |
| 169 | |
| 170 | switch (type & IRQ_TYPE_SENSE_MASK) { |
| 171 | case IRQ_TYPE_EDGE_BOTH: |
| 172 | rg->rising |= mask; |
| 173 | rg->falling |= mask; |
| 174 | break; |
| 175 | case IRQ_TYPE_EDGE_RISING: |
| 176 | rg->rising |= mask; |
| 177 | break; |
| 178 | case IRQ_TYPE_EDGE_FALLING: |
| 179 | rg->falling |= mask; |
| 180 | break; |
| 181 | case IRQ_TYPE_LEVEL_HIGH: |
| 182 | rg->hlevel |= mask; |
| 183 | break; |
| 184 | case IRQ_TYPE_LEVEL_LOW: |
| 185 | rg->llevel |= mask; |
| 186 | break; |
| 187 | } |
| 188 | |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | static struct irq_chip mediatek_gpio_irq_chip = { |
| 193 | .irq_unmask = mediatek_gpio_irq_unmask, |
| 194 | .irq_mask = mediatek_gpio_irq_mask, |
| 195 | .irq_mask_ack = mediatek_gpio_irq_mask, |
| 196 | .irq_set_type = mediatek_gpio_irq_type, |
| 197 | }; |
| 198 | |
| 199 | static int |
| 200 | mediatek_gpio_xlate(struct gpio_chip *chip, |
| 201 | const struct of_phandle_args *spec, u32 *flags) |
| 202 | { |
| 203 | int gpio = spec->args[0]; |
| 204 | struct mtk_gc *rg = to_mediatek_gpio(chip); |
| 205 | |
| 206 | if (rg->bank != gpio / MTK_BANK_WIDTH) |
| 207 | return -EINVAL; |
| 208 | |
| 209 | if (flags) |
| 210 | *flags = spec->args[1]; |
| 211 | |
| 212 | return gpio % MTK_BANK_WIDTH; |
| 213 | } |
| 214 | |
| 215 | static int |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 216 | mediatek_gpio_bank_probe(struct device *dev, |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 217 | struct device_node *node, int bank) |
| 218 | { |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 219 | struct mtk *mtk = dev_get_drvdata(dev); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 220 | struct mtk_gc *rg; |
| 221 | void __iomem *dat, *set, *ctrl, *diro; |
| 222 | int ret; |
| 223 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 224 | rg = &mtk->gc_map[bank]; |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 225 | memset(rg, 0, sizeof(*rg)); |
| 226 | |
| 227 | spin_lock_init(&rg->lock); |
| 228 | rg->chip.of_node = node; |
| 229 | rg->bank = bank; |
| 230 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 231 | dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); |
| 232 | set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); |
| 233 | ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); |
| 234 | diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 235 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 236 | ret = bgpio_init(&rg->chip, dev, 4, |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 237 | dat, set, ctrl, diro, NULL, 0); |
| 238 | if (ret) { |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 239 | dev_err(dev, "bgpio_init() failed\n"); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 240 | return ret; |
| 241 | } |
| 242 | |
| 243 | rg->chip.of_gpio_n_cells = 2; |
| 244 | rg->chip.of_xlate = mediatek_gpio_xlate; |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 245 | rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", |
| 246 | dev_name(dev), bank); |
Nicholas Mc Guire | 59d646c | 2018-11-21 19:06:12 +0100 | [diff] [blame] | 247 | if (!rg->chip.label) |
| 248 | return -ENOMEM; |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 249 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 250 | ret = devm_gpiochip_add_data(dev, &rg->chip, mtk); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 251 | if (ret < 0) { |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 252 | dev_err(dev, "Could not register gpio %d, ret=%d\n", |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 253 | rg->chip.ngpio, ret); |
| 254 | return ret; |
| 255 | } |
| 256 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 257 | if (mtk->gpio_irq) { |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 258 | /* |
| 259 | * Manually request the irq here instead of passing |
| 260 | * a flow-handler to gpiochip_set_chained_irqchip, |
| 261 | * because the irq is shared. |
| 262 | */ |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 263 | ret = devm_request_irq(dev, mtk->gpio_irq, |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 264 | mediatek_gpio_irq_handler, IRQF_SHARED, |
| 265 | rg->chip.label, &rg->chip); |
| 266 | |
| 267 | if (ret) { |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 268 | dev_err(dev, "Error requesting IRQ %d: %d\n", |
| 269 | mtk->gpio_irq, ret); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 270 | return ret; |
| 271 | } |
| 272 | |
| 273 | ret = gpiochip_irqchip_add(&rg->chip, &mediatek_gpio_irq_chip, |
| 274 | 0, handle_simple_irq, IRQ_TYPE_NONE); |
| 275 | if (ret) { |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 276 | dev_err(dev, "failed to add gpiochip_irqchip\n"); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 277 | return ret; |
| 278 | } |
| 279 | |
| 280 | gpiochip_set_chained_irqchip(&rg->chip, &mediatek_gpio_irq_chip, |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 281 | mtk->gpio_irq, NULL); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 282 | } |
| 283 | |
| 284 | /* set polarity to low for all gpios */ |
| 285 | mtk_gpio_w32(rg, GPIO_REG_POL, 0); |
| 286 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 287 | dev_info(dev, "registering %d gpios\n", rg->chip.ngpio); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 288 | |
| 289 | return 0; |
| 290 | } |
| 291 | |
| 292 | static int |
| 293 | mediatek_gpio_probe(struct platform_device *pdev) |
| 294 | { |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 295 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 296 | struct device *dev = &pdev->dev; |
| 297 | struct device_node *np = dev->of_node; |
| 298 | struct mtk *mtk; |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 299 | int i; |
Nicholas Mc Guire | a109c2d | 2018-11-27 18:00:18 +0100 | [diff] [blame^] | 300 | int ret; |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 301 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 302 | mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); |
| 303 | if (!mtk) |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 304 | return -ENOMEM; |
| 305 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 306 | mtk->base = devm_ioremap_resource(dev, res); |
| 307 | if (IS_ERR(mtk->base)) |
| 308 | return PTR_ERR(mtk->base); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 309 | |
Linus Walleij | 8512486 | 2018-07-09 13:51:57 +0200 | [diff] [blame] | 310 | mtk->gpio_irq = irq_of_parse_and_map(np, 0); |
| 311 | mtk->dev = dev; |
| 312 | platform_set_drvdata(pdev, mtk); |
| 313 | mediatek_gpio_irq_chip.name = dev_name(dev); |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 314 | |
Nicholas Mc Guire | a109c2d | 2018-11-27 18:00:18 +0100 | [diff] [blame^] | 315 | for (i = 0; i < MTK_BANK_CNT; i++) { |
| 316 | ret = mediatek_gpio_bank_probe(dev, np, i); |
| 317 | if (ret) |
| 318 | return ret; |
| 319 | } |
Sergio Paracuellos | 4ba9c3a | 2018-07-05 15:43:10 +0200 | [diff] [blame] | 320 | |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | static const struct of_device_id mediatek_gpio_match[] = { |
| 325 | { .compatible = "mediatek,mt7621-gpio" }, |
| 326 | {}, |
| 327 | }; |
| 328 | MODULE_DEVICE_TABLE(of, mediatek_gpio_match); |
| 329 | |
| 330 | static struct platform_driver mediatek_gpio_driver = { |
| 331 | .probe = mediatek_gpio_probe, |
| 332 | .driver = { |
| 333 | .name = "mt7621_gpio", |
| 334 | .of_match_table = mediatek_gpio_match, |
| 335 | }, |
| 336 | }; |
| 337 | |
| 338 | builtin_platform_driver(mediatek_gpio_driver); |