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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / a06b85ff07147cf03c4d5e17db9ac0644bd27861 / . / drivers / edac / Kconfig
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Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]1#
2# EDAC Kconfig
Doug Thompson4577ca52009-04-02 16:58:43 -0700[diff] [blame]3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]4# Licensed and distributed under the GPL
Borislav Petkovb01aec92015-05-21 19:59:31 +0200[diff] [blame]5
6config EDAC_ATOMIC_SCRUB
7 bool
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]8
Borislav Petkov544516632012-12-18 22:02:56 +0100[diff] [blame]9config EDAC_SUPPORT
10 bool
11
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700[diff] [blame]12menuconfig EDAC
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]13 tristate "EDAC (Error Detection And Correction) reporting"
14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]15 help
Borislav Petkova06b85f2017-02-04 16:32:27 +0100[diff] [blame^]16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
18 in the CPU or supporting chipset or other subsystems:
Douglas Thompson8cb2a3982007-07-19 01:50:12 -0700[diff] [blame]19 memory errors, cache errors, PCI errors, thermal throttling, etc..
20 If unsure, select 'Y'.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]21
Borislav Petkova06b85f2017-02-04 16:32:27 +0100[diff] [blame^]22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
Tim Small57c432b2006-03-09 17:33:50 -0800[diff] [blame]23
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700[diff] [blame]24if EDAC
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]25
Mauro Carvalho Chehab19974712012-03-21 17:06:53 -0300[diff] [blame]26config EDAC_LEGACY_SYSFS
27 bool "EDAC legacy sysfs"
28 default y
29 help
30 Enable the compatibility sysfs nodes.
31 Use 'Y' if your edac utilities aren't ported to work with the newer
32 structures.
33
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]34config EDAC_DEBUG
35 bool "Debugging"
Borislav Petkov1c5bf782017-03-18 18:25:05 +0100[diff] [blame]36 select DEBUG_FS
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]37 help
Borislav Petkov37929872012-09-10 16:50:54 +0200[diff] [blame]38 This turns on debugging information for the entire EDAC subsystem.
39 You do so by inserting edac_module with "edac_debug_level=x." Valid
40 levels are 0-4 (from low to high) and by default it is set to 2.
41 Usually you should select 'N' here.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]42
Borislav Petkov9cdeb402010-09-02 18:33:24 +0200[diff] [blame]43config EDAC_DECODE_MCE
Borislav Petkov0d18b2e2009-10-02 15:31:48 +0200[diff] [blame]44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
Borislav Petkov168eb342011-08-10 09:43:30 -0300[diff] [blame]45 depends on CPU_SUP_AMD && X86_MCE_AMD
Borislav Petkov0d18b2e2009-10-02 15:31:48 +0200[diff] [blame]46 default y
47 ---help---
48 Enable this option if you want to decode Machine Check Exceptions
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]49 occurring on your machine in human-readable form.
Borislav Petkov0d18b2e2009-10-02 15:31:48 +0200[diff] [blame]50
51 You should definitely say Y here in case you want to decode MCEs
52 which occur really early upon boot, before the module infrastructure
53 has been initialized.
54
Mauro Carvalho Chehab77c5f5d2013-02-15 06:11:57 -0300[diff] [blame]55config EDAC_GHES
56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]57 depends on ACPI_APEI_GHES && (EDAC=y)
Mauro Carvalho Chehab77c5f5d2013-02-15 06:11:57 -0300[diff] [blame]58 default y
59 help
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
62 APEI/GHES driver. By enabling this option, the error reports provided
63 by GHES are sent to userspace via the EDAC API.
64
65 When this option is enabled, it will disable the hardware-driven
66 mechanisms, if a GHES BIOS is detected, entering into the
67 "Firmware First" mode.
68
69 It should be noticed that keeping both GHES and a hardware-driven
70 error mechanism won't work well, as BIOS will race with OS, while
71 reading the error registers. So, if you want to not use "Firmware
72 first" GHES error mechanism, you should disable GHES either at
73 compilation time or by passing "ghes.disable=1" Kernel parameter
74 at boot time.
75
76 In doubt, say 'Y'.
77
Doug Thompson7d6034d2009-04-27 20:01:01 +0200[diff] [blame]78config EDAC_AMD64
Tomasz Palaf5b10c42014-11-02 11:22:12 +0100[diff] [blame]79 tristate "AMD64 (Opteron, Athlon64)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]80 depends on AMD_NB && EDAC_DECODE_MCE
Doug Thompson7d6034d2009-04-27 20:01:01 +0200[diff] [blame]81 help
Borislav Petkov027dbd62010-10-13 22:12:15 +0200[diff] [blame]82 Support for error detection and correction of DRAM ECC errors on
Tomasz Palaf5b10c42014-11-02 11:22:12 +0100[diff] [blame]83 the AMD64 families (>= K8) of memory controllers.
Doug Thompson7d6034d2009-04-27 20:01:01 +0200[diff] [blame]84
85config EDAC_AMD64_ERROR_INJECTION
Borislav Petkov9cdeb402010-09-02 18:33:24 +0200[diff] [blame]86 bool "Sysfs HW Error injection facilities"
Doug Thompson7d6034d2009-04-27 20:01:01 +0200[diff] [blame]87 depends on EDAC_AMD64
88 help
89 Recent Opterons (Family 10h and later) provide for Memory Error
90 Injection into the ECC detection circuits. The amd64_edac module
91 allows the operator/user to inject Uncorrectable and Correctable
92 errors into DRAM.
93
94 When enabled, in each of the respective memory controller directories
95 (/sys/devices/system/edac/mc/mcX), there are 3 input files:
96
97 - inject_section (0..3, 16-byte section of 64-byte cacheline),
98 - inject_word (0..8, 16-bit word of 16-byte section),
99 - inject_ecc_vector (hex ecc vector: select bits of inject word)
100
101 In addition, there are two control files, inject_read and inject_write,
102 which trigger the DRAM ECC Read and Write respectively.
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]103
104config EDAC_AMD76X
105 tristate "AMD 76x (760, 762, 768)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]106 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]107 help
108 Support for error detection and correction on the AMD 76x
109 series of chipsets used with the Athlon processor.
110
111config EDAC_E7XXX
112 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]113 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]114 help
115 Support for error detection and correction on the Intel
116 E7205, E7500, E7501 and E7505 server chipsets.
117
118config EDAC_E752X
Andrei Konovalov5135b792008-04-29 01:03:13 -0700[diff] [blame]119 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]120 depends on PCI && X86
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]121 help
122 Support for error detection and correction on the Intel
123 E7520, E7525, E7320 server chipsets.
124
Tim Small5a2c6752007-07-19 01:49:42 -0700[diff] [blame]125config EDAC_I82443BXGX
126 tristate "Intel 82443BX/GX (440BX/GX)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]127 depends on PCI && X86_32
Andrew Morton28f96eea2007-07-19 01:49:45 -0700[diff] [blame]128 depends on BROKEN
Tim Small5a2c6752007-07-19 01:49:42 -0700[diff] [blame]129 help
130 Support for error detection and correction on the Intel
131 82443BX/GX memory controllers (440BX/GX chipsets).
132
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]133config EDAC_I82875P
134 tristate "Intel 82875p (D82875P, E7210)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]135 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]136 help
137 Support for error detection and correction on the Intel
138 DP82785P and E7210 server chipsets.
139
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700[diff] [blame]140config EDAC_I82975X
141 tristate "Intel 82975x (D82975x)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]142 depends on PCI && X86
Ranganathan Desikan420390f2007-07-19 01:50:31 -0700[diff] [blame]143 help
144 Support for error detection and correction on the Intel
145 DP82975x server chipsets.
146
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700[diff] [blame]147config EDAC_I3000
148 tristate "Intel 3000/3010"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]149 depends on PCI && X86
Jason Uhlenkott535c6a52007-07-19 01:49:48 -0700[diff] [blame]150 help
151 Support for error detection and correction on the Intel
152 3000 and 3010 server chipsets.
153
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700[diff] [blame]154config EDAC_I3200
155 tristate "Intel 3200"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]156 depends on PCI && X86
Jason Uhlenkottdd8ef1d2009-09-23 15:57:27 -0700[diff] [blame]157 help
158 Support for error detection and correction on the Intel
159 3200 and 3210 server chipsets.
160
Jason Baron7ee40b82014-07-04 13:48:32 +0200[diff] [blame]161config EDAC_IE31200
162 tristate "Intel e312xx"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]163 depends on PCI && X86
Jason Baron7ee40b82014-07-04 13:48:32 +0200[diff] [blame]164 help
165 Support for error detection and correction on the Intel
166 E3-1200 based DRAM controllers.
167
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700[diff] [blame]168config EDAC_X38
169 tristate "Intel X38"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]170 depends on PCI && X86
Hitoshi Mitakedf8bc08c2008-10-29 14:00:50 -0700[diff] [blame]171 help
172 Support for error detection and correction on the Intel
173 X38 server chipsets.
174
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800[diff] [blame]175config EDAC_I5400
176 tristate "Intel 5400 (Seaburg) chipsets"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]177 depends on PCI && X86
Mauro Carvalho Chehab920c8df2009-01-06 14:43:00 -0800[diff] [blame]178 help
179 Support for error detection and correction the Intel
180 i5400 MCH chipset (Seaburg).
181
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300[diff] [blame]182config EDAC_I7CORE
183 tristate "Intel i7 Core (Nehalem) processors"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]184 depends on PCI && X86 && X86_MCE_INTEL
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300[diff] [blame]185 help
186 Support for error detection and correction the Intel
Mauro Carvalho Chehab696e4092009-07-23 06:57:45 -0300[diff] [blame]187 i7 Core (Nehalem) Integrated Memory Controller that exists on
188 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
189 and Xeon 55xx processors.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300[diff] [blame]190
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]191config EDAC_I82860
192 tristate "Intel 82860"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]193 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]194 help
195 Support for error detection and correction on the Intel
196 82860 chipset.
197
198config EDAC_R82600
199 tristate "Radisys 82600 embedded chipset"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]200 depends on PCI && X86_32
Alan Coxda9bb1d2006-01-18 17:44:13 -0800[diff] [blame]201 help
202 Support for error detection and correction on the Radisys
203 82600 embedded chipset.
204
Eric Wolleseneb607052007-07-19 01:49:39 -0700[diff] [blame]205config EDAC_I5000
206 tristate "Intel Greencreek/Blackford chipset"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]207 depends on X86 && PCI
Eric Wolleseneb607052007-07-19 01:49:39 -0700[diff] [blame]208 help
209 Support for error detection and correction the Intel
210 Greekcreek/Blackford chipsets.
211
Arthur Jones8f421c592008-07-25 01:49:04 -0700[diff] [blame]212config EDAC_I5100
213 tristate "Intel San Clemente MCH"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]214 depends on X86 && PCI
Arthur Jones8f421c592008-07-25 01:49:04 -0700[diff] [blame]215 help
216 Support for error detection and correction the Intel
217 San Clemente MCH.
218
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300[diff] [blame]219config EDAC_I7300
220 tristate "Intel Clarksboro MCH"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]221 depends on X86 && PCI
Mauro Carvalho Chehabfcaf7802010-08-24 23:22:57 -0300[diff] [blame]222 help
223 Support for error detection and correction the Intel
224 Clarksboro MCH (Intel 7300 chipset).
225
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200[diff] [blame]226config EDAC_SBRIDGE
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300[diff] [blame]227 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]228 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200[diff] [blame]229 help
230 Support for error detection and correction the Intel
Aristeu Rozanski50d1bb92014-06-20 10:27:54 -0300[diff] [blame]231 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
Mauro Carvalho Chehab3d78c9a2011-10-20 19:33:46 -0200[diff] [blame]232
Tony Luck4ec656b2016-08-20 16:27:58 -0700[diff] [blame]233config EDAC_SKX
234 tristate "Intel Skylake server Integrated MC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]235 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
Tony Luck4ec656b2016-08-20 16:27:58 -0700[diff] [blame]236 help
237 Support for error detection and correction the Intel
238 Skylake server Integrated Memory Controllers.
239
Tony Luck5c71ad12017-03-09 01:45:39 +0800[diff] [blame]240config EDAC_PND2
241 tristate "Intel Pondicherry2"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]242 depends on PCI && X86_64 && X86_MCE_INTEL
Tony Luck5c71ad12017-03-09 01:45:39 +0800[diff] [blame]243 help
244 Support for error detection and correction on the Intel
245 Pondicherry2 Integrated Memory Controller. This SoC IP is
246 first used on the Apollo Lake platform and Denverton
247 micro-server but may appear on others in the future.
248
Dave Jianga9a753d2008-02-07 00:14:55 -0800[diff] [blame]249config EDAC_MPC85XX
Ira W. Snyderb4846252009-09-23 15:57:25 -0700[diff] [blame]250 tristate "Freescale MPC83xx / MPC85xx"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]251 depends on FSL_SOC
Dave Jianga9a753d2008-02-07 00:14:55 -0800[diff] [blame]252 help
253 Support for error detection and correction on the Freescale
York Sun74210262015-05-12 18:03:41 +0800[diff] [blame]254 MPC8349, MPC8560, MPC8540, MPC8548, T4240
Dave Jianga9a753d2008-02-07 00:14:55 -0800[diff] [blame]255
York Suneeb3d682016-08-23 15:14:03 -0700[diff] [blame]256config EDAC_LAYERSCAPE
257 tristate "Freescale Layerscape DDR"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]258 depends on ARCH_LAYERSCAPE
York Suneeb3d682016-08-23 15:14:03 -0700[diff] [blame]259 help
260 Support for error detection and correction on Freescale memory
261 controllers on Layerscape SoCs.
262
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800[diff] [blame]263config EDAC_MV64X60
264 tristate "Marvell MV64x60"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]265 depends on MV64X60
Dave Jiang4f4aeea2008-02-07 00:14:56 -0800[diff] [blame]266 help
267 Support for error detection and correction on the Marvell
268 MV64360 and MV64460 chipsets.
269
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700[diff] [blame]270config EDAC_PASEMI
271 tristate "PA Semi PWRficient"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]272 depends on PPC_PASEMI && PCI
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700[diff] [blame]273 help
274 Support for error detection and correction on PA Semi
275 PWRficient.
276
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800[diff] [blame]277config EDAC_CELL
278 tristate "Cell Broadband Engine memory controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]279 depends on PPC_CELL_COMMON
Benjamin Herrenschmidt48764e42008-02-07 00:14:53 -0800[diff] [blame]280 help
281 Support for error detection and correction on the
282 Cell Broadband Engine internal memory controller
283 on platform without a hypervisor
Egor Martovetsky7d8536f2007-07-19 01:50:24 -0700[diff] [blame]284
Grant Ericksondba7a772009-04-02 16:58:45 -0700[diff] [blame]285config EDAC_PPC4XX
286 tristate "PPC4xx IBM DDR2 Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]287 depends on 4xx
Grant Ericksondba7a772009-04-02 16:58:45 -0700[diff] [blame]288 help
289 This enables support for EDAC on the ECC memory used
290 with the IBM DDR2 memory controller found in various
291 PowerPC 4xx embedded processors such as the 405EX[r],
292 440SP, 440SPe, 460EX, 460GT and 460SX.
293
Harry Ciaoe8765582009-04-02 16:58:51 -0700[diff] [blame]294config EDAC_AMD8131
295 tristate "AMD8131 HyperTransport PCI-X Tunnel"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]296 depends on PCI && PPC_MAPLE
Harry Ciaoe8765582009-04-02 16:58:51 -0700[diff] [blame]297 help
298 Support for error detection and correction on the
299 AMD8131 HyperTransport PCI-X Tunnel chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700[diff] [blame]300 Note, add more Kconfig dependency if it's adopted
301 on some machine other than Maple.
Harry Ciaoe8765582009-04-02 16:58:51 -0700[diff] [blame]302
Harry Ciao58b4ce62009-04-02 16:58:51 -0700[diff] [blame]303config EDAC_AMD8111
304 tristate "AMD8111 HyperTransport I/O Hub"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]305 depends on PCI && PPC_MAPLE
Harry Ciao58b4ce62009-04-02 16:58:51 -0700[diff] [blame]306 help
307 Support for error detection and correction on the
308 AMD8111 HyperTransport I/O Hub chip.
Harry Ciao715fe7a2009-05-28 14:34:43 -0700[diff] [blame]309 Note, add more Kconfig dependency if it's adopted
310 on some machine other than Maple.
Harry Ciao58b4ce62009-04-02 16:58:51 -0700[diff] [blame]311
Harry Ciao2a9036a2009-06-17 16:27:58 -0700[diff] [blame]312config EDAC_CPC925
313 tristate "IBM CPC925 Memory Controller (PPC970FX)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]314 depends on PPC64
Harry Ciao2a9036a2009-06-17 16:27:58 -0700[diff] [blame]315 help
316 Support for error detection and correction on the
317 IBM CPC925 Bridge and Memory Controller, which is
318 a companion chip to the PowerPC 970 family of
319 processors.
320
Chris Metcalf5c770752011-03-01 13:01:49 -0500[diff] [blame]321config EDAC_TILE
322 tristate "Tilera Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]323 depends on TILE
Chris Metcalf5c770752011-03-01 13:01:49 -0500[diff] [blame]324 default y
325 help
326 Support for error detection and correction on the
327 Tilera memory controller.
328
Rob Herringa1b01ed2012-06-13 12:01:55 -0500[diff] [blame]329config EDAC_HIGHBANK_MC
330 tristate "Highbank Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]331 depends on ARCH_HIGHBANK
Rob Herringa1b01ed2012-06-13 12:01:55 -0500[diff] [blame]332 help
333 Support for error detection and correction on the
334 Calxeda Highbank memory controller.
335
Rob Herring69154d02012-06-11 21:32:14 -0500[diff] [blame]336config EDAC_HIGHBANK_L2
337 tristate "Highbank L2 Cache"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]338 depends on ARCH_HIGHBANK
Rob Herring69154d02012-06-11 21:32:14 -0500[diff] [blame]339 help
340 Support for error detection and correction on the
341 Calxeda Highbank memory controller.
342
Ralf Baechlef65aad42012-10-17 00:39:09 +0200[diff] [blame]343config EDAC_OCTEON_PC
344 tristate "Cavium Octeon Primary Caches"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]345 depends on CPU_CAVIUM_OCTEON
Ralf Baechlef65aad42012-10-17 00:39:09 +0200[diff] [blame]346 help
347 Support for error detection and correction on the primary caches of
348 the cnMIPS cores of Cavium Octeon family SOCs.
349
350config EDAC_OCTEON_L2C
351 tristate "Cavium Octeon Secondary Caches (L2C)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]352 depends on CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200[diff] [blame]353 help
354 Support for error detection and correction on the
355 Cavium Octeon family of SOCs.
356
357config EDAC_OCTEON_LMC
358 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]359 depends on CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200[diff] [blame]360 help
361 Support for error detection and correction on the
362 Cavium Octeon family of SOCs.
363
364config EDAC_OCTEON_PCI
365 tristate "Cavium Octeon PCI Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]366 depends on PCI && CAVIUM_OCTEON_SOC
Ralf Baechlef65aad42012-10-17 00:39:09 +0200[diff] [blame]367 help
368 Support for error detection and correction on the
369 Cavium Octeon family of SOCs.
370
Sergey Temerkhanov41003392017-03-24 22:28:37 +0000[diff] [blame]371config EDAC_THUNDERX
372 tristate "Cavium ThunderX EDAC"
Sergey Temerkhanov41003392017-03-24 22:28:37 +0000[diff] [blame]373 depends on ARM64
374 depends on PCI
375 help
376 Support for error detection and correction on the
377 Cavium ThunderX memory controllers (LMC), Cache
378 Coherent Processor Interconnect (CCPI) and L2 cache
379 blocks (TAD, CBC, MCI).
380
Thor Thayerc3eea192016-02-10 13:26:21 -0600[diff] [blame]381config EDAC_ALTERA
382 bool "Altera SOCFPGA ECC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]383 depends on EDAC=y && ARCH_SOCFPGA
Thor Thayer71bcada2014-09-03 10:27:54 -0500[diff] [blame]384 help
385 Support for error detection and correction on the
Thor Thayerc3eea192016-02-10 13:26:21 -0600[diff] [blame]386 Altera SOCs. This must be selected for SDRAM ECC.
387 Note that the preloader must initialize the SDRAM
388 before loading the kernel.
389
390config EDAC_ALTERA_L2C
391 bool "Altera L2 Cache ECC"
Thor Thayer3a8f21f2016-03-21 11:01:38 -0500[diff] [blame]392 depends on EDAC_ALTERA=y && CACHE_L2X0
Thor Thayerc3eea192016-02-10 13:26:21 -0600[diff] [blame]393 help
394 Support for error detection and correction on the
395 Altera L2 cache Memory for Altera SoCs. This option
Thor Thayer3a8f21f2016-03-21 11:01:38 -0500[diff] [blame]396 requires L2 cache.
Thor Thayerc3eea192016-02-10 13:26:21 -0600[diff] [blame]397
398config EDAC_ALTERA_OCRAM
399 bool "Altera On-Chip RAM ECC"
400 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
401 help
402 Support for error detection and correction on the
403 Altera On-Chip RAM Memory for Altera SoCs.
Thor Thayer71bcada2014-09-03 10:27:54 -0500[diff] [blame]404
Thor Thayerab8c1e02016-06-22 08:58:58 -0500[diff] [blame]405config EDAC_ALTERA_ETHERNET
406 bool "Altera Ethernet FIFO ECC"
407 depends on EDAC_ALTERA=y
408 help
409 Support for error detection and correction on the
410 Altera Ethernet FIFO Memory for Altera SoCs.
411
Thor Thayerc6882fb2016-07-14 11:06:43 -0500[diff] [blame]412config EDAC_ALTERA_NAND
413 bool "Altera NAND FIFO ECC"
414 depends on EDAC_ALTERA=y && MTD_NAND_DENALI
415 help
416 Support for error detection and correction on the
417 Altera NAND FIFO Memory for Altera SoCs.
418
Thor Thayere8263792016-07-28 10:03:57 +0200[diff] [blame]419config EDAC_ALTERA_DMA
420 bool "Altera DMA FIFO ECC"
421 depends on EDAC_ALTERA=y && PL330_DMA=y
422 help
423 Support for error detection and correction on the
424 Altera DMA FIFO Memory for Altera SoCs.
425
Thor Thayerc6095812016-07-14 11:06:45 -0500[diff] [blame]426config EDAC_ALTERA_USB
427 bool "Altera USB FIFO ECC"
428 depends on EDAC_ALTERA=y && USB_DWC2
429 help
430 Support for error detection and correction on the
431 Altera USB FIFO Memory for Altera SoCs.
432
Thor Thayer485fe9e2016-07-14 11:06:46 -0500[diff] [blame]433config EDAC_ALTERA_QSPI
434 bool "Altera QSPI FIFO ECC"
435 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
436 help
437 Support for error detection and correction on the
438 Altera QSPI FIFO Memory for Altera SoCs.
439
Thor Thayer91104982016-08-09 09:40:52 -0500[diff] [blame]440config EDAC_ALTERA_SDMMC
441 bool "Altera SDMMC FIFO ECC"
442 depends on EDAC_ALTERA=y && MMC_DW
443 help
444 Support for error detection and correction on the
445 Altera SDMMC FIFO Memory for Altera SoCs.
446
Punnaiah Choudary Kalluriae9b56e32015-01-06 23:13:47 +0530[diff] [blame]447config EDAC_SYNOPSYS
448 tristate "Synopsys DDR Memory Controller"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]449 depends on ARCH_ZYNQ
Punnaiah Choudary Kalluriae9b56e32015-01-06 23:13:47 +0530[diff] [blame]450 help
451 Support for error detection and correction on the Synopsys DDR
452 memory controller.
453
Loc Ho0d442932015-05-22 17:32:59 -0600[diff] [blame]454config EDAC_XGENE
455 tristate "APM X-Gene SoC"
Borislav Petkove3c4ff62017-02-03 18:18:05 +0100[diff] [blame]456 depends on (ARM64 || COMPILE_TEST)
Loc Ho0d442932015-05-22 17:32:59 -0600[diff] [blame]457 help
458 Support for error detection and correction on the
459 APM X-Gene family of SOCs.
460
Jan Engelhardt751cb5e2007-07-15 23:39:27 -0700[diff] [blame]461endif # EDAC