blob: 858fefd67ebed72dbe59cc4e07806be1b8895577 [file] [log] [blame]
David Brownell75862692005-09-23 17:14:37 -07001/*
2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
6 *
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
8 * (and others)
9 */
10
David Brownell75862692005-09-23 17:14:37 -070011#include <linux/types.h>
12#include <linux/kernel.h>
13#include <linux/pci.h>
David Brownell75862692005-09-23 17:14:37 -070014#include <linux/delay.h>
Paul Gortmakerf940fcd2011-05-27 09:56:31 -040015#include <linux/export.h>
David Brownell75862692005-09-23 17:14:37 -070016#include <linux/acpi.h>
Andy Ross3610ea52011-05-11 15:52:38 -070017#include <linux/dmi.h>
Adrian Bunk75e2df62006-03-25 18:01:53 +010018#include "pci-quirks.h"
Sarah Sharp66d4ead2009-04-27 19:52:28 -070019#include "xhci-ext-caps.h"
David Brownell75862692005-09-23 17:14:37 -070020
21
David Brownell75862692005-09-23 17:14:37 -070022#define UHCI_USBLEGSUP 0xc0 /* legacy support */
23#define UHCI_USBCMD 0 /* command register */
David Brownell75862692005-09-23 17:14:37 -070024#define UHCI_USBINTR 4 /* interrupt register */
Alan Sternbb200f62005-10-03 16:36:29 -040025#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
26#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
27#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
28#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
29#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
30#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
31#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
David Brownell75862692005-09-23 17:14:37 -070032
33#define OHCI_CONTROL 0x04
34#define OHCI_CMDSTATUS 0x08
35#define OHCI_INTRSTATUS 0x0c
36#define OHCI_INTRENABLE 0x10
37#define OHCI_INTRDISABLE 0x14
Alan Stern6ea12a02011-07-15 17:22:15 -040038#define OHCI_FMINTERVAL 0x34
Alan Sternc6187592011-11-17 16:41:45 -050039#define OHCI_HCFS (3 << 6) /* hc functional state */
Alan Stern6ea12a02011-07-15 17:22:15 -040040#define OHCI_HCR (1 << 0) /* host controller reset */
David Brownell75862692005-09-23 17:14:37 -070041#define OHCI_OCR (1 << 3) /* ownership change request */
David Brownellf2cb36c2005-09-22 22:43:30 -070042#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
David Brownell75862692005-09-23 17:14:37 -070043#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
44#define OHCI_INTR_OC (1 << 30) /* ownership change */
45
46#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
47#define EHCI_USBCMD 0 /* command register */
48#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
49#define EHCI_USBSTS 4 /* status register */
50#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
51#define EHCI_USBINTR 8 /* interrupt register */
Alan Stern4fe53542007-04-05 16:06:53 -040052#define EHCI_CONFIGFLAG 0x40 /* configured flag register */
David Brownell75862692005-09-23 17:14:37 -070053#define EHCI_USBLEGSUP 0 /* legacy support register */
54#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
55#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
56#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
57#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
58
Andiry Xuad935622011-03-01 14:57:05 +080059/* AMD quirk use */
60#define AB_REG_BAR_LOW 0xe0
61#define AB_REG_BAR_HIGH 0xe1
62#define AB_REG_BAR_SB700 0xf0
63#define AB_INDX(addr) ((addr) + 0x00)
64#define AB_DATA(addr) ((addr) + 0x04)
65#define AX_INDXC 0x30
66#define AX_DATAC 0x34
67
68#define NB_PCIE_INDX_ADDR 0xe0
69#define NB_PCIE_INDX_DATA 0xe4
70#define PCIE_P_CNTL 0x10040
71#define BIF_NB 0x10002
72#define NB_PIF0_PWRDOWN_0 0x01100012
73#define NB_PIF0_PWRDOWN_1 0x01100013
74
Sarah Sharp69e848c2011-02-22 09:57:15 -080075#define USB_INTEL_XUSB2PR 0xD0
Keng-Yu Lina96874a2012-08-10 01:39:23 +080076#define USB_INTEL_USB2PRM 0xD4
Sarah Sharp69e848c2011-02-22 09:57:15 -080077#define USB_INTEL_USB3_PSSEN 0xD8
Keng-Yu Lina96874a2012-08-10 01:39:23 +080078#define USB_INTEL_USB3PRM 0xDC
Sarah Sharp69e848c2011-02-22 09:57:15 -080079
Jiahau Chang9da5a102017-07-20 14:48:27 +030080/* ASMEDIA quirk use */
81#define ASMT_DATA_WRITE0_REG 0xF8
82#define ASMT_DATA_WRITE1_REG 0xFC
83#define ASMT_CONTROL_REG 0xE0
84#define ASMT_CONTROL_WRITE_BIT 0x02
85#define ASMT_WRITEREG_CMD 0x10423
86#define ASMT_FLOWCTL_ADDR 0xFA30
87#define ASMT_FLOWCTL_DATA 0xBA
88#define ASMT_PSEUDO_DATA 0
89
Huang Rui22b4f0c2013-09-16 23:47:27 +080090/*
91 * amd_chipset_gen values represent AMD different chipset generations
92 */
93enum amd_chipset_gen {
94 NOT_AMD_CHIPSET = 0,
95 AMD_CHIPSET_SB600,
96 AMD_CHIPSET_SB700,
97 AMD_CHIPSET_SB800,
98 AMD_CHIPSET_HUDSON2,
99 AMD_CHIPSET_BOLTON,
100 AMD_CHIPSET_YANGTZE,
101 AMD_CHIPSET_UNKNOWN,
102};
103
104struct amd_chipset_type {
105 enum amd_chipset_gen gen;
106 u8 rev;
107};
108
Andiry Xuad935622011-03-01 14:57:05 +0800109static struct amd_chipset_info {
110 struct pci_dev *nb_dev;
111 struct pci_dev *smbus_dev;
112 int nb_type;
Huang Rui22b4f0c2013-09-16 23:47:27 +0800113 struct amd_chipset_type sb_type;
Andiry Xuad935622011-03-01 14:57:05 +0800114 int isoc_reqs;
115 int probe_count;
116 int probe_result;
117} amd_chipset;
118
119static DEFINE_SPINLOCK(amd_lock);
120
Huang Rui22b4f0c2013-09-16 23:47:27 +0800121/*
122 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
123 *
124 * AMD FCH/SB generation and revision is identified by SMBus controller
125 * vendor, device and revision IDs.
126 *
127 * Returns: 1 if it is an AMD chipset, 0 otherwise.
128 */
Fengguang Wu40b3dc62013-09-26 11:56:44 -0700129static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
Huang Rui22b4f0c2013-09-16 23:47:27 +0800130{
131 u8 rev = 0;
132 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN;
133
134 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
135 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
136 if (pinfo->smbus_dev) {
137 rev = pinfo->smbus_dev->revision;
138 if (rev >= 0x10 && rev <= 0x1f)
139 pinfo->sb_type.gen = AMD_CHIPSET_SB600;
140 else if (rev >= 0x30 && rev <= 0x3f)
141 pinfo->sb_type.gen = AMD_CHIPSET_SB700;
142 else if (rev >= 0x40 && rev <= 0x4f)
143 pinfo->sb_type.gen = AMD_CHIPSET_SB800;
144 } else {
145 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
146 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
147
148 if (!pinfo->smbus_dev) {
149 pinfo->sb_type.gen = NOT_AMD_CHIPSET;
150 return 0;
151 }
152
153 rev = pinfo->smbus_dev->revision;
154 if (rev >= 0x11 && rev <= 0x14)
155 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2;
156 else if (rev >= 0x15 && rev <= 0x18)
157 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON;
158 else if (rev >= 0x39 && rev <= 0x3a)
159 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE;
160 }
161
162 pinfo->sb_type.rev = rev;
163 return 1;
164}
165
Manjunath Goudar2621d012013-05-28 18:34:50 +0530166void sb800_prefetch(struct device *dev, int on)
167{
168 u16 misc;
169 struct pci_dev *pdev = to_pci_dev(dev);
170
171 pci_read_config_word(pdev, 0x50, &misc);
172 if (on == 0)
173 pci_write_config_word(pdev, 0x50, misc & 0xfcff);
174 else
175 pci_write_config_word(pdev, 0x50, misc | 0x0300);
176}
177EXPORT_SYMBOL_GPL(sb800_prefetch);
178
Andiry Xuad935622011-03-01 14:57:05 +0800179int usb_amd_find_chipset_info(void)
180{
Andiry Xuad935622011-03-01 14:57:05 +0800181 unsigned long flags;
Joerg Roedel9ab79272011-04-13 08:38:16 +0200182 struct amd_chipset_info info;
183 int ret;
Andiry Xuad935622011-03-01 14:57:05 +0800184
185 spin_lock_irqsave(&amd_lock, flags);
186
Andiry Xuad935622011-03-01 14:57:05 +0800187 /* probe only once */
Joerg Roedel9ab79272011-04-13 08:38:16 +0200188 if (amd_chipset.probe_count > 0) {
189 amd_chipset.probe_count++;
Andiry Xuad935622011-03-01 14:57:05 +0800190 spin_unlock_irqrestore(&amd_lock, flags);
191 return amd_chipset.probe_result;
192 }
Joerg Roedel9ab79272011-04-13 08:38:16 +0200193 memset(&info, 0, sizeof(info));
194 spin_unlock_irqrestore(&amd_lock, flags);
Andiry Xuad935622011-03-01 14:57:05 +0800195
Huang Rui22b4f0c2013-09-16 23:47:27 +0800196 if (!amd_chipset_sb_type_init(&info)) {
197 ret = 0;
198 goto commit;
Andiry Xuad935622011-03-01 14:57:05 +0800199 }
200
Huang Rui22b4f0c2013-09-16 23:47:27 +0800201 /* Below chipset generations needn't enable AMD PLL quirk */
202 if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN ||
203 info.sb_type.gen == AMD_CHIPSET_SB600 ||
204 info.sb_type.gen == AMD_CHIPSET_YANGTZE ||
205 (info.sb_type.gen == AMD_CHIPSET_SB700 &&
206 info.sb_type.rev > 0x3b)) {
Joerg Roedel9ab79272011-04-13 08:38:16 +0200207 if (info.smbus_dev) {
208 pci_dev_put(info.smbus_dev);
209 info.smbus_dev = NULL;
Andiry Xuad935622011-03-01 14:57:05 +0800210 }
Joerg Roedel9ab79272011-04-13 08:38:16 +0200211 ret = 0;
212 goto commit;
Andiry Xuad935622011-03-01 14:57:05 +0800213 }
214
Joerg Roedel9ab79272011-04-13 08:38:16 +0200215 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
216 if (info.nb_dev) {
217 info.nb_type = 1;
Andiry Xuad935622011-03-01 14:57:05 +0800218 } else {
Joerg Roedel9ab79272011-04-13 08:38:16 +0200219 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
220 if (info.nb_dev) {
221 info.nb_type = 2;
222 } else {
223 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
224 0x9600, NULL);
225 if (info.nb_dev)
226 info.nb_type = 3;
Andiry Xuad935622011-03-01 14:57:05 +0800227 }
228 }
229
Joerg Roedel9ab79272011-04-13 08:38:16 +0200230 ret = info.probe_result = 1;
Andiry Xuad935622011-03-01 14:57:05 +0800231 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
232
Joerg Roedel9ab79272011-04-13 08:38:16 +0200233commit:
234
235 spin_lock_irqsave(&amd_lock, flags);
236 if (amd_chipset.probe_count > 0) {
237 /* race - someone else was faster - drop devices */
238
239 /* Mark that we where here */
240 amd_chipset.probe_count++;
241 ret = amd_chipset.probe_result;
242
243 spin_unlock_irqrestore(&amd_lock, flags);
244
Markus Elfringf910b6c2014-11-21 15:20:12 +0100245 pci_dev_put(info.nb_dev);
246 pci_dev_put(info.smbus_dev);
Joerg Roedel9ab79272011-04-13 08:38:16 +0200247
248 } else {
249 /* no race - commit the result */
250 info.probe_count++;
251 amd_chipset = info;
252 spin_unlock_irqrestore(&amd_lock, flags);
253 }
254
255 return ret;
Andiry Xuad935622011-03-01 14:57:05 +0800256}
257EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
258
Huang Rui78689432013-09-16 23:47:28 +0800259int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
260{
261 /* Make sure amd chipset type has already been initialized */
262 usb_amd_find_chipset_info();
263 if (amd_chipset.sb_type.gen != AMD_CHIPSET_YANGTZE)
264 return 0;
265
266 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
267 return 1;
268}
269EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
270
Huang Rui3ad145b2013-10-03 23:37:12 +0800271bool usb_amd_hang_symptom_quirk(void)
272{
273 u8 rev;
274
275 usb_amd_find_chipset_info();
276 rev = amd_chipset.sb_type.rev;
277 /* SB600 and old version of SB700 have hang symptom bug */
278 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 ||
279 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
280 rev >= 0x3a && rev <= 0x3b);
281}
282EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk);
283
Huang Rui02c123e2013-10-03 23:37:13 +0800284bool usb_amd_prefetch_quirk(void)
285{
286 usb_amd_find_chipset_info();
287 /* SB800 needs pre-fetch fix */
288 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800;
289}
290EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk);
291
Andiry Xuad935622011-03-01 14:57:05 +0800292/*
293 * The hardware normally enables the A-link power management feature, which
294 * lets the system lower the power consumption in idle states.
295 *
296 * This USB quirk prevents the link going into that lower power state
297 * during isochronous transfers.
298 *
299 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
300 * some AMD platforms may stutter or have breaks occasionally.
301 */
302static void usb_amd_quirk_pll(int disable)
303{
304 u32 addr, addr_low, addr_high, val;
305 u32 bit = disable ? 0 : 1;
306 unsigned long flags;
307
308 spin_lock_irqsave(&amd_lock, flags);
309
310 if (disable) {
311 amd_chipset.isoc_reqs++;
312 if (amd_chipset.isoc_reqs > 1) {
313 spin_unlock_irqrestore(&amd_lock, flags);
314 return;
315 }
316 } else {
317 amd_chipset.isoc_reqs--;
318 if (amd_chipset.isoc_reqs > 0) {
319 spin_unlock_irqrestore(&amd_lock, flags);
320 return;
321 }
322 }
323
Huang Rui22b4f0c2013-09-16 23:47:27 +0800324 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 ||
325 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 ||
326 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) {
Andiry Xuad935622011-03-01 14:57:05 +0800327 outb_p(AB_REG_BAR_LOW, 0xcd6);
328 addr_low = inb_p(0xcd7);
329 outb_p(AB_REG_BAR_HIGH, 0xcd6);
330 addr_high = inb_p(0xcd7);
331 addr = addr_high << 8 | addr_low;
332
333 outl_p(0x30, AB_INDX(addr));
334 outl_p(0x40, AB_DATA(addr));
335 outl_p(0x34, AB_INDX(addr));
336 val = inl_p(AB_DATA(addr));
Huang Rui22b4f0c2013-09-16 23:47:27 +0800337 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
338 amd_chipset.sb_type.rev <= 0x3b) {
Andiry Xuad935622011-03-01 14:57:05 +0800339 pci_read_config_dword(amd_chipset.smbus_dev,
340 AB_REG_BAR_SB700, &addr);
341 outl(AX_INDXC, AB_INDX(addr));
342 outl(0x40, AB_DATA(addr));
343 outl(AX_DATAC, AB_INDX(addr));
344 val = inl(AB_DATA(addr));
345 } else {
346 spin_unlock_irqrestore(&amd_lock, flags);
347 return;
348 }
349
350 if (disable) {
351 val &= ~0x08;
352 val |= (1 << 4) | (1 << 9);
353 } else {
354 val |= 0x08;
355 val &= ~((1 << 4) | (1 << 9));
356 }
357 outl_p(val, AB_DATA(addr));
358
359 if (!amd_chipset.nb_dev) {
360 spin_unlock_irqrestore(&amd_lock, flags);
361 return;
362 }
363
364 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
365 addr = PCIE_P_CNTL;
366 pci_write_config_dword(amd_chipset.nb_dev,
367 NB_PCIE_INDX_ADDR, addr);
368 pci_read_config_dword(amd_chipset.nb_dev,
369 NB_PCIE_INDX_DATA, &val);
370
371 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
372 val |= bit | (bit << 3) | (bit << 12);
373 val |= ((!bit) << 4) | ((!bit) << 9);
374 pci_write_config_dword(amd_chipset.nb_dev,
375 NB_PCIE_INDX_DATA, val);
376
377 addr = BIF_NB;
378 pci_write_config_dword(amd_chipset.nb_dev,
379 NB_PCIE_INDX_ADDR, addr);
380 pci_read_config_dword(amd_chipset.nb_dev,
381 NB_PCIE_INDX_DATA, &val);
382 val &= ~(1 << 8);
383 val |= bit << 8;
384
385 pci_write_config_dword(amd_chipset.nb_dev,
386 NB_PCIE_INDX_DATA, val);
387 } else if (amd_chipset.nb_type == 2) {
388 addr = NB_PIF0_PWRDOWN_0;
389 pci_write_config_dword(amd_chipset.nb_dev,
390 NB_PCIE_INDX_ADDR, addr);
391 pci_read_config_dword(amd_chipset.nb_dev,
392 NB_PCIE_INDX_DATA, &val);
393 if (disable)
394 val &= ~(0x3f << 7);
395 else
396 val |= 0x3f << 7;
397
398 pci_write_config_dword(amd_chipset.nb_dev,
399 NB_PCIE_INDX_DATA, val);
400
401 addr = NB_PIF0_PWRDOWN_1;
402 pci_write_config_dword(amd_chipset.nb_dev,
403 NB_PCIE_INDX_ADDR, addr);
404 pci_read_config_dword(amd_chipset.nb_dev,
405 NB_PCIE_INDX_DATA, &val);
406 if (disable)
407 val &= ~(0x3f << 7);
408 else
409 val |= 0x3f << 7;
410
411 pci_write_config_dword(amd_chipset.nb_dev,
412 NB_PCIE_INDX_DATA, val);
413 }
414
415 spin_unlock_irqrestore(&amd_lock, flags);
416 return;
417}
418
419void usb_amd_quirk_pll_disable(void)
420{
421 usb_amd_quirk_pll(1);
422}
423EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
424
Jiahau Chang9da5a102017-07-20 14:48:27 +0300425static int usb_asmedia_wait_write(struct pci_dev *pdev)
426{
427 unsigned long retry_count;
428 unsigned char value;
429
430 for (retry_count = 1000; retry_count > 0; --retry_count) {
431
432 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
433
434 if (value == 0xff) {
435 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
436 return -EIO;
437 }
438
439 if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
440 return 0;
441
442 usleep_range(40, 60);
443 }
444
445 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
446 return -ETIMEDOUT;
447}
448
449void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
450{
451 if (usb_asmedia_wait_write(pdev) != 0)
452 return;
453
454 /* send command and address to device */
455 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
456 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
457 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
458
459 if (usb_asmedia_wait_write(pdev) != 0)
460 return;
461
462 /* send data to device */
463 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
464 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
465 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
466}
467EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
468
Andiry Xuad935622011-03-01 14:57:05 +0800469void usb_amd_quirk_pll_enable(void)
470{
471 usb_amd_quirk_pll(0);
472}
473EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
474
475void usb_amd_dev_put(void)
476{
Joerg Roedel9ab79272011-04-13 08:38:16 +0200477 struct pci_dev *nb, *smbus;
Andiry Xuad935622011-03-01 14:57:05 +0800478 unsigned long flags;
479
480 spin_lock_irqsave(&amd_lock, flags);
481
482 amd_chipset.probe_count--;
483 if (amd_chipset.probe_count > 0) {
484 spin_unlock_irqrestore(&amd_lock, flags);
485 return;
486 }
487
Joerg Roedel9ab79272011-04-13 08:38:16 +0200488 /* save them to pci_dev_put outside of spinlock */
489 nb = amd_chipset.nb_dev;
490 smbus = amd_chipset.smbus_dev;
491
492 amd_chipset.nb_dev = NULL;
493 amd_chipset.smbus_dev = NULL;
Andiry Xuad935622011-03-01 14:57:05 +0800494 amd_chipset.nb_type = 0;
Huang Rui22b4f0c2013-09-16 23:47:27 +0800495 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
Andiry Xuad935622011-03-01 14:57:05 +0800496 amd_chipset.isoc_reqs = 0;
497 amd_chipset.probe_result = 0;
498
499 spin_unlock_irqrestore(&amd_lock, flags);
Joerg Roedel9ab79272011-04-13 08:38:16 +0200500
Markus Elfringf910b6c2014-11-21 15:20:12 +0100501 pci_dev_put(nb);
502 pci_dev_put(smbus);
Andiry Xuad935622011-03-01 14:57:05 +0800503}
504EXPORT_SYMBOL_GPL(usb_amd_dev_put);
David Brownell75862692005-09-23 17:14:37 -0700505
Alan Sternbb200f62005-10-03 16:36:29 -0400506/*
507 * Make sure the controller is completely inactive, unable to
508 * generate interrupts or do DMA.
509 */
510void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
511{
512 /* Turn off PIRQ enable and SMI enable. (This also turns off the
513 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
514 */
515 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
516
517 /* Reset the HC - this will force us to get a
518 * new notification of any already connected
519 * ports due to the virtual disconnect that it
520 * implies.
521 */
522 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
523 mb();
524 udelay(5);
525 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
526 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
527
528 /* Just to be safe, disable interrupt requests and
529 * make sure the controller is stopped.
530 */
531 outw(0, base + UHCI_USBINTR);
532 outw(0, base + UHCI_USBCMD);
533}
534EXPORT_SYMBOL_GPL(uhci_reset_hc);
535
536/*
537 * Initialize a controller that was newly discovered or has just been
538 * resumed. In either case we can't be sure of its previous state.
539 *
540 * Returns: 1 if the controller was reset, 0 otherwise.
541 */
542int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
543{
544 u16 legsup;
545 unsigned int cmd, intr;
546
547 /*
548 * When restarting a suspended controller, we expect all the
549 * settings to be the same as we left them:
550 *
551 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
552 * Controller is stopped and configured with EGSM set;
553 * No interrupts enabled except possibly Resume Detect.
554 *
555 * If any of these conditions are violated we do a complete reset.
556 */
557 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
558 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
559 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
Harvey Harrison441b62c2008-03-03 16:08:34 -0800560 __func__, legsup);
Alan Sternbb200f62005-10-03 16:36:29 -0400561 goto reset_needed;
562 }
563
564 cmd = inw(base + UHCI_USBCMD);
565 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
566 !(cmd & UHCI_USBCMD_EGSM)) {
567 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
Harvey Harrison441b62c2008-03-03 16:08:34 -0800568 __func__, cmd);
Alan Sternbb200f62005-10-03 16:36:29 -0400569 goto reset_needed;
570 }
571
572 intr = inw(base + UHCI_USBINTR);
573 if (intr & (~UHCI_USBINTR_RESUME)) {
574 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
Harvey Harrison441b62c2008-03-03 16:08:34 -0800575 __func__, intr);
Alan Sternbb200f62005-10-03 16:36:29 -0400576 goto reset_needed;
577 }
578 return 0;
579
580reset_needed:
581 dev_dbg(&pdev->dev, "Performing full reset\n");
582 uhci_reset_hc(pdev, base);
583 return 1;
584}
585EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
586
Linus Torvalds541ab4a2005-10-31 21:12:40 -0800587static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
588{
589 u16 cmd;
590 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
591}
592
593#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
594#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
595
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500596static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
David Brownell75862692005-09-23 17:14:37 -0700597{
598 unsigned long base = 0;
David Brownell75862692005-09-23 17:14:37 -0700599 int i;
600
Linus Torvalds541ab4a2005-10-31 21:12:40 -0800601 if (!pio_enabled(pdev))
602 return;
603
David Brownell75862692005-09-23 17:14:37 -0700604 for (i = 0; i < PCI_ROM_RESOURCE; i++)
605 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
606 base = pci_resource_start(pdev, i);
607 break;
608 }
609
Alan Sternbb200f62005-10-03 16:36:29 -0400610 if (base)
611 uhci_check_and_reset_hc(pdev, base);
David Brownell75862692005-09-23 17:14:37 -0700612}
613
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500614static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
Linus Torvalds541ab4a2005-10-31 21:12:40 -0800615{
616 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
617}
618
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500619static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
David Brownell75862692005-09-23 17:14:37 -0700620{
621 void __iomem *base;
Alan Stern3df71692010-09-10 16:37:05 -0400622 u32 control;
Arseny Solokha56abcab2014-12-06 09:54:06 +0700623 u32 fminterval = 0;
624 bool no_fminterval = false;
Alan Sternc6187592011-11-17 16:41:45 -0500625 int cnt;
David Brownell75862692005-09-23 17:14:37 -0700626
Linus Torvalds541ab4a2005-10-31 21:12:40 -0800627 if (!mmio_resource_enabled(pdev, 0))
628 return;
629
Arjan van de Ven8e8ce4b2008-10-20 21:46:01 -0700630 base = pci_ioremap_bar(pdev, 0);
631 if (base == NULL)
632 return;
David Brownell75862692005-09-23 17:14:37 -0700633
Arseny Solokha56abcab2014-12-06 09:54:06 +0700634 /*
635 * ULi M5237 OHCI controller locks the whole system when accessing
636 * the OHCI_FMINTERVAL offset.
637 */
638 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)
639 no_fminterval = true;
640
Alan Stern3df71692010-09-10 16:37:05 -0400641 control = readl(base + OHCI_CONTROL);
642
David Brownellf2cb36c2005-09-22 22:43:30 -0700643/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
Alan Stern3df71692010-09-10 16:37:05 -0400644#ifdef __hppa__
645#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
646#else
647#define OHCI_CTRL_MASK OHCI_CTRL_RWC
648
David Brownellf2cb36c2005-09-22 22:43:30 -0700649 if (control & OHCI_CTRL_IR) {
Kyle McMartinc1b45f22006-06-25 18:45:29 -0400650 int wait_time = 500; /* arbitrary; 5 seconds */
David Brownell75862692005-09-23 17:14:37 -0700651 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
652 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
653 while (wait_time > 0 &&
654 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
655 wait_time -= 10;
656 msleep(10);
657 }
David Brownellf2cb36c2005-09-22 22:43:30 -0700658 if (wait_time <= 0)
Andy Shevchenkoe307ff02015-01-29 12:35:19 +0200659 dev_warn(&pdev->dev,
660 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n",
661 readl(base + OHCI_CONTROL));
David Brownell75862692005-09-23 17:14:37 -0700662 }
David Brownellf2cb36c2005-09-22 22:43:30 -0700663#endif
David Brownell75862692005-09-23 17:14:37 -0700664
Alan Sternc6187592011-11-17 16:41:45 -0500665 /* disable interrupts */
666 writel((u32) ~0, base + OHCI_INTRDISABLE);
Alan Stern6ea12a02011-07-15 17:22:15 -0400667
Alan Sternc6187592011-11-17 16:41:45 -0500668 /* Reset the USB bus, if the controller isn't already in RESET */
669 if (control & OHCI_HCFS) {
670 /* Go into RESET, preserving RWC (and possibly IR) */
671 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
672 readl(base + OHCI_CONTROL);
Alan Stern6ea12a02011-07-15 17:22:15 -0400673
Alan Sternc6187592011-11-17 16:41:45 -0500674 /* drive bus reset for at least 50 ms (7.1.7.5) */
Alan Stern6ea12a02011-07-15 17:22:15 -0400675 msleep(50);
Alan Stern6ea12a02011-07-15 17:22:15 -0400676 }
Alan Stern3df71692010-09-10 16:37:05 -0400677
Alan Sternc6187592011-11-17 16:41:45 -0500678 /* software reset of the controller, preserving HcFmInterval */
Arseny Solokha56abcab2014-12-06 09:54:06 +0700679 if (!no_fminterval)
680 fminterval = readl(base + OHCI_FMINTERVAL);
681
Alan Sternc6187592011-11-17 16:41:45 -0500682 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
David Brownell75862692005-09-23 17:14:37 -0700683
Alan Sternc6187592011-11-17 16:41:45 -0500684 /* reset requires max 10 us delay */
685 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */
686 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
687 break;
688 udelay(1);
689 }
Arseny Solokha56abcab2014-12-06 09:54:06 +0700690
691 if (!no_fminterval)
692 writel(fminterval, base + OHCI_FMINTERVAL);
Alan Sternc6187592011-11-17 16:41:45 -0500693
694 /* Now the controller is safely in SUSPEND and nothing can wake it up */
David Brownell75862692005-09-23 17:14:37 -0700695 iounmap(base);
696}
697
Bill Pemberton2f826862012-11-19 13:25:20 -0500698static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
Anisse Astier03c75362011-07-05 16:38:45 +0200699 {
700 /* Pegatron Lucid (ExoPC) */
701 .matches = {
702 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
703 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
704 },
705 },
Anisse Astier0c42a4e2011-07-05 16:38:46 +0200706 {
707 /* Pegatron Lucid (Ordissimo AIRIS) */
708 .matches = {
709 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
Anisse Astierc323dc02012-10-09 12:22:36 +0200710 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
Anisse Astier0c42a4e2011-07-05 16:38:46 +0200711 },
712 },
Anisse Astier8daf8b62012-10-09 12:22:37 +0200713 {
714 /* Pegatron Lucid (Ordissimo) */
715 .matches = {
716 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
717 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
718 },
719 },
Alan Sternb0a50e92014-06-03 11:00:27 -0400720 {
721 /* HASEE E200 */
722 .matches = {
723 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"),
724 DMI_MATCH(DMI_BOARD_NAME, "E210"),
725 DMI_MATCH(DMI_BIOS_VERSION, "6.00"),
726 },
727 },
Anisse Astier03c75362011-07-05 16:38:45 +0200728 { }
729};
730
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500731static void ehci_bios_handoff(struct pci_dev *pdev,
Andy Ross5c853012011-05-11 15:15:51 -0700732 void __iomem *op_reg_base,
733 u32 cap, u8 offset)
734{
Andy Ross3610ea52011-05-11 15:52:38 -0700735 int try_handoff = 1, tried_handoff = 0;
Andy Ross5c853012011-05-11 15:15:51 -0700736
Alan Sternb0a50e92014-06-03 11:00:27 -0400737 /*
738 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying
739 * the handoff on its unused controller. Skip it.
740 *
741 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021).
742 */
743 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a ||
744 pdev->device == 0x27cc)) {
Anisse Astier03c75362011-07-05 16:38:45 +0200745 if (dmi_check_system(ehci_dmi_nohandoff_table))
Andy Ross3610ea52011-05-11 15:52:38 -0700746 try_handoff = 0;
747 }
748
749 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
Andy Ross5c853012011-05-11 15:15:51 -0700750 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
751
752#if 0
753/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
754 * but that seems dubious in general (the BIOS left it off intentionally)
755 * and is known to prevent some systems from booting. so we won't do this
756 * unless maybe we can determine when we're on a system that needs SMI forced.
757 */
758 /* BIOS workaround (?): be sure the pre-Linux code
759 * receives the SMI
760 */
761 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
762 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
763 val | EHCI_USBLEGCTLSTS_SOOE);
764#endif
765
766 /* some systems get upset if this semaphore is
767 * set for any other reason than forcing a BIOS
768 * handoff..
769 */
770 pci_write_config_byte(pdev, offset + 3, 1);
771 }
772
773 /* if boot firmware now owns EHCI, spin till it hands it over. */
Andy Ross3610ea52011-05-11 15:52:38 -0700774 if (try_handoff) {
775 int msec = 1000;
776 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
777 tried_handoff = 1;
778 msleep(10);
779 msec -= 10;
780 pci_read_config_dword(pdev, offset, &cap);
781 }
Andy Ross5c853012011-05-11 15:15:51 -0700782 }
783
784 if (cap & EHCI_USBLEGSUP_BIOS) {
785 /* well, possibly buggy BIOS... try to shut it down,
786 * and hope nothing goes too wrong
787 */
Andy Ross3610ea52011-05-11 15:52:38 -0700788 if (try_handoff)
Andy Shevchenkoe307ff02015-01-29 12:35:19 +0200789 dev_warn(&pdev->dev,
790 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n",
791 cap);
Andy Ross5c853012011-05-11 15:15:51 -0700792 pci_write_config_byte(pdev, offset + 2, 0);
793 }
794
795 /* just in case, always disable EHCI SMIs */
796 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
797
798 /* If the BIOS ever owned the controller then we can't expect
799 * any power sessions to remain intact.
800 */
801 if (tried_handoff)
802 writel(0, op_reg_base + EHCI_CONFIGFLAG);
803}
804
Bill Pemberton41ac7b32012-11-19 13:21:48 -0500805static void quirk_usb_disable_ehci(struct pci_dev *pdev)
David Brownell75862692005-09-23 17:14:37 -0700806{
David Brownell75862692005-09-23 17:14:37 -0700807 void __iomem *base, *op_reg_base;
Andy Ross5c853012011-05-11 15:15:51 -0700808 u32 hcc_params, cap, val;
David Brownell401feaf2006-01-24 07:15:30 -0800809 u8 offset, cap_length;
Alan Stern97ff22e2011-10-27 11:20:21 -0400810 int wait_time, count = 256/4;
David Brownell75862692005-09-23 17:14:37 -0700811
Linus Torvalds541ab4a2005-10-31 21:12:40 -0800812 if (!mmio_resource_enabled(pdev, 0))
813 return;
814
Arjan van de Ven8e8ce4b2008-10-20 21:46:01 -0700815 base = pci_ioremap_bar(pdev, 0);
816 if (base == NULL)
817 return;
David Brownell75862692005-09-23 17:14:37 -0700818
819 cap_length = readb(base);
820 op_reg_base = base + cap_length;
David Brownell75862692005-09-23 17:14:37 -0700821
David Brownell401feaf2006-01-24 07:15:30 -0800822 /* EHCI 0.96 and later may have "extended capabilities"
823 * spec section 5.1 explains the bios handoff, e.g. for
824 * booting from USB disk or using a usb keyboard
825 */
826 hcc_params = readl(base + EHCI_HCC_PARAMS);
827 offset = (hcc_params >> 8) & 0xff;
Roel Kluin6e14bda2009-01-31 12:37:04 +0100828 while (offset && --count) {
David Brownell401feaf2006-01-24 07:15:30 -0800829 pci_read_config_dword(pdev, offset, &cap);
Andy Ross5c853012011-05-11 15:15:51 -0700830
David Brownell401feaf2006-01-24 07:15:30 -0800831 switch (cap & 0xff) {
Andy Ross5c853012011-05-11 15:15:51 -0700832 case 1:
833 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
David Brownell401feaf2006-01-24 07:15:30 -0800834 break;
Andy Ross5c853012011-05-11 15:15:51 -0700835 case 0: /* Illegal reserved cap, set cap=0 so we exit */
836 cap = 0; /* then fallthrough... */
David Brownell401feaf2006-01-24 07:15:30 -0800837 default:
Andy Shevchenkoe307ff02015-01-29 12:35:19 +0200838 dev_warn(&pdev->dev,
839 "EHCI: unrecognized capability %02x\n",
840 cap & 0xff);
David Brownell75862692005-09-23 17:14:37 -0700841 }
David Brownell401feaf2006-01-24 07:15:30 -0800842 offset = (cap >> 8) & 0xff;
David Brownell75862692005-09-23 17:14:37 -0700843 }
David Brownell401feaf2006-01-24 07:15:30 -0800844 if (!count)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700845 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
David Brownell75862692005-09-23 17:14:37 -0700846
847 /*
848 * halt EHCI & disable its interrupts in any case
849 */
850 val = readl(op_reg_base + EHCI_USBSTS);
851 if ((val & EHCI_USBSTS_HALTED) == 0) {
852 val = readl(op_reg_base + EHCI_USBCMD);
853 val &= ~EHCI_USBCMD_RUN;
854 writel(val, op_reg_base + EHCI_USBCMD);
855
856 wait_time = 2000;
David Brownell75862692005-09-23 17:14:37 -0700857 do {
858 writel(0x3f, op_reg_base + EHCI_USBSTS);
Alan Stern97ff22e2011-10-27 11:20:21 -0400859 udelay(100);
860 wait_time -= 100;
David Brownell75862692005-09-23 17:14:37 -0700861 val = readl(op_reg_base + EHCI_USBSTS);
862 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
863 break;
864 }
865 } while (wait_time > 0);
866 }
867 writel(0, op_reg_base + EHCI_USBINTR);
868 writel(0x3f, op_reg_base + EHCI_USBSTS);
869
870 iounmap(base);
David Brownell75862692005-09-23 17:14:37 -0700871}
872
Sarah Sharp66d4ead2009-04-27 19:52:28 -0700873/*
874 * handshake - spin reading a register until handshake completes
875 * @ptr: address of hc register to be read
876 * @mask: bits to look at in result of read
877 * @done: value of those bits when handshake succeeds
878 * @wait_usec: timeout in microseconds
879 * @delay_usec: delay in microseconds to wait between polling
880 *
881 * Polls a register every delay_usec microseconds.
882 * Returns 0 when the mask bits have the value done.
883 * Returns -ETIMEDOUT if this condition is not true after
884 * wait_usec microseconds have passed.
885 */
886static int handshake(void __iomem *ptr, u32 mask, u32 done,
887 int wait_usec, int delay_usec)
888{
889 u32 result;
David Brownell75862692005-09-23 17:14:37 -0700890
Sarah Sharp66d4ead2009-04-27 19:52:28 -0700891 do {
892 result = readl(ptr);
893 result &= mask;
894 if (result == done)
895 return 0;
896 udelay(delay_usec);
897 wait_usec -= delay_usec;
898 } while (wait_usec > 0);
899 return -ETIMEDOUT;
900}
901
Sarah Sharp69e848c2011-02-22 09:57:15 -0800902/*
903 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
904 * share some number of ports. These ports can be switched between either
905 * controller. Not all of the ports under the EHCI host controller may be
906 * switchable.
907 *
908 * The ports should be switched over to xHCI before PCI probes for any device
909 * start. This avoids active devices under EHCI being disconnected during the
910 * port switchover, which could cause loss of data on USB storage devices, or
911 * failed boot when the root file system is on a USB mass storage device and is
912 * enumerated under EHCI first.
913 *
914 * We write into the xHC's PCI configuration space in some Intel-specific
915 * registers to switch the ports over. The USB 3.0 terminations and the USB
916 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
917 * terminations before switching the USB 2.0 wires over, so that USB 3.0
918 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
919 */
Mathias Nyman26b76792013-07-23 11:35:47 +0300920void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
Sarah Sharp69e848c2011-02-22 09:57:15 -0800921{
922 u32 ports_available;
Mathias Nyman26b76792013-07-23 11:35:47 +0300923 bool ehci_found = false;
924 struct pci_dev *companion = NULL;
925
Mathias Nymanb38f09c2014-05-28 23:18:35 +0300926 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of
927 * switching ports from EHCI to xHCI
928 */
929 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY &&
930 xhci_pdev->subsystem_device == 0x90a8)
931 return;
932
Mathias Nyman26b76792013-07-23 11:35:47 +0300933 /* make sure an intel EHCI controller exists */
934 for_each_pci_dev(companion) {
935 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
936 companion->vendor == PCI_VENDOR_ID_INTEL) {
937 ehci_found = true;
938 break;
939 }
940 }
941
942 if (!ehci_found)
943 return;
Sarah Sharp69e848c2011-02-22 09:57:15 -0800944
Sarah Sharp51c9e6c2012-04-16 10:56:47 -0700945 /* Don't switchover the ports if the user hasn't compiled the xHCI
946 * driver. Otherwise they will see "dead" USB ports that don't power
947 * the devices.
948 */
949 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
950 dev_warn(&xhci_pdev->dev,
Andy Shevchenkoe307ff02015-01-29 12:35:19 +0200951 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n");
Sarah Sharp51c9e6c2012-04-16 10:56:47 -0700952 dev_warn(&xhci_pdev->dev,
953 "USB 3.0 devices will work at USB 2.0 speeds.\n");
David Moore58b29392013-01-23 22:19:49 -0800954 usb_disable_xhci_ports(xhci_pdev);
Sarah Sharp51c9e6c2012-04-16 10:56:47 -0700955 return;
956 }
957
Keng-Yu Lina96874a2012-08-10 01:39:23 +0800958 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
959 * Indicate the ports that can be changed from OS.
960 */
961 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
962 &ports_available);
963
964 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
965 ports_available);
966
Sarah Sharp69e848c2011-02-22 09:57:15 -0800967 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
Keng-Yu Lina96874a2012-08-10 01:39:23 +0800968 * Register, to turn on SuperSpeed terminations for the
969 * switchable ports.
Sarah Sharp69e848c2011-02-22 09:57:15 -0800970 */
971 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
Xenia Ragiadakoue4599332013-09-20 19:45:53 +0300972 ports_available);
Sarah Sharp69e848c2011-02-22 09:57:15 -0800973
974 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
975 &ports_available);
Andy Shevchenkoe307ff02015-01-29 12:35:19 +0200976 dev_dbg(&xhci_pdev->dev,
977 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n",
978 ports_available);
Sarah Sharp69e848c2011-02-22 09:57:15 -0800979
Keng-Yu Lina96874a2012-08-10 01:39:23 +0800980 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
981 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
982 */
983
984 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
985 &ports_available);
986
987 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
988 ports_available);
989
Sarah Sharp69e848c2011-02-22 09:57:15 -0800990 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
991 * switch the USB 2.0 power and data lines over to the xHCI
992 * host.
993 */
994 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
Xenia Ragiadakoue4599332013-09-20 19:45:53 +0300995 ports_available);
Sarah Sharp69e848c2011-02-22 09:57:15 -0800996
997 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
998 &ports_available);
Andy Shevchenkoe307ff02015-01-29 12:35:19 +0200999 dev_dbg(&xhci_pdev->dev,
1000 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n",
1001 ports_available);
Sarah Sharp69e848c2011-02-22 09:57:15 -08001002}
Mathias Nyman26b76792013-07-23 11:35:47 +03001003EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
Sarah Sharp69e848c2011-02-22 09:57:15 -08001004
Sarah Sharpe95829f2012-07-23 18:59:30 +03001005void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
1006{
1007 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
1008 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
1009}
1010EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
1011
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001012/**
1013 * PCI Quirks for xHCI.
1014 *
1015 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
1016 * It signals to the BIOS that the OS wants control of the host controller,
1017 * and then waits 5 seconds for the BIOS to hand over control.
1018 * If we timeout, assume the BIOS is broken and take control anyway.
1019 */
Bill Pemberton41ac7b32012-11-19 13:21:48 -05001020static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001021{
1022 void __iomem *base;
1023 int ext_cap_offset;
1024 void __iomem *op_reg_base;
1025 u32 val;
1026 int timeout;
Matthew Garrette955a1c2012-08-14 16:44:49 -04001027 int len = pci_resource_len(pdev, 0);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001028
1029 if (!mmio_resource_enabled(pdev, 0))
1030 return;
1031
Matthew Garrette955a1c2012-08-14 16:44:49 -04001032 base = ioremap_nocache(pci_resource_start(pdev, 0), len);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001033 if (base == NULL)
1034 return;
1035
1036 /*
1037 * Find the Legacy Support Capability register -
1038 * this is optional for xHCI host controllers.
1039 */
Mathias Nymand5ddcdf2015-11-24 13:09:58 +02001040 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY);
Matthew Garrette955a1c2012-08-14 16:44:49 -04001041
Mathias Nymand5ddcdf2015-11-24 13:09:58 +02001042 if (!ext_cap_offset)
1043 goto hc_init;
Matthew Garrette955a1c2012-08-14 16:44:49 -04001044
Mathias Nymand5ddcdf2015-11-24 13:09:58 +02001045 if ((ext_cap_offset + sizeof(val)) > len) {
1046 /* We're reading garbage from the controller */
1047 dev_warn(&pdev->dev, "xHCI controller failing to respond");
Saurabh Sengaracc27b62016-02-11 15:12:06 +05301048 goto iounmap;
Mathias Nymand5ddcdf2015-11-24 13:09:58 +02001049 }
1050 val = readl(base + ext_cap_offset);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001051
Babu Mogerc289d0e2016-10-21 15:25:05 -07001052 /* Auto handoff never worked for these devices. Force it and continue */
1053 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ||
1054 (pdev->vendor == PCI_VENDOR_ID_RENESAS
1055 && pdev->device == 0x0014)) {
1056 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED;
1057 writel(val, base + ext_cap_offset);
1058 }
1059
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001060 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
1061 if (val & XHCI_HC_BIOS_OWNED) {
JiSheng Zhang67684582011-07-16 11:04:19 +08001062 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001063
1064 /* Wait for 5 seconds with 10 microsecond polling interval */
1065 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
1066 0, 5000, 10);
1067
1068 /* Assume a buggy BIOS and take HC ownership anyway */
1069 if (timeout) {
Andy Shevchenkoe307ff02015-01-29 12:35:19 +02001070 dev_warn(&pdev->dev,
1071 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n",
1072 val);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001073 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
1074 }
1075 }
1076
Alex He95018a52012-03-30 10:21:38 +08001077 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1078 /* Mask off (turn off) any enabled SMIs */
1079 val &= XHCI_LEGACY_DISABLE_SMI;
1080 /* Mask all SMI events bits, RW1C */
1081 val |= XHCI_LEGACY_SMI_EVENTS;
1082 /* Disable any BIOS SMIs and clear all SMI events*/
1083 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001084
Manoj Iyer29d21452012-08-22 11:53:18 -05001085hc_init:
Mathias Nyman26b76792013-07-23 11:35:47 +03001086 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
1087 usb_enable_intel_xhci_ports(pdev);
Manoj Iyer29d21452012-08-22 11:53:18 -05001088
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001089 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
1090
1091 /* Wait for the host controller to be ready before writing any
1092 * operational or runtime registers. Wait 5 seconds and no more.
1093 */
1094 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
1095 5000, 10);
1096 /* Assume a buggy HC and start HC initialization anyway */
1097 if (timeout) {
1098 val = readl(op_reg_base + XHCI_STS_OFFSET);
1099 dev_warn(&pdev->dev,
Andy Shevchenkoe307ff02015-01-29 12:35:19 +02001100 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",
1101 val);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001102 }
1103
1104 /* Send the halt and disable interrupts command */
1105 val = readl(op_reg_base + XHCI_CMD_OFFSET);
1106 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
1107 writel(val, op_reg_base + XHCI_CMD_OFFSET);
1108
1109 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
1110 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
1111 XHCI_MAX_HALT_USEC, 125);
1112 if (timeout) {
1113 val = readl(op_reg_base + XHCI_STS_OFFSET);
1114 dev_warn(&pdev->dev,
Andy Shevchenkoe307ff02015-01-29 12:35:19 +02001115 "xHCI HW did not halt within %d usec status = 0x%x\n",
1116 XHCI_MAX_HALT_USEC, val);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001117 }
1118
Saurabh Sengaracc27b62016-02-11 15:12:06 +05301119iounmap:
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001120 iounmap(base);
1121}
David Brownell75862692005-09-23 17:14:37 -07001122
Bill Pemberton41ac7b32012-11-19 13:21:48 -05001123static void quirk_usb_early_handoff(struct pci_dev *pdev)
David Brownell75862692005-09-23 17:14:37 -07001124{
Jayachandran Ce4436a72012-01-27 20:27:32 +05301125 /* Skip Netlogic mips SoC's internal PCI USB controller.
1126 * This device does not need/support EHCI/OHCI handoff
1127 */
1128 if (pdev->vendor == 0x184e) /* vendor Netlogic */
1129 return;
Sarah Sharpcab928ee2012-02-07 15:11:46 -08001130 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
1131 pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
1132 pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
1133 pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
1134 return;
Jayachandran Ce4436a72012-01-27 20:27:32 +05301135
Sarah Sharpcab928ee2012-02-07 15:11:46 -08001136 if (pci_enable_device(pdev) < 0) {
Andy Shevchenkoe307ff02015-01-29 12:35:19 +02001137 dev_warn(&pdev->dev,
1138 "Can't enable PCI device, BIOS handoff failed.\n");
Sarah Sharpcab928ee2012-02-07 15:11:46 -08001139 return;
1140 }
Alan Stern478a3ba2005-10-19 12:52:02 -04001141 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
David Brownell75862692005-09-23 17:14:37 -07001142 quirk_usb_handoff_uhci(pdev);
Alan Stern478a3ba2005-10-19 12:52:02 -04001143 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
David Brownell75862692005-09-23 17:14:37 -07001144 quirk_usb_handoff_ohci(pdev);
Alan Stern478a3ba2005-10-19 12:52:02 -04001145 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
David Brownell75862692005-09-23 17:14:37 -07001146 quirk_usb_disable_ehci(pdev);
Sarah Sharp66d4ead2009-04-27 19:52:28 -07001147 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
1148 quirk_usb_handoff_xhci(pdev);
Sarah Sharpcab928ee2012-02-07 15:11:46 -08001149 pci_disable_device(pdev);
David Brownell75862692005-09-23 17:14:37 -07001150}
Yinghai Lu8474ecd2012-02-23 23:46:59 -08001151DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1152 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
Marc Zyngier84664892017-08-01 20:11:08 -05001153
1154bool usb_xhci_needs_pci_reset(struct pci_dev *pdev)
1155{
1156 /*
1157 * Our dear uPD72020{1,2} friend only partially resets when
1158 * asked to via the XHCI interface, and may end up doing DMA
1159 * at the wrong addresses, as it keeps the top 32bit of some
1160 * addresses from its previous programming under obscure
1161 * circumstances.
1162 * Give it a good wack at probe time. Unfortunately, this
1163 * needs to happen before we've had a chance to discover any
1164 * quirk, or the system will be in a rather bad state.
1165 */
1166 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
1167 (pdev->device == 0x0014 || pdev->device == 0x0015))
1168 return true;
1169
1170 return false;
1171}
1172EXPORT_SYMBOL_GPL(usb_xhci_needs_pci_reset);