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Thomas Gleixner41a1c9e2019-05-29 07:18:10 -07001// SPDX-License-Identifier: GPL-2.0-only
Sourav Poddar505a1492013-08-20 18:55:48 +05302/*
3 * TI QSPI driver
4 *
Alexander A. Klimov3ea4eac2020-07-08 21:44:00 +02005 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
Sourav Poddar505a1492013-08-20 18:55:48 +05306 * Author: Sourav Poddar <sourav.poddar@ti.com>
Sourav Poddar505a1492013-08-20 18:55:48 +05307 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/interrupt.h>
12#include <linux/module.h>
13#include <linux/device.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/omap-dma.h>
18#include <linux/platform_device.h>
19#include <linux/err.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/pinctrl/consumer.h>
Vignesh R4dea6c92015-12-11 09:39:57 +053027#include <linux/mfd/syscon.h>
28#include <linux/regmap.h>
Vignesh Rc687c462017-04-11 17:22:25 +053029#include <linux/sizes.h>
Sourav Poddar505a1492013-08-20 18:55:48 +053030
31#include <linux/spi/spi.h>
Boris Brezillonb95cb392018-04-26 18:18:18 +020032#include <linux/spi/spi-mem.h>
Sourav Poddar505a1492013-08-20 18:55:48 +053033
34struct ti_qspi_regs {
35 u32 clkctrl;
36};
37
38struct ti_qspi {
Vignesh R5720ec02016-08-17 15:22:37 +053039 struct completion transfer_complete;
40
Sourav Poddar505a1492013-08-20 18:55:48 +053041 /* list synchronization */
42 struct mutex list_lock;
43
44 struct spi_master *master;
45 void __iomem *base;
Sourav Poddar6b3938a2013-12-06 19:54:43 +053046 void __iomem *mmap_base;
Boris Brezillonb95cb392018-04-26 18:18:18 +020047 size_t mmap_size;
Vignesh R4dea6c92015-12-11 09:39:57 +053048 struct regmap *ctrl_base;
49 unsigned int ctrl_reg;
Sourav Poddar505a1492013-08-20 18:55:48 +053050 struct clk *fclk;
51 struct device *dev;
52
53 struct ti_qspi_regs ctx_reg;
54
Vignesh R5720ec02016-08-17 15:22:37 +053055 dma_addr_t mmap_phys_base;
Vignesh Rc687c462017-04-11 17:22:25 +053056 dma_addr_t rx_bb_dma_addr;
57 void *rx_bb_addr;
Vignesh R5720ec02016-08-17 15:22:37 +053058 struct dma_chan *rx_chan;
59
Sourav Poddar505a1492013-08-20 18:55:48 +053060 u32 spi_max_frequency;
61 u32 cmd;
62 u32 dc;
Sourav Poddar6b3938a2013-12-06 19:54:43 +053063
Vignesh R4dea6c92015-12-11 09:39:57 +053064 bool mmap_enabled;
Vignesh Raghavendrac52c91b2019-12-11 21:22:16 +053065 int current_cs;
Sourav Poddar505a1492013-08-20 18:55:48 +053066};
67
68#define QSPI_PID (0x0)
69#define QSPI_SYSCONFIG (0x10)
Sourav Poddar505a1492013-08-20 18:55:48 +053070#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
71#define QSPI_SPI_DC_REG (0x44)
72#define QSPI_SPI_CMD_REG (0x48)
73#define QSPI_SPI_STATUS_REG (0x4c)
74#define QSPI_SPI_DATA_REG (0x50)
Vignesh R4dea6c92015-12-11 09:39:57 +053075#define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
Sourav Poddar505a1492013-08-20 18:55:48 +053076#define QSPI_SPI_SWITCH_REG (0x64)
Sourav Poddar505a1492013-08-20 18:55:48 +053077#define QSPI_SPI_DATA_REG_1 (0x68)
78#define QSPI_SPI_DATA_REG_2 (0x6c)
79#define QSPI_SPI_DATA_REG_3 (0x70)
80
81#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
82
Sourav Poddar505a1492013-08-20 18:55:48 +053083/* Clock Control */
84#define QSPI_CLK_EN (1 << 31)
85#define QSPI_CLK_DIV_MAX 0xffff
86
87/* Command */
88#define QSPI_EN_CS(n) (n << 28)
89#define QSPI_WLEN(n) ((n - 1) << 19)
90#define QSPI_3_PIN (1 << 18)
91#define QSPI_RD_SNGL (1 << 16)
92#define QSPI_WR_SNGL (2 << 16)
93#define QSPI_RD_DUAL (3 << 16)
94#define QSPI_RD_QUAD (7 << 16)
95#define QSPI_INVAL (4 << 16)
Sourav Poddar505a1492013-08-20 18:55:48 +053096#define QSPI_FLEN(n) ((n - 1) << 0)
Vignesh Rf682c4f2015-08-20 16:00:59 +053097#define QSPI_WLEN_MAX_BITS 128
98#define QSPI_WLEN_MAX_BYTES 16
Ben Hutchingsea1b60f2016-04-12 12:56:25 +010099#define QSPI_WLEN_MASK QSPI_WLEN(QSPI_WLEN_MAX_BITS)
Sourav Poddar505a1492013-08-20 18:55:48 +0530100
101/* STATUS REGISTER */
Mugunthan V N00611042015-02-18 00:33:51 +0530102#define BUSY 0x01
Sourav Poddar505a1492013-08-20 18:55:48 +0530103#define WC 0x02
104
Sourav Poddar505a1492013-08-20 18:55:48 +0530105/* Device Control */
106#define QSPI_DD(m, n) (m << (3 + n * 8))
107#define QSPI_CKPHA(n) (1 << (2 + n * 8))
108#define QSPI_CSPOL(n) (1 << (1 + n * 8))
109#define QSPI_CKPOL(n) (1 << (n * 8))
110
111#define QSPI_FRAME 4096
112
113#define QSPI_AUTOSUSPEND_TIMEOUT 2000
114
Vignesh R4dea6c92015-12-11 09:39:57 +0530115#define MEM_CS_EN(n) ((n + 1) << 8)
116#define MEM_CS_MASK (7 << 8)
117
118#define MM_SWITCH 0x1
119
120#define QSPI_SETUP_RD_NORMAL (0x0 << 12)
121#define QSPI_SETUP_RD_DUAL (0x1 << 12)
122#define QSPI_SETUP_RD_QUAD (0x3 << 12)
123#define QSPI_SETUP_ADDR_SHIFT 8
124#define QSPI_SETUP_DUMMY_SHIFT 10
125
Vignesh Rc687c462017-04-11 17:22:25 +0530126#define QSPI_DMA_BUFFER_SIZE SZ_64K
127
Sourav Poddar505a1492013-08-20 18:55:48 +0530128static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
129 unsigned long reg)
130{
131 return readl(qspi->base + reg);
132}
133
134static inline void ti_qspi_write(struct ti_qspi *qspi,
135 unsigned long val, unsigned long reg)
136{
137 writel(val, qspi->base + reg);
138}
139
140static int ti_qspi_setup(struct spi_device *spi)
141{
142 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
143 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
144 int clk_div = 0, ret;
145 u32 clk_ctrl_reg, clk_rate, clk_mask;
146
147 if (spi->master->busy) {
Colin Ian King77cca632016-06-23 18:01:34 +0100148 dev_dbg(qspi->dev, "master busy doing other transfers\n");
Sourav Poddar505a1492013-08-20 18:55:48 +0530149 return -EBUSY;
150 }
151
152 if (!qspi->spi_max_frequency) {
153 dev_err(qspi->dev, "spi max frequency not defined\n");
154 return -EINVAL;
155 }
156
157 clk_rate = clk_get_rate(qspi->fclk);
158
159 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
160
161 if (clk_div < 0) {
162 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
163 return -EINVAL;
164 }
165
166 if (clk_div > QSPI_CLK_DIV_MAX) {
167 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
168 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
169 return -EINVAL;
170 }
171
172 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
173 qspi->spi_max_frequency, clk_div);
174
175 ret = pm_runtime_get_sync(qspi->dev);
Sourav Poddar05b96672013-11-19 18:37:15 +0530176 if (ret < 0) {
Sourav Poddar505a1492013-08-20 18:55:48 +0530177 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
178 return ret;
179 }
180
181 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
182
183 clk_ctrl_reg &= ~QSPI_CLK_EN;
184
185 /* disable SCLK */
186 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
187
188 /* enable SCLK */
189 clk_mask = QSPI_CLK_EN | clk_div;
190 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
191 ctx_reg->clkctrl = clk_mask;
192
193 pm_runtime_mark_last_busy(qspi->dev);
194 ret = pm_runtime_put_autosuspend(qspi->dev);
195 if (ret < 0) {
196 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
197 return ret;
198 }
199
200 return 0;
201}
202
203static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
204{
205 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
206
207 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
208}
209
Mugunthan V N00611042015-02-18 00:33:51 +0530210static inline u32 qspi_is_busy(struct ti_qspi *qspi)
211{
212 u32 stat;
213 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
214
215 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
216 while ((stat & BUSY) && time_after(timeout, jiffies)) {
217 cpu_relax();
218 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
219 }
220
221 WARN(stat & BUSY, "qspi busy\n");
222 return stat & BUSY;
223}
224
Vignesh R57c2ecd2015-10-13 15:51:05 +0530225static inline int ti_qspi_poll_wc(struct ti_qspi *qspi)
226{
227 u32 stat;
228 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT;
229
230 do {
231 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
232 if (stat & WC)
233 return 0;
234 cpu_relax();
235 } while (time_after(timeout, jiffies));
236
237 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
238 if (stat & WC)
239 return 0;
240 return -ETIMEDOUT;
241}
242
Ben Hutchings1ff77602016-04-12 12:58:14 +0100243static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t,
244 int count)
Sourav Poddar505a1492013-08-20 18:55:48 +0530245{
Ben Hutchings1ff77602016-04-12 12:58:14 +0100246 int wlen, xfer_len;
Sourav Poddar505a1492013-08-20 18:55:48 +0530247 unsigned int cmd;
248 const u8 *txbuf;
Vignesh Rf682c4f2015-08-20 16:00:59 +0530249 u32 data;
Sourav Poddar505a1492013-08-20 18:55:48 +0530250
251 txbuf = t->tx_buf;
252 cmd = qspi->cmd | QSPI_WR_SNGL;
Axel Lin3ab54622014-01-12 14:40:22 +0800253 wlen = t->bits_per_word >> 3; /* in bytes */
Vignesh Rf682c4f2015-08-20 16:00:59 +0530254 xfer_len = wlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530255
256 while (count) {
Mugunthan V N00611042015-02-18 00:33:51 +0530257 if (qspi_is_busy(qspi))
258 return -EBUSY;
259
Sourav Poddar505a1492013-08-20 18:55:48 +0530260 switch (wlen) {
Axel Lin3ab54622014-01-12 14:40:22 +0800261 case 1:
Sourav Poddar505a1492013-08-20 18:55:48 +0530262 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
263 cmd, qspi->dc, *txbuf);
Vignesh Rf682c4f2015-08-20 16:00:59 +0530264 if (count >= QSPI_WLEN_MAX_BYTES) {
265 u32 *txp = (u32 *)txbuf;
266
267 data = cpu_to_be32(*txp++);
268 writel(data, qspi->base +
269 QSPI_SPI_DATA_REG_3);
270 data = cpu_to_be32(*txp++);
271 writel(data, qspi->base +
272 QSPI_SPI_DATA_REG_2);
273 data = cpu_to_be32(*txp++);
274 writel(data, qspi->base +
275 QSPI_SPI_DATA_REG_1);
276 data = cpu_to_be32(*txp++);
277 writel(data, qspi->base +
278 QSPI_SPI_DATA_REG);
279 xfer_len = QSPI_WLEN_MAX_BYTES;
280 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
281 } else {
282 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
283 cmd = qspi->cmd | QSPI_WR_SNGL;
284 xfer_len = wlen;
285 cmd |= QSPI_WLEN(wlen);
286 }
Sourav Poddar505a1492013-08-20 18:55:48 +0530287 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800288 case 2:
Sourav Poddar505a1492013-08-20 18:55:48 +0530289 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
290 cmd, qspi->dc, *txbuf);
291 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530292 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800293 case 4:
Sourav Poddar505a1492013-08-20 18:55:48 +0530294 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
295 cmd, qspi->dc, *txbuf);
296 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530297 break;
298 }
Axel Lin3ab54622014-01-12 14:40:22 +0800299
300 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
Vignesh R57c2ecd2015-10-13 15:51:05 +0530301 if (ti_qspi_poll_wc(qspi)) {
Axel Lin3ab54622014-01-12 14:40:22 +0800302 dev_err(qspi->dev, "write timed out\n");
303 return -ETIMEDOUT;
304 }
Vignesh Rf682c4f2015-08-20 16:00:59 +0530305 txbuf += xfer_len;
306 count -= xfer_len;
Sourav Poddar505a1492013-08-20 18:55:48 +0530307 }
308
309 return 0;
310}
311
Ben Hutchings1ff77602016-04-12 12:58:14 +0100312static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t,
313 int count)
Sourav Poddar505a1492013-08-20 18:55:48 +0530314{
Ben Hutchings1ff77602016-04-12 12:58:14 +0100315 int wlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530316 unsigned int cmd;
Jean Pihete7cc5cfb2020-01-14 13:41:25 +0100317 u32 rx;
318 u8 rxlen, rx_wlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530319 u8 *rxbuf;
320
321 rxbuf = t->rx_buf;
Sourav Poddar70e2e972013-08-23 15:12:16 +0530322 cmd = qspi->cmd;
323 switch (t->rx_nbits) {
324 case SPI_NBITS_DUAL:
325 cmd |= QSPI_RD_DUAL;
326 break;
327 case SPI_NBITS_QUAD:
328 cmd |= QSPI_RD_QUAD;
329 break;
330 default:
331 cmd |= QSPI_RD_SNGL;
332 break;
333 }
Axel Lin3ab54622014-01-12 14:40:22 +0800334 wlen = t->bits_per_word >> 3; /* in bytes */
Jean Pihet6925212f2020-01-15 11:07:00 +0100335 rx_wlen = wlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530336
337 while (count) {
338 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
Mugunthan V N00611042015-02-18 00:33:51 +0530339 if (qspi_is_busy(qspi))
340 return -EBUSY;
341
Jean Pihete7cc5cfb2020-01-14 13:41:25 +0100342 switch (wlen) {
343 case 1:
344 /*
345 * Optimize the 8-bit words transfers, as used by
346 * the SPI flash devices.
347 */
348 if (count >= QSPI_WLEN_MAX_BYTES) {
349 rxlen = QSPI_WLEN_MAX_BYTES;
350 } else {
351 rxlen = min(count, 4);
352 }
353 rx_wlen = rxlen << 3;
354 cmd &= ~QSPI_WLEN_MASK;
355 cmd |= QSPI_WLEN(rx_wlen);
356 break;
357 default:
358 rxlen = wlen;
359 break;
360 }
361
Sourav Poddar505a1492013-08-20 18:55:48 +0530362 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
Vignesh R57c2ecd2015-10-13 15:51:05 +0530363 if (ti_qspi_poll_wc(qspi)) {
Sourav Poddar505a1492013-08-20 18:55:48 +0530364 dev_err(qspi->dev, "read timed out\n");
365 return -ETIMEDOUT;
366 }
Jean Pihete7cc5cfb2020-01-14 13:41:25 +0100367
Sourav Poddar505a1492013-08-20 18:55:48 +0530368 switch (wlen) {
Axel Lin3ab54622014-01-12 14:40:22 +0800369 case 1:
Jean Pihete7cc5cfb2020-01-14 13:41:25 +0100370 /*
371 * Optimize the 8-bit words transfers, as used by
372 * the SPI flash devices.
373 */
374 if (count >= QSPI_WLEN_MAX_BYTES) {
375 u32 *rxp = (u32 *) rxbuf;
376 rx = readl(qspi->base + QSPI_SPI_DATA_REG_3);
377 *rxp++ = be32_to_cpu(rx);
378 rx = readl(qspi->base + QSPI_SPI_DATA_REG_2);
379 *rxp++ = be32_to_cpu(rx);
380 rx = readl(qspi->base + QSPI_SPI_DATA_REG_1);
381 *rxp++ = be32_to_cpu(rx);
382 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
383 *rxp++ = be32_to_cpu(rx);
384 } else {
385 u8 *rxp = rxbuf;
386 rx = readl(qspi->base + QSPI_SPI_DATA_REG);
387 if (rx_wlen >= 8)
388 *rxp++ = rx >> (rx_wlen - 8);
389 if (rx_wlen >= 16)
390 *rxp++ = rx >> (rx_wlen - 16);
391 if (rx_wlen >= 24)
392 *rxp++ = rx >> (rx_wlen - 24);
393 if (rx_wlen >= 32)
394 *rxp++ = rx;
395 }
Sourav Poddar505a1492013-08-20 18:55:48 +0530396 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800397 case 2:
Sourav Poddar505a1492013-08-20 18:55:48 +0530398 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530399 break;
Axel Lin3ab54622014-01-12 14:40:22 +0800400 case 4:
Sourav Poddar505a1492013-08-20 18:55:48 +0530401 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530402 break;
403 }
Jean Pihete7cc5cfb2020-01-14 13:41:25 +0100404 rxbuf += rxlen;
405 count -= rxlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530406 }
407
408 return 0;
409}
410
Ben Hutchings1ff77602016-04-12 12:58:14 +0100411static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t,
412 int count)
Sourav Poddar505a1492013-08-20 18:55:48 +0530413{
414 int ret;
415
416 if (t->tx_buf) {
Ben Hutchings1ff77602016-04-12 12:58:14 +0100417 ret = qspi_write_msg(qspi, t, count);
Sourav Poddar505a1492013-08-20 18:55:48 +0530418 if (ret) {
419 dev_dbg(qspi->dev, "Error while writing\n");
420 return ret;
421 }
422 }
423
424 if (t->rx_buf) {
Ben Hutchings1ff77602016-04-12 12:58:14 +0100425 ret = qspi_read_msg(qspi, t, count);
Sourav Poddar505a1492013-08-20 18:55:48 +0530426 if (ret) {
427 dev_dbg(qspi->dev, "Error while reading\n");
428 return ret;
429 }
430 }
431
432 return 0;
433}
434
Vignesh R5720ec02016-08-17 15:22:37 +0530435static void ti_qspi_dma_callback(void *param)
436{
437 struct ti_qspi *qspi = param;
438
439 complete(&qspi->transfer_complete);
440}
441
442static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
443 dma_addr_t dma_src, size_t len)
444{
445 struct dma_chan *chan = qspi->rx_chan;
Vignesh R5720ec02016-08-17 15:22:37 +0530446 dma_cookie_t cookie;
447 enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
448 struct dma_async_tx_descriptor *tx;
449 int ret;
450
Vignesh R1351aae2017-03-24 12:12:15 +0530451 tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, flags);
Vignesh R5720ec02016-08-17 15:22:37 +0530452 if (!tx) {
453 dev_err(qspi->dev, "device_prep_dma_memcpy error\n");
454 return -EIO;
455 }
456
457 tx->callback = ti_qspi_dma_callback;
458 tx->callback_param = qspi;
459 cookie = tx->tx_submit(tx);
Prahlad Vd06a3502016-11-15 23:56:43 +0530460 reinit_completion(&qspi->transfer_complete);
Vignesh R5720ec02016-08-17 15:22:37 +0530461
462 ret = dma_submit_error(cookie);
463 if (ret) {
464 dev_err(qspi->dev, "dma_submit_error %d\n", cookie);
465 return -EIO;
466 }
467
468 dma_async_issue_pending(chan);
469 ret = wait_for_completion_timeout(&qspi->transfer_complete,
470 msecs_to_jiffies(len));
471 if (ret <= 0) {
472 dmaengine_terminate_sync(chan);
473 dev_err(qspi->dev, "DMA wait_for_completion_timeout\n");
474 return -ETIMEDOUT;
475 }
476
477 return 0;
478}
479
Boris Brezillonb95cb392018-04-26 18:18:18 +0200480static int ti_qspi_dma_bounce_buffer(struct ti_qspi *qspi, loff_t offs,
481 void *to, size_t readsize)
Vignesh Rc687c462017-04-11 17:22:25 +0530482{
Boris Brezillonb95cb392018-04-26 18:18:18 +0200483 dma_addr_t dma_src = qspi->mmap_phys_base + offs;
Vignesh Rc687c462017-04-11 17:22:25 +0530484 int ret = 0;
485
486 /*
487 * Use bounce buffer as FS like jffs2, ubifs may pass
488 * buffers that does not belong to kernel lowmem region.
489 */
490 while (readsize != 0) {
491 size_t xfer_len = min_t(size_t, QSPI_DMA_BUFFER_SIZE,
492 readsize);
493
494 ret = ti_qspi_dma_xfer(qspi, qspi->rx_bb_dma_addr,
495 dma_src, xfer_len);
496 if (ret != 0)
497 return ret;
498 memcpy(to, qspi->rx_bb_addr, xfer_len);
499 readsize -= xfer_len;
500 dma_src += xfer_len;
501 to += xfer_len;
502 }
503
504 return ret;
505}
506
Vignesh R5720ec02016-08-17 15:22:37 +0530507static int ti_qspi_dma_xfer_sg(struct ti_qspi *qspi, struct sg_table rx_sg,
508 loff_t from)
509{
510 struct scatterlist *sg;
511 dma_addr_t dma_src = qspi->mmap_phys_base + from;
512 dma_addr_t dma_dst;
513 int i, len, ret;
514
515 for_each_sg(rx_sg.sgl, sg, rx_sg.nents, i) {
516 dma_dst = sg_dma_address(sg);
517 len = sg_dma_len(sg);
518 ret = ti_qspi_dma_xfer(qspi, dma_dst, dma_src, len);
519 if (ret)
520 return ret;
521 dma_src += len;
522 }
523
524 return 0;
525}
526
Vignesh R4dea6c92015-12-11 09:39:57 +0530527static void ti_qspi_enable_memory_map(struct spi_device *spi)
528{
529 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
530
531 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
532 if (qspi->ctrl_base) {
533 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
Vignesh R673c8652019-01-29 13:14:22 +0530534 MEM_CS_MASK,
535 MEM_CS_EN(spi->chip_select));
Vignesh R4dea6c92015-12-11 09:39:57 +0530536 }
537 qspi->mmap_enabled = true;
Vignesh Raghavendrac52c91b2019-12-11 21:22:16 +0530538 qspi->current_cs = spi->chip_select;
Vignesh R4dea6c92015-12-11 09:39:57 +0530539}
540
541static void ti_qspi_disable_memory_map(struct spi_device *spi)
542{
543 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
544
545 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
546 if (qspi->ctrl_base)
547 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
Vignesh R673c8652019-01-29 13:14:22 +0530548 MEM_CS_MASK, 0);
Vignesh R4dea6c92015-12-11 09:39:57 +0530549 qspi->mmap_enabled = false;
Vignesh Raghavendrac52c91b2019-12-11 21:22:16 +0530550 qspi->current_cs = -1;
Vignesh R4dea6c92015-12-11 09:39:57 +0530551}
552
Boris Brezillonb95cb392018-04-26 18:18:18 +0200553static void ti_qspi_setup_mmap_read(struct spi_device *spi, u8 opcode,
554 u8 data_nbits, u8 addr_width,
555 u8 dummy_bytes)
Vignesh R4dea6c92015-12-11 09:39:57 +0530556{
557 struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
Boris Brezillonb95cb392018-04-26 18:18:18 +0200558 u32 memval = opcode;
Vignesh R4dea6c92015-12-11 09:39:57 +0530559
Boris Brezillonb95cb392018-04-26 18:18:18 +0200560 switch (data_nbits) {
Vignesh R4dea6c92015-12-11 09:39:57 +0530561 case SPI_NBITS_QUAD:
562 memval |= QSPI_SETUP_RD_QUAD;
563 break;
564 case SPI_NBITS_DUAL:
565 memval |= QSPI_SETUP_RD_DUAL;
566 break;
567 default:
568 memval |= QSPI_SETUP_RD_NORMAL;
569 break;
570 }
Boris Brezillonb95cb392018-04-26 18:18:18 +0200571 memval |= ((addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
572 dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
Vignesh R4dea6c92015-12-11 09:39:57 +0530573 ti_qspi_write(qspi, memval,
574 QSPI_SPI_SETUP_REG(spi->chip_select));
575}
576
Jean Pihete97f4912020-01-14 13:41:24 +0100577static int ti_qspi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op)
578{
579 struct ti_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
580 size_t max_len;
581
582 if (op->data.dir == SPI_MEM_DATA_IN) {
583 if (op->addr.val < qspi->mmap_size) {
584 /* Limit MMIO to the mmaped region */
585 if (op->addr.val + op->data.nbytes > qspi->mmap_size) {
586 max_len = qspi->mmap_size - op->addr.val;
587 op->data.nbytes = min((size_t) op->data.nbytes,
588 max_len);
589 }
590 } else {
591 /*
592 * Use fallback mode (SW generated transfers) above the
593 * mmaped region.
594 * Adjust size to comply with the QSPI max frame length.
595 */
596 max_len = QSPI_FRAME;
597 max_len -= 1 + op->addr.nbytes + op->dummy.nbytes;
598 op->data.nbytes = min((size_t) op->data.nbytes,
599 max_len);
600 }
601 }
602
603 return 0;
604}
605
Boris Brezillonb95cb392018-04-26 18:18:18 +0200606static int ti_qspi_exec_mem_op(struct spi_mem *mem,
607 const struct spi_mem_op *op)
608{
609 struct ti_qspi *qspi = spi_master_get_devdata(mem->spi->master);
610 u32 from = 0;
611 int ret = 0;
612
613 /* Only optimize read path. */
614 if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
615 !op->addr.nbytes || op->addr.nbytes > 4)
616 return -ENOTSUPP;
617
618 /* Address exceeds MMIO window size, fall back to regular mode. */
619 from = op->addr.val;
620 if (from + op->data.nbytes > qspi->mmap_size)
621 return -ENOTSUPP;
622
623 mutex_lock(&qspi->list_lock);
624
Vignesh Raghavendrac52c91b2019-12-11 21:22:16 +0530625 if (!qspi->mmap_enabled || qspi->current_cs != mem->spi->chip_select)
Boris Brezillonb95cb392018-04-26 18:18:18 +0200626 ti_qspi_enable_memory_map(mem->spi);
627 ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
628 op->addr.nbytes, op->dummy.nbytes);
629
630 if (qspi->rx_chan) {
631 struct sg_table sgt;
632
633 if (virt_addr_valid(op->data.buf.in) &&
634 !spi_controller_dma_map_mem_op_data(mem->spi->master, op,
635 &sgt)) {
636 ret = ti_qspi_dma_xfer_sg(qspi, sgt, from);
637 spi_controller_dma_unmap_mem_op_data(mem->spi->master,
638 op, &sgt);
639 } else {
640 ret = ti_qspi_dma_bounce_buffer(qspi, from,
641 op->data.buf.in,
642 op->data.nbytes);
643 }
644 } else {
645 memcpy_fromio(op->data.buf.in, qspi->mmap_base + from,
646 op->data.nbytes);
647 }
648
649 mutex_unlock(&qspi->list_lock);
650
651 return ret;
652}
653
654static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
655 .exec_op = ti_qspi_exec_mem_op,
Jean Pihete97f4912020-01-14 13:41:24 +0100656 .adjust_op_size = ti_qspi_adjust_op_size,
Boris Brezillonb95cb392018-04-26 18:18:18 +0200657};
658
Sourav Poddar505a1492013-08-20 18:55:48 +0530659static int ti_qspi_start_transfer_one(struct spi_master *master,
660 struct spi_message *m)
661{
662 struct ti_qspi *qspi = spi_master_get_devdata(master);
663 struct spi_device *spi = m->spi;
664 struct spi_transfer *t;
665 int status = 0, ret;
Ben Hutchings1ff77602016-04-12 12:58:14 +0100666 unsigned int frame_len_words, transfer_len_words;
667 int wlen;
Sourav Poddar505a1492013-08-20 18:55:48 +0530668
669 /* setup device control reg */
670 qspi->dc = 0;
671
672 if (spi->mode & SPI_CPHA)
673 qspi->dc |= QSPI_CKPHA(spi->chip_select);
674 if (spi->mode & SPI_CPOL)
675 qspi->dc |= QSPI_CKPOL(spi->chip_select);
676 if (spi->mode & SPI_CS_HIGH)
677 qspi->dc |= QSPI_CSPOL(spi->chip_select);
678
Ben Hutchingsea1b60f2016-04-12 12:56:25 +0100679 frame_len_words = 0;
680 list_for_each_entry(t, &m->transfers, transfer_list)
681 frame_len_words += t->len / (t->bits_per_word >> 3);
682 frame_len_words = min_t(unsigned int, frame_len_words, QSPI_FRAME);
Sourav Poddar505a1492013-08-20 18:55:48 +0530683
684 /* setup command reg */
685 qspi->cmd = 0;
686 qspi->cmd |= QSPI_EN_CS(spi->chip_select);
Ben Hutchingsea1b60f2016-04-12 12:56:25 +0100687 qspi->cmd |= QSPI_FLEN(frame_len_words);
Sourav Poddar505a1492013-08-20 18:55:48 +0530688
Sourav Poddar505a1492013-08-20 18:55:48 +0530689 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
690
691 mutex_lock(&qspi->list_lock);
692
Vignesh R4dea6c92015-12-11 09:39:57 +0530693 if (qspi->mmap_enabled)
694 ti_qspi_disable_memory_map(spi);
695
Sourav Poddar505a1492013-08-20 18:55:48 +0530696 list_for_each_entry(t, &m->transfers, transfer_list) {
Ben Hutchingsea1b60f2016-04-12 12:56:25 +0100697 qspi->cmd = ((qspi->cmd & ~QSPI_WLEN_MASK) |
698 QSPI_WLEN(t->bits_per_word));
Sourav Poddar505a1492013-08-20 18:55:48 +0530699
Ben Hutchings1ff77602016-04-12 12:58:14 +0100700 wlen = t->bits_per_word >> 3;
701 transfer_len_words = min(t->len / wlen, frame_len_words);
702
703 ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
Sourav Poddar505a1492013-08-20 18:55:48 +0530704 if (ret) {
705 dev_dbg(qspi->dev, "transfer message failed\n");
Wei Yongjunb6460362013-09-01 09:01:00 +0800706 mutex_unlock(&qspi->list_lock);
Sourav Poddar505a1492013-08-20 18:55:48 +0530707 return -EINVAL;
708 }
709
Ben Hutchings1ff77602016-04-12 12:58:14 +0100710 m->actual_length += transfer_len_words * wlen;
711 frame_len_words -= transfer_len_words;
712 if (frame_len_words == 0)
713 break;
Sourav Poddar505a1492013-08-20 18:55:48 +0530714 }
715
716 mutex_unlock(&qspi->list_lock);
717
Vignesh Rbc27a532015-10-12 13:22:02 +0530718 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
Sourav Poddar505a1492013-08-20 18:55:48 +0530719 m->status = status;
720 spi_finalize_current_message(master);
721
Sourav Poddar505a1492013-08-20 18:55:48 +0530722 return status;
723}
724
Sourav Poddar505a1492013-08-20 18:55:48 +0530725static int ti_qspi_runtime_resume(struct device *dev)
726{
727 struct ti_qspi *qspi;
Sourav Poddar505a1492013-08-20 18:55:48 +0530728
Sourav Poddarf17414c2013-12-20 18:22:57 +0530729 qspi = dev_get_drvdata(dev);
Sourav Poddar505a1492013-08-20 18:55:48 +0530730 ti_qspi_restore_ctx(qspi);
731
732 return 0;
733}
734
735static const struct of_device_id ti_qspi_match[] = {
736 {.compatible = "ti,dra7xxx-qspi" },
Sourav Poddar09222fc2013-08-27 19:42:24 +0530737 {.compatible = "ti,am4372-qspi" },
Sourav Poddar505a1492013-08-20 18:55:48 +0530738 {},
739};
Sourav Poddare1432d32013-08-27 12:41:20 +0530740MODULE_DEVICE_TABLE(of, ti_qspi_match);
Sourav Poddar505a1492013-08-20 18:55:48 +0530741
742static int ti_qspi_probe(struct platform_device *pdev)
743{
744 struct ti_qspi *qspi;
745 struct spi_master *master;
Vignesh R4dea6c92015-12-11 09:39:57 +0530746 struct resource *r, *res_mmap;
Sourav Poddar505a1492013-08-20 18:55:48 +0530747 struct device_node *np = pdev->dev.of_node;
748 u32 max_freq;
749 int ret = 0, num_cs, irq;
Vignesh R5720ec02016-08-17 15:22:37 +0530750 dma_cap_mask_t mask;
Sourav Poddar505a1492013-08-20 18:55:48 +0530751
752 master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
753 if (!master)
754 return -ENOMEM;
755
Sourav Poddar633795b2013-09-24 20:41:23 +0530756 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
Sourav Poddar505a1492013-08-20 18:55:48 +0530757
Sourav Poddar505a1492013-08-20 18:55:48 +0530758 master->flags = SPI_MASTER_HALF_DUPLEX;
759 master->setup = ti_qspi_setup;
760 master->auto_runtime_pm = true;
761 master->transfer_one_message = ti_qspi_start_transfer_one;
762 master->dev.of_node = pdev->dev.of_node;
Axel Linaa188f92014-02-05 21:59:18 +0800763 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
764 SPI_BPW_MASK(8);
Boris Brezillonb95cb392018-04-26 18:18:18 +0200765 master->mem_ops = &ti_qspi_mem_ops;
Sourav Poddar505a1492013-08-20 18:55:48 +0530766
767 if (!of_property_read_u32(np, "num-cs", &num_cs))
768 master->num_chipselect = num_cs;
769
Sourav Poddar505a1492013-08-20 18:55:48 +0530770 qspi = spi_master_get_devdata(master);
771 qspi->master = master;
772 qspi->dev = &pdev->dev;
Wei Yongjun160a0612013-11-11 14:13:41 +0800773 platform_set_drvdata(pdev, qspi);
Sourav Poddar505a1492013-08-20 18:55:48 +0530774
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530775 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
776 if (r == NULL) {
777 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
778 if (r == NULL) {
779 dev_err(&pdev->dev, "missing platform data\n");
Prahlad Vcce59c22017-02-17 02:03:35 +0530780 ret = -ENODEV;
781 goto free_master;
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530782 }
783 }
784
785 res_mmap = platform_get_resource_byname(pdev,
786 IORESOURCE_MEM, "qspi_mmap");
787 if (res_mmap == NULL) {
788 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
789 if (res_mmap == NULL) {
790 dev_err(&pdev->dev,
791 "memory mapped resource not required\n");
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530792 }
793 }
Boris Brezillon6282f122018-05-14 11:11:29 +0200794
795 if (res_mmap)
796 qspi->mmap_size = resource_size(res_mmap);
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530797
Sourav Poddar505a1492013-08-20 18:55:48 +0530798 irq = platform_get_irq(pdev, 0);
799 if (irq < 0) {
Prahlad Vcce59c22017-02-17 02:03:35 +0530800 ret = irq;
801 goto free_master;
Sourav Poddar505a1492013-08-20 18:55:48 +0530802 }
803
Sourav Poddar505a1492013-08-20 18:55:48 +0530804 mutex_init(&qspi->list_lock);
805
806 qspi->base = devm_ioremap_resource(&pdev->dev, r);
807 if (IS_ERR(qspi->base)) {
808 ret = PTR_ERR(qspi->base);
809 goto free_master;
810 }
811
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530812
Vignesh R4dea6c92015-12-11 09:39:57 +0530813 if (of_property_read_bool(np, "syscon-chipselects")) {
814 qspi->ctrl_base =
815 syscon_regmap_lookup_by_phandle(np,
816 "syscon-chipselects");
Prahlad Vcce59c22017-02-17 02:03:35 +0530817 if (IS_ERR(qspi->ctrl_base)) {
818 ret = PTR_ERR(qspi->ctrl_base);
819 goto free_master;
820 }
Vignesh R4dea6c92015-12-11 09:39:57 +0530821 ret = of_property_read_u32_index(np,
822 "syscon-chipselects",
823 1, &qspi->ctrl_reg);
824 if (ret) {
825 dev_err(&pdev->dev,
826 "couldn't get ctrl_mod reg index\n");
Prahlad Vcce59c22017-02-17 02:03:35 +0530827 goto free_master;
Sourav Poddar6b3938a2013-12-06 19:54:43 +0530828 }
829 }
830
Sourav Poddar505a1492013-08-20 18:55:48 +0530831 qspi->fclk = devm_clk_get(&pdev->dev, "fck");
832 if (IS_ERR(qspi->fclk)) {
833 ret = PTR_ERR(qspi->fclk);
834 dev_err(&pdev->dev, "could not get clk: %d\n", ret);
835 }
836
Sourav Poddar505a1492013-08-20 18:55:48 +0530837 pm_runtime_use_autosuspend(&pdev->dev);
838 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
839 pm_runtime_enable(&pdev->dev);
840
841 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
842 qspi->spi_max_frequency = max_freq;
843
Vignesh R5720ec02016-08-17 15:22:37 +0530844 dma_cap_zero(mask);
845 dma_cap_set(DMA_MEMCPY, mask);
Sourav Poddar505a1492013-08-20 18:55:48 +0530846
Vignesh R5720ec02016-08-17 15:22:37 +0530847 qspi->rx_chan = dma_request_chan_by_mask(&mask);
Christophe JAILLET7abfe042017-02-18 10:42:02 +0100848 if (IS_ERR(qspi->rx_chan)) {
Vignesh R5720ec02016-08-17 15:22:37 +0530849 dev_err(qspi->dev,
850 "No Rx DMA available, trying mmap mode\n");
Christophe JAILLET7abfe042017-02-18 10:42:02 +0100851 qspi->rx_chan = NULL;
Vignesh R5720ec02016-08-17 15:22:37 +0530852 ret = 0;
853 goto no_dma;
854 }
Vignesh Rc687c462017-04-11 17:22:25 +0530855 qspi->rx_bb_addr = dma_alloc_coherent(qspi->dev,
856 QSPI_DMA_BUFFER_SIZE,
857 &qspi->rx_bb_dma_addr,
858 GFP_KERNEL | GFP_DMA);
859 if (!qspi->rx_bb_addr) {
860 dev_err(qspi->dev,
861 "dma_alloc_coherent failed, using PIO mode\n");
862 dma_release_channel(qspi->rx_chan);
863 goto no_dma;
864 }
Vignesh R5720ec02016-08-17 15:22:37 +0530865 master->dma_rx = qspi->rx_chan;
866 init_completion(&qspi->transfer_complete);
867 if (res_mmap)
868 qspi->mmap_phys_base = (dma_addr_t)res_mmap->start;
869
870no_dma:
871 if (!qspi->rx_chan && res_mmap) {
872 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
873 if (IS_ERR(qspi->mmap_base)) {
874 dev_info(&pdev->dev,
875 "mmap failed with error %ld using PIO mode\n",
876 PTR_ERR(qspi->mmap_base));
877 qspi->mmap_base = NULL;
Boris Brezillonb95cb392018-04-26 18:18:18 +0200878 master->mem_ops = NULL;
Vignesh R5720ec02016-08-17 15:22:37 +0530879 }
880 }
881 qspi->mmap_enabled = false;
Vignesh Raghavendrac52c91b2019-12-11 21:22:16 +0530882 qspi->current_cs = -1;
Vignesh R5720ec02016-08-17 15:22:37 +0530883
884 ret = devm_spi_register_master(&pdev->dev, master);
885 if (!ret)
886 return 0;
Sourav Poddar505a1492013-08-20 18:55:48 +0530887
Prahlad Vcce59c22017-02-17 02:03:35 +0530888 pm_runtime_disable(&pdev->dev);
Sourav Poddar505a1492013-08-20 18:55:48 +0530889free_master:
890 spi_master_put(master);
891 return ret;
892}
893
894static int ti_qspi_remove(struct platform_device *pdev)
895{
Jean-Jacques Hiblot3ac066e2016-05-31 17:56:23 +0200896 struct ti_qspi *qspi = platform_get_drvdata(pdev);
897 int rc;
898
899 rc = spi_master_suspend(qspi->master);
900 if (rc)
901 return rc;
902
Felipe Balbie6b51402015-10-29 08:57:30 -0500903 pm_runtime_put_sync(&pdev->dev);
Sourav Poddarcbcabb72013-11-19 18:37:16 +0530904 pm_runtime_disable(&pdev->dev);
905
Vignesh Rc687c462017-04-11 17:22:25 +0530906 if (qspi->rx_bb_addr)
907 dma_free_coherent(qspi->dev, QSPI_DMA_BUFFER_SIZE,
908 qspi->rx_bb_addr,
909 qspi->rx_bb_dma_addr);
Vignesh R5720ec02016-08-17 15:22:37 +0530910 if (qspi->rx_chan)
911 dma_release_channel(qspi->rx_chan);
912
Sourav Poddar505a1492013-08-20 18:55:48 +0530913 return 0;
914}
915
916static const struct dev_pm_ops ti_qspi_pm_ops = {
917 .runtime_resume = ti_qspi_runtime_resume,
918};
919
920static struct platform_driver ti_qspi_driver = {
921 .probe = ti_qspi_probe,
Mark Browndabefd52013-10-07 12:02:26 +0100922 .remove = ti_qspi_remove,
Sourav Poddar505a1492013-08-20 18:55:48 +0530923 .driver = {
Axel Lin5a33d302014-01-12 15:02:32 +0800924 .name = "ti-qspi",
Sourav Poddar505a1492013-08-20 18:55:48 +0530925 .pm = &ti_qspi_pm_ops,
926 .of_match_table = ti_qspi_match,
927 }
928};
929
930module_platform_driver(ti_qspi_driver);
931
932MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
933MODULE_LICENSE("GPL v2");
934MODULE_DESCRIPTION("TI QSPI controller driver");
Axel Lin5a33d302014-01-12 15:02:32 +0800935MODULE_ALIAS("platform:ti-qspi");