Sean Paul | 495eb7f | 2018-01-08 14:55:38 -0500 | [diff] [blame] | 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Copyright (C) 2017 Google, Inc. |
| 4 | * |
| 5 | * Authors: |
| 6 | * Sean Paul <seanpaul@chromium.org> |
| 7 | */ |
| 8 | |
| 9 | #ifndef _DRM_HDCP_H_INCLUDED_ |
| 10 | #define _DRM_HDCP_H_INCLUDED_ |
| 11 | |
Jani Nikula | f7e271d | 2018-12-27 14:56:39 +0200 | [diff] [blame] | 12 | #include <linux/types.h> |
| 13 | |
Sean Paul | 495eb7f | 2018-01-08 14:55:38 -0500 | [diff] [blame] | 14 | /* Period of hdcp checks (to ensure we're still authenticated) */ |
| 15 | #define DRM_HDCP_CHECK_PERIOD_MS (128 * 16) |
Ramalingam C | aeb0d80 | 2019-02-16 23:06:56 +0530 | [diff] [blame] | 16 | #define DRM_HDCP2_CHECK_PERIOD_MS 500 |
Sean Paul | 495eb7f | 2018-01-08 14:55:38 -0500 | [diff] [blame] | 17 | |
| 18 | /* Shared lengths/masks between HDMI/DVI/DisplayPort */ |
| 19 | #define DRM_HDCP_AN_LEN 8 |
| 20 | #define DRM_HDCP_BSTATUS_LEN 2 |
| 21 | #define DRM_HDCP_KSV_LEN 5 |
| 22 | #define DRM_HDCP_RI_LEN 2 |
| 23 | #define DRM_HDCP_V_PRIME_PART_LEN 4 |
| 24 | #define DRM_HDCP_V_PRIME_NUM_PARTS 5 |
Ramalingam C | b8e47d8 | 2018-04-05 17:33:22 +0530 | [diff] [blame] | 25 | #define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f) |
Ramalingam C | 49d85d0 | 2018-01-18 11:18:08 +0530 | [diff] [blame] | 26 | #define DRM_HDCP_MAX_CASCADE_EXCEEDED(x) (x & BIT(3)) |
| 27 | #define DRM_HDCP_MAX_DEVICE_EXCEEDED(x) (x & BIT(7)) |
Sean Paul | 495eb7f | 2018-01-08 14:55:38 -0500 | [diff] [blame] | 28 | |
| 29 | /* Slave address for the HDCP registers in the receiver */ |
| 30 | #define DRM_HDCP_DDC_ADDR 0x3A |
| 31 | |
Sean Paul | 9ab5765 | 2020-08-18 11:38:49 -0400 | [diff] [blame] | 32 | /* Value to use at the end of the SHA-1 bytestream used for repeaters */ |
| 33 | #define DRM_HDCP_SHA1_TERMINATOR 0x80 |
| 34 | |
Sean Paul | 495eb7f | 2018-01-08 14:55:38 -0500 | [diff] [blame] | 35 | /* HDCP register offsets for HDMI/DVI devices */ |
| 36 | #define DRM_HDCP_DDC_BKSV 0x00 |
| 37 | #define DRM_HDCP_DDC_RI_PRIME 0x08 |
| 38 | #define DRM_HDCP_DDC_AKSV 0x10 |
| 39 | #define DRM_HDCP_DDC_AN 0x18 |
| 40 | #define DRM_HDCP_DDC_V_PRIME(h) (0x20 + h * 4) |
| 41 | #define DRM_HDCP_DDC_BCAPS 0x40 |
| 42 | #define DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT BIT(6) |
| 43 | #define DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY BIT(5) |
| 44 | #define DRM_HDCP_DDC_BSTATUS 0x41 |
| 45 | #define DRM_HDCP_DDC_KSV_FIFO 0x43 |
| 46 | |
Ramalingam C | af5aad0 | 2018-10-29 15:15:49 +0530 | [diff] [blame] | 47 | #define DRM_HDCP_1_4_SRM_ID 0x8 |
| 48 | #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 |
| 49 | #define DRM_HDCP_1_4_DCP_SIG_SIZE 40 |
| 50 | |
| 51 | /* Protocol message definition for HDCP2.2 specification */ |
| 52 | /* |
| 53 | * Protected content streams are classified into 2 types: |
| 54 | * - Type0: Can be transmitted with HDCP 1.4+ |
| 55 | * - Type1: Can be transmitted with HDCP 2.2+ |
| 56 | */ |
| 57 | #define HDCP_STREAM_TYPE0 0x00 |
| 58 | #define HDCP_STREAM_TYPE1 0x01 |
| 59 | |
| 60 | /* HDCP2.2 Msg IDs */ |
| 61 | #define HDCP_2_2_NULL_MSG 1 |
| 62 | #define HDCP_2_2_AKE_INIT 2 |
| 63 | #define HDCP_2_2_AKE_SEND_CERT 3 |
| 64 | #define HDCP_2_2_AKE_NO_STORED_KM 4 |
| 65 | #define HDCP_2_2_AKE_STORED_KM 5 |
| 66 | #define HDCP_2_2_AKE_SEND_HPRIME 7 |
| 67 | #define HDCP_2_2_AKE_SEND_PAIRING_INFO 8 |
| 68 | #define HDCP_2_2_LC_INIT 9 |
| 69 | #define HDCP_2_2_LC_SEND_LPRIME 10 |
| 70 | #define HDCP_2_2_SKE_SEND_EKS 11 |
| 71 | #define HDCP_2_2_REP_SEND_RECVID_LIST 12 |
| 72 | #define HDCP_2_2_REP_SEND_ACK 15 |
| 73 | #define HDCP_2_2_REP_STREAM_MANAGE 16 |
| 74 | #define HDCP_2_2_REP_STREAM_READY 17 |
Ramalingam C | af5aad0 | 2018-10-29 15:15:49 +0530 | [diff] [blame] | 75 | |
| 76 | #define HDCP_2_2_RTX_LEN 8 |
| 77 | #define HDCP_2_2_RRX_LEN 8 |
| 78 | |
| 79 | #define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128 |
| 80 | #define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3 |
| 81 | #define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \ |
| 82 | HDCP_2_2_K_PUB_RX_EXP_E_LEN) |
| 83 | |
| 84 | #define HDCP_2_2_DCP_LLC_SIG_LEN 384 |
| 85 | |
| 86 | #define HDCP_2_2_E_KPUB_KM_LEN 128 |
| 87 | #define HDCP_2_2_E_KH_KM_M_LEN (16 + 16) |
| 88 | #define HDCP_2_2_H_PRIME_LEN 32 |
| 89 | #define HDCP_2_2_E_KH_KM_LEN 16 |
| 90 | #define HDCP_2_2_RN_LEN 8 |
| 91 | #define HDCP_2_2_L_PRIME_LEN 32 |
| 92 | #define HDCP_2_2_E_DKEY_KS_LEN 16 |
| 93 | #define HDCP_2_2_RIV_LEN 8 |
| 94 | #define HDCP_2_2_SEQ_NUM_LEN 3 |
| 95 | #define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2) |
| 96 | #define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN |
| 97 | #define HDCP_2_2_MAX_DEVICE_COUNT 31 |
| 98 | #define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \ |
| 99 | HDCP_2_2_MAX_DEVICE_COUNT) |
| 100 | #define HDCP_2_2_MPRIME_LEN 32 |
| 101 | |
| 102 | /* Following Macros take a byte at a time for bit(s) masking */ |
| 103 | /* |
| 104 | * TODO: This has to be changed for DP MST, as multiple stream on |
| 105 | * same port is possible. |
| 106 | * For HDCP2.2 on HDMI and DP SST this value is always 1. |
| 107 | */ |
| 108 | #define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 |
| 109 | #define HDCP_2_2_TXCAP_MASK_LEN 2 |
| 110 | #define HDCP_2_2_RXCAPS_LEN 3 |
| 111 | #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) |
| 112 | #define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) |
| 113 | #define HDCP_2_2_RXINFO_LEN 2 |
| 114 | |
| 115 | /* HDCP1.x compliant device in downstream */ |
| 116 | #define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) |
| 117 | |
| 118 | /* HDCP2.0 Compliant repeater in downstream */ |
| 119 | #define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) |
| 120 | #define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) |
| 121 | #define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) |
| 122 | #define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4) |
| 123 | #define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) |
| 124 | #define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1) |
| 125 | |
| 126 | struct hdcp2_cert_rx { |
| 127 | u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN]; |
| 128 | u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN]; |
| 129 | u8 reserved[2]; |
| 130 | u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN]; |
| 131 | } __packed; |
| 132 | |
| 133 | struct hdcp2_streamid_type { |
| 134 | u8 stream_id; |
| 135 | u8 stream_type; |
| 136 | } __packed; |
| 137 | |
| 138 | /* |
| 139 | * The TxCaps field specified in the HDCP HDMI, DP specs |
| 140 | * This field is big endian as specified in the errata. |
| 141 | */ |
| 142 | struct hdcp2_tx_caps { |
| 143 | /* Transmitter must set this to 0x2 */ |
| 144 | u8 version; |
| 145 | |
| 146 | /* Reserved for HDCP and DP Spec. Read as Zero */ |
| 147 | u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN]; |
| 148 | } __packed; |
| 149 | |
| 150 | /* Main structures for HDCP2.2 protocol communication */ |
| 151 | struct hdcp2_ake_init { |
| 152 | u8 msg_id; |
| 153 | u8 r_tx[HDCP_2_2_RTX_LEN]; |
| 154 | struct hdcp2_tx_caps tx_caps; |
| 155 | } __packed; |
| 156 | |
| 157 | struct hdcp2_ake_send_cert { |
| 158 | u8 msg_id; |
| 159 | struct hdcp2_cert_rx cert_rx; |
| 160 | u8 r_rx[HDCP_2_2_RRX_LEN]; |
| 161 | u8 rx_caps[HDCP_2_2_RXCAPS_LEN]; |
| 162 | } __packed; |
| 163 | |
| 164 | struct hdcp2_ake_no_stored_km { |
| 165 | u8 msg_id; |
| 166 | u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; |
| 167 | } __packed; |
| 168 | |
| 169 | struct hdcp2_ake_stored_km { |
| 170 | u8 msg_id; |
| 171 | u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; |
| 172 | } __packed; |
| 173 | |
| 174 | struct hdcp2_ake_send_hprime { |
| 175 | u8 msg_id; |
| 176 | u8 h_prime[HDCP_2_2_H_PRIME_LEN]; |
| 177 | } __packed; |
| 178 | |
| 179 | struct hdcp2_ake_send_pairing_info { |
| 180 | u8 msg_id; |
| 181 | u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN]; |
| 182 | } __packed; |
| 183 | |
| 184 | struct hdcp2_lc_init { |
| 185 | u8 msg_id; |
| 186 | u8 r_n[HDCP_2_2_RN_LEN]; |
| 187 | } __packed; |
| 188 | |
| 189 | struct hdcp2_lc_send_lprime { |
| 190 | u8 msg_id; |
| 191 | u8 l_prime[HDCP_2_2_L_PRIME_LEN]; |
| 192 | } __packed; |
| 193 | |
| 194 | struct hdcp2_ske_send_eks { |
| 195 | u8 msg_id; |
| 196 | u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN]; |
| 197 | u8 riv[HDCP_2_2_RIV_LEN]; |
| 198 | } __packed; |
| 199 | |
| 200 | struct hdcp2_rep_send_receiverid_list { |
| 201 | u8 msg_id; |
| 202 | u8 rx_info[HDCP_2_2_RXINFO_LEN]; |
| 203 | u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN]; |
| 204 | u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN]; |
| 205 | u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN]; |
| 206 | } __packed; |
| 207 | |
| 208 | struct hdcp2_rep_send_ack { |
| 209 | u8 msg_id; |
| 210 | u8 v[HDCP_2_2_V_PRIME_HALF_LEN]; |
| 211 | } __packed; |
| 212 | |
| 213 | struct hdcp2_rep_stream_manage { |
| 214 | u8 msg_id; |
| 215 | u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN]; |
| 216 | __be16 k; |
| 217 | struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT]; |
| 218 | } __packed; |
| 219 | |
| 220 | struct hdcp2_rep_stream_ready { |
| 221 | u8 msg_id; |
| 222 | u8 m_prime[HDCP_2_2_MPRIME_LEN]; |
| 223 | } __packed; |
| 224 | |
Ramalingam C | 8b44fef | 2018-10-29 15:15:50 +0530 | [diff] [blame] | 225 | /* HDCP2.2 TIMEOUTs in mSec */ |
| 226 | #define HDCP_2_2_CERT_TIMEOUT_MS 100 |
| 227 | #define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 |
| 228 | #define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 |
| 229 | #define HDCP_2_2_PAIRING_TIMEOUT_MS 200 |
| 230 | #define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 |
| 231 | #define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 |
| 232 | #define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 |
| 233 | #define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 |
| 234 | |
| 235 | /* HDMI HDCP2.2 Register Offsets */ |
| 236 | #define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 |
| 237 | #define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 |
| 238 | #define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 |
| 239 | #define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 |
| 240 | #define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 |
| 241 | |
| 242 | #define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) |
| 243 | #define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 |
| 244 | #define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF |
| 245 | #define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 |
| 246 | |
| 247 | /* Below macros take a byte at a time and mask the bit(s) */ |
| 248 | #define HDCP_2_2_HDMI_RXSTATUS_LEN 2 |
| 249 | #define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) |
| 250 | #define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) |
| 251 | #define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) |
| 252 | |
Ramalingam C | 3209706 | 2019-02-15 14:05:04 +0530 | [diff] [blame] | 253 | /* |
| 254 | * Helper functions to convert 24bit big endian hdcp sequence number to |
| 255 | * host format and back |
| 256 | */ |
| 257 | static inline |
Ramalingam C | 0de655c | 2019-05-07 21:57:37 +0530 | [diff] [blame] | 258 | u32 drm_hdcp_be24_to_cpu(const u8 seq_num[HDCP_2_2_SEQ_NUM_LEN]) |
Ramalingam C | 3209706 | 2019-02-15 14:05:04 +0530 | [diff] [blame] | 259 | { |
| 260 | return (u32)(seq_num[2] | seq_num[1] << 8 | seq_num[0] << 16); |
| 261 | } |
| 262 | |
| 263 | static inline |
Ramalingam C | 0de655c | 2019-05-07 21:57:37 +0530 | [diff] [blame] | 264 | void drm_hdcp_cpu_to_be24(u8 seq_num[HDCP_2_2_SEQ_NUM_LEN], u32 val) |
Ramalingam C | 3209706 | 2019-02-15 14:05:04 +0530 | [diff] [blame] | 265 | { |
| 266 | seq_num[0] = val >> 16; |
| 267 | seq_num[1] = val >> 8; |
| 268 | seq_num[2] = val; |
| 269 | } |
| 270 | |
Ramalingam C | 6498bf5 | 2019-05-07 21:57:38 +0530 | [diff] [blame] | 271 | #define DRM_HDCP_SRM_GEN1_MAX_BYTES (5 * 1024) |
| 272 | #define DRM_HDCP_1_4_SRM_ID 0x8 |
| 273 | #define DRM_HDCP_SRM_ID_MASK (0xF << 4) |
| 274 | #define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 |
| 275 | #define DRM_HDCP_1_4_DCP_SIG_SIZE 40 |
| 276 | #define DRM_HDCP_2_SRM_ID 0x9 |
| 277 | #define DRM_HDCP_2_INDICATOR 0x1 |
| 278 | #define DRM_HDCP_2_INDICATOR_MASK 0xF |
| 279 | #define DRM_HDCP_2_VRL_LENGTH_SIZE 3 |
| 280 | #define DRM_HDCP_2_DCP_SIG_SIZE 384 |
| 281 | #define DRM_HDCP_2_NO_OF_DEV_PLUS_RESERVED_SZ 4 |
Ramalingam C | 05f3a6f | 2020-02-12 15:59:39 +0530 | [diff] [blame] | 282 | #define DRM_HDCP_2_KSV_COUNT_2_LSBITS(byte) (((byte) & 0xC0) >> 6) |
Ramalingam C | 6498bf5 | 2019-05-07 21:57:38 +0530 | [diff] [blame] | 283 | |
| 284 | struct hdcp_srm_header { |
| 285 | u8 srm_id; |
| 286 | u8 reserved; |
| 287 | __be16 srm_version; |
| 288 | u8 srm_gen_no; |
| 289 | } __packed; |
| 290 | |
| 291 | struct drm_device; |
Ramalingam C | c16fd9b | 2019-05-07 21:57:40 +0530 | [diff] [blame] | 292 | struct drm_connector; |
Ramalingam C | 6498bf5 | 2019-05-07 21:57:38 +0530 | [diff] [blame] | 293 | |
Ramalingam C | 79643fd | 2020-02-12 15:59:38 +0530 | [diff] [blame] | 294 | int drm_hdcp_check_ksvs_revoked(struct drm_device *dev, |
| 295 | u8 *ksvs, u32 ksv_count); |
Ramalingam C | c16fd9b | 2019-05-07 21:57:40 +0530 | [diff] [blame] | 296 | int drm_connector_attach_content_protection_property( |
Ramalingam C | 7672dbb | 2019-08-01 17:11:14 +0530 | [diff] [blame] | 297 | struct drm_connector *connector, bool hdcp_content_type); |
Ramalingam C | bb5a45d | 2019-08-01 17:11:17 +0530 | [diff] [blame] | 298 | void drm_hdcp_update_content_protection(struct drm_connector *connector, |
| 299 | u64 val); |
Ramalingam C | 7672dbb | 2019-08-01 17:11:14 +0530 | [diff] [blame] | 300 | |
| 301 | /* Content Type classification for HDCP2.2 vs others */ |
| 302 | #define DRM_MODE_HDCP_CONTENT_TYPE0 0 |
| 303 | #define DRM_MODE_HDCP_CONTENT_TYPE1 1 |
| 304 | |
Sean Paul | 495eb7f | 2018-01-08 14:55:38 -0500 | [diff] [blame] | 305 | #endif |