Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 1 | Secure Memory Encryption (SME) and Secure Encrypted Virtualization (SEV) are |
| 2 | features found on AMD processors. |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 3 | |
| 4 | SME provides the ability to mark individual pages of memory as encrypted using |
| 5 | the standard x86 page tables. A page that is marked encrypted will be |
| 6 | automatically decrypted when read from DRAM and encrypted when written to |
| 7 | DRAM. SME can therefore be used to protect the contents of DRAM from physical |
| 8 | attacks on the system. |
| 9 | |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 10 | SEV enables running encrypted virtual machines (VMs) in which the code and data |
| 11 | of the guest VM are secured so that a decrypted version is available only |
| 12 | within the VM itself. SEV guest VMs have the concept of private and shared |
| 13 | memory. Private memory is encrypted with the guest-specific key, while shared |
| 14 | memory may be encrypted with hypervisor key. When SME is enabled, the hypervisor |
| 15 | key is the same key which is used in SME. |
| 16 | |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 17 | A page is encrypted when a page table entry has the encryption bit set (see |
| 18 | below on how to determine its position). The encryption bit can also be |
| 19 | specified in the cr3 register, allowing the PGD table to be encrypted. Each |
| 20 | successive level of page tables can also be encrypted by setting the encryption |
| 21 | bit in the page table entry that points to the next table. This allows the full |
| 22 | page table hierarchy to be encrypted. Note, this means that just because the |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 23 | encryption bit is set in cr3, doesn't imply the full hierarchy is encrypted. |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 24 | Each page table entry in the hierarchy needs to have the encryption bit set to |
| 25 | achieve that. So, theoretically, you could have the encryption bit set in cr3 |
| 26 | so that the PGD is encrypted, but not set the encryption bit in the PGD entry |
| 27 | for a PUD which results in the PUD pointed to by that entry to not be |
| 28 | encrypted. |
| 29 | |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 30 | When SEV is enabled, instruction pages and guest page tables are always treated |
| 31 | as private. All the DMA operations inside the guest must be performed on shared |
| 32 | memory. Since the memory encryption bit is controlled by the guest OS when it |
| 33 | is operating in 64-bit or 32-bit PAE mode, in all other modes the SEV hardware |
| 34 | forces the memory encryption bit to 1. |
| 35 | |
| 36 | Support for SME and SEV can be determined through the CPUID instruction. The |
| 37 | CPUID function 0x8000001f reports information related to SME: |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 38 | |
| 39 | 0x8000001f[eax]: |
| 40 | Bit[0] indicates support for SME |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 41 | Bit[1] indicates support for SEV |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 42 | 0x8000001f[ebx]: |
| 43 | Bits[5:0] pagetable bit number used to activate memory |
| 44 | encryption |
| 45 | Bits[11:6] reduction in physical address space, in bits, when |
| 46 | memory encryption is enabled (this only affects |
| 47 | system physical addresses, not guest physical |
| 48 | addresses) |
| 49 | |
| 50 | If support for SME is present, MSR 0xc00100010 (MSR_K8_SYSCFG) can be used to |
| 51 | determine if SME is enabled and/or to enable memory encryption: |
| 52 | |
| 53 | 0xc0010010: |
| 54 | Bit[23] 0 = memory encryption features are disabled |
| 55 | 1 = memory encryption features are enabled |
| 56 | |
Brijesh Singh | 33e63ac | 2017-10-20 09:30:43 -0500 | [diff] [blame] | 57 | If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if |
| 58 | SEV is active: |
| 59 | |
| 60 | 0xc0010131: |
| 61 | Bit[0] 0 = memory encryption is not active |
| 62 | 1 = memory encryption is active |
| 63 | |
Tom Lendacky | c262f3b | 2017-07-17 16:09:58 -0500 | [diff] [blame] | 64 | Linux relies on BIOS to set this bit if BIOS has determined that the reduction |
| 65 | in the physical address space as a result of enabling memory encryption (see |
| 66 | CPUID information above) will not conflict with the address space resource |
| 67 | requirements for the system. If this bit is not set upon Linux startup then |
| 68 | Linux itself will not set it and memory encryption will not be possible. |
| 69 | |
| 70 | The state of SME in the Linux kernel can be documented as follows: |
| 71 | - Supported: |
| 72 | The CPU supports SME (determined through CPUID instruction). |
| 73 | |
| 74 | - Enabled: |
| 75 | Supported and bit 23 of MSR_K8_SYSCFG is set. |
| 76 | |
| 77 | - Active: |
| 78 | Supported, Enabled and the Linux kernel is actively applying |
| 79 | the encryption bit to page table entries (the SME mask in the |
| 80 | kernel is non-zero). |
| 81 | |
| 82 | SME can also be enabled and activated in the BIOS. If SME is enabled and |
| 83 | activated in the BIOS, then all memory accesses will be encrypted and it will |
| 84 | not be necessary to activate the Linux memory encryption support. If the BIOS |
| 85 | merely enables SME (sets bit 23 of the MSR_K8_SYSCFG), then Linux can activate |
| 86 | memory encryption by default (CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT=y) or |
| 87 | by supplying mem_encrypt=on on the kernel command line. However, if BIOS does |
| 88 | not enable SME, then Linux will not be able to activate memory encryption, even |
| 89 | if configured to do so by default or the mem_encrypt=on command line parameter |
| 90 | is specified. |