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Graeme Gregorye5ce4202012-05-18 16:53:57 +01001/*
2 * Driver for Regulator part of Palmas PMIC Chips
3 *
Graeme Gregory7be859f2013-03-07 13:17:48 +00004 * Copyright 2011-2013 Texas Instruments Inc.
Graeme Gregorye5ce4202012-05-18 16:53:57 +01005 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
Graeme Gregorya7dddf22013-02-23 16:35:40 +00007 * Author: Ian Lartey <ian@slimlogic.co.uk>
Graeme Gregorye5ce4202012-05-18 16:53:57 +01008 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/err.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/driver.h>
22#include <linux/regulator/machine.h>
23#include <linux/slab.h>
24#include <linux/regmap.h>
25#include <linux/mfd/palmas.h>
Graeme Gregorya361cd92012-08-28 13:47:40 +020026#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/regulator/of_regulator.h>
Graeme Gregorye5ce4202012-05-18 16:53:57 +010029
Keerthydbabd622014-05-22 14:48:29 +053030static const struct regulator_linear_range smps_low_ranges[] = {
Nishanth Menon6b7f2d82014-06-04 14:34:31 -050031 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
Keerthydbabd622014-05-22 14:48:29 +053032 REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
33 REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
34 REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
35};
36
37static const struct regulator_linear_range smps_high_ranges[] = {
Nishanth Menon6b7f2d82014-06-04 14:34:31 -050038 REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
Keerthydbabd622014-05-22 14:48:29 +053039 REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
40 REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
41 REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
42};
43
Nishanth Menon6839cd62014-06-30 10:57:37 -050044static struct palmas_regs_info palmas_generic_regs_info[] = {
Graeme Gregorye5ce4202012-05-18 16:53:57 +010045 {
46 .name = "SMPS12",
Laxman Dewangan504382c2013-03-20 19:26:37 +053047 .sname = "smps1-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +010048 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
49 .ctrl_addr = PALMAS_SMPS12_CTRL,
50 .tstep_addr = PALMAS_SMPS12_TSTEP,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +053051 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
Graeme Gregorye5ce4202012-05-18 16:53:57 +010052 },
53 {
54 .name = "SMPS123",
Laxman Dewangan504382c2013-03-20 19:26:37 +053055 .sname = "smps1-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +010056 .vsel_addr = PALMAS_SMPS12_VOLTAGE,
57 .ctrl_addr = PALMAS_SMPS12_CTRL,
58 .tstep_addr = PALMAS_SMPS12_TSTEP,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +053059 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
Graeme Gregorye5ce4202012-05-18 16:53:57 +010060 },
61 {
62 .name = "SMPS3",
Laxman Dewangan504382c2013-03-20 19:26:37 +053063 .sname = "smps3-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +010064 .vsel_addr = PALMAS_SMPS3_VOLTAGE,
65 .ctrl_addr = PALMAS_SMPS3_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +053066 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
Graeme Gregorye5ce4202012-05-18 16:53:57 +010067 },
68 {
69 .name = "SMPS45",
Laxman Dewangan504382c2013-03-20 19:26:37 +053070 .sname = "smps4-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +010071 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
72 .ctrl_addr = PALMAS_SMPS45_CTRL,
73 .tstep_addr = PALMAS_SMPS45_TSTEP,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +053074 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
Graeme Gregorye5ce4202012-05-18 16:53:57 +010075 },
76 {
77 .name = "SMPS457",
Laxman Dewangan504382c2013-03-20 19:26:37 +053078 .sname = "smps4-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +010079 .vsel_addr = PALMAS_SMPS45_VOLTAGE,
80 .ctrl_addr = PALMAS_SMPS45_CTRL,
81 .tstep_addr = PALMAS_SMPS45_TSTEP,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +053082 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
Graeme Gregorye5ce4202012-05-18 16:53:57 +010083 },
84 {
85 .name = "SMPS6",
Laxman Dewangan504382c2013-03-20 19:26:37 +053086 .sname = "smps6-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +010087 .vsel_addr = PALMAS_SMPS6_VOLTAGE,
88 .ctrl_addr = PALMAS_SMPS6_CTRL,
89 .tstep_addr = PALMAS_SMPS6_TSTEP,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +053090 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
Graeme Gregorye5ce4202012-05-18 16:53:57 +010091 },
92 {
93 .name = "SMPS7",
Laxman Dewangan504382c2013-03-20 19:26:37 +053094 .sname = "smps7-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +010095 .vsel_addr = PALMAS_SMPS7_VOLTAGE,
96 .ctrl_addr = PALMAS_SMPS7_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +053097 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
Graeme Gregorye5ce4202012-05-18 16:53:57 +010098 },
99 {
100 .name = "SMPS8",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530101 .sname = "smps8-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100102 .vsel_addr = PALMAS_SMPS8_VOLTAGE,
103 .ctrl_addr = PALMAS_SMPS8_CTRL,
104 .tstep_addr = PALMAS_SMPS8_TSTEP,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530105 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100106 },
107 {
108 .name = "SMPS9",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530109 .sname = "smps9-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100110 .vsel_addr = PALMAS_SMPS9_VOLTAGE,
111 .ctrl_addr = PALMAS_SMPS9_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530112 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100113 },
114 {
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +0530115 .name = "SMPS10_OUT2",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530116 .sname = "smps10-in",
Axel Line31089c2013-04-19 20:33:45 +0800117 .ctrl_addr = PALMAS_SMPS10_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530118 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100119 },
120 {
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +0530121 .name = "SMPS10_OUT1",
122 .sname = "smps10-out2",
123 .ctrl_addr = PALMAS_SMPS10_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530124 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +0530125 },
126 {
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100127 .name = "LDO1",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530128 .sname = "ldo1-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100129 .vsel_addr = PALMAS_LDO1_VOLTAGE,
130 .ctrl_addr = PALMAS_LDO1_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530131 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100132 },
133 {
134 .name = "LDO2",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530135 .sname = "ldo2-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100136 .vsel_addr = PALMAS_LDO2_VOLTAGE,
137 .ctrl_addr = PALMAS_LDO2_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530138 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100139 },
140 {
141 .name = "LDO3",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530142 .sname = "ldo3-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100143 .vsel_addr = PALMAS_LDO3_VOLTAGE,
144 .ctrl_addr = PALMAS_LDO3_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530145 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100146 },
147 {
148 .name = "LDO4",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530149 .sname = "ldo4-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100150 .vsel_addr = PALMAS_LDO4_VOLTAGE,
151 .ctrl_addr = PALMAS_LDO4_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530152 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100153 },
154 {
155 .name = "LDO5",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530156 .sname = "ldo5-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100157 .vsel_addr = PALMAS_LDO5_VOLTAGE,
158 .ctrl_addr = PALMAS_LDO5_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530159 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100160 },
161 {
162 .name = "LDO6",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530163 .sname = "ldo6-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100164 .vsel_addr = PALMAS_LDO6_VOLTAGE,
165 .ctrl_addr = PALMAS_LDO6_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530166 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100167 },
168 {
169 .name = "LDO7",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530170 .sname = "ldo7-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100171 .vsel_addr = PALMAS_LDO7_VOLTAGE,
172 .ctrl_addr = PALMAS_LDO7_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530173 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100174 },
175 {
176 .name = "LDO8",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530177 .sname = "ldo8-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100178 .vsel_addr = PALMAS_LDO8_VOLTAGE,
179 .ctrl_addr = PALMAS_LDO8_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530180 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100181 },
182 {
183 .name = "LDO9",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530184 .sname = "ldo9-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100185 .vsel_addr = PALMAS_LDO9_VOLTAGE,
186 .ctrl_addr = PALMAS_LDO9_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530187 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100188 },
189 {
190 .name = "LDOLN",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530191 .sname = "ldoln-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100192 .vsel_addr = PALMAS_LDOLN_VOLTAGE,
193 .ctrl_addr = PALMAS_LDOLN_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530194 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100195 },
196 {
197 .name = "LDOUSB",
Laxman Dewangan504382c2013-03-20 19:26:37 +0530198 .sname = "ldousb-in",
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100199 .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
200 .ctrl_addr = PALMAS_LDOUSB_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530201 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100202 },
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530203 {
204 .name = "REGEN1",
205 .ctrl_addr = PALMAS_REGEN1_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530206 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530207 },
208 {
209 .name = "REGEN2",
210 .ctrl_addr = PALMAS_REGEN2_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530211 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530212 },
213 {
214 .name = "REGEN3",
215 .ctrl_addr = PALMAS_REGEN3_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530216 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530217 },
218 {
219 .name = "SYSEN1",
220 .ctrl_addr = PALMAS_SYSEN1_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530221 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530222 },
223 {
224 .name = "SYSEN2",
225 .ctrl_addr = PALMAS_SYSEN2_CTRL,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530226 .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530227 },
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100228};
229
Nishanth Menone7cf34e2014-06-30 10:57:35 -0500230static struct palmas_regs_info tps65917_regs_info[] = {
Keerthyd6f83372014-06-18 15:29:00 +0530231 {
232 .name = "SMPS1",
233 .sname = "smps1-in",
234 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
235 .ctrl_addr = TPS65917_SMPS1_CTRL,
236 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
237 },
238 {
239 .name = "SMPS2",
240 .sname = "smps2-in",
241 .vsel_addr = TPS65917_SMPS2_VOLTAGE,
242 .ctrl_addr = TPS65917_SMPS2_CTRL,
243 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
244 },
245 {
246 .name = "SMPS3",
247 .sname = "smps3-in",
248 .vsel_addr = TPS65917_SMPS3_VOLTAGE,
249 .ctrl_addr = TPS65917_SMPS3_CTRL,
250 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
251 },
252 {
253 .name = "SMPS4",
254 .sname = "smps4-in",
255 .vsel_addr = TPS65917_SMPS4_VOLTAGE,
256 .ctrl_addr = TPS65917_SMPS4_CTRL,
257 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
258 },
259 {
260 .name = "SMPS5",
261 .sname = "smps5-in",
262 .vsel_addr = TPS65917_SMPS5_VOLTAGE,
263 .ctrl_addr = TPS65917_SMPS5_CTRL,
264 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
265 },
266 {
Keerthybe035302017-05-23 17:46:56 +0530267 .name = "SMPS12",
268 .sname = "smps1-in",
269 .vsel_addr = TPS65917_SMPS1_VOLTAGE,
270 .ctrl_addr = TPS65917_SMPS1_CTRL,
271 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
272 },
273 {
Keerthyd6f83372014-06-18 15:29:00 +0530274 .name = "LDO1",
275 .sname = "ldo1-in",
276 .vsel_addr = TPS65917_LDO1_VOLTAGE,
277 .ctrl_addr = TPS65917_LDO1_CTRL,
278 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
279 },
280 {
281 .name = "LDO2",
282 .sname = "ldo2-in",
283 .vsel_addr = TPS65917_LDO2_VOLTAGE,
284 .ctrl_addr = TPS65917_LDO2_CTRL,
285 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
286 },
287 {
288 .name = "LDO3",
289 .sname = "ldo3-in",
290 .vsel_addr = TPS65917_LDO3_VOLTAGE,
291 .ctrl_addr = TPS65917_LDO3_CTRL,
292 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
293 },
294 {
295 .name = "LDO4",
296 .sname = "ldo4-in",
297 .vsel_addr = TPS65917_LDO4_VOLTAGE,
298 .ctrl_addr = TPS65917_LDO4_CTRL,
299 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
300 },
301 {
302 .name = "LDO5",
303 .sname = "ldo5-in",
304 .vsel_addr = TPS65917_LDO5_VOLTAGE,
305 .ctrl_addr = TPS65917_LDO5_CTRL,
306 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
307 },
308 {
309 .name = "REGEN1",
310 .ctrl_addr = TPS65917_REGEN1_CTRL,
311 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
312 },
313 {
314 .name = "REGEN2",
315 .ctrl_addr = TPS65917_REGEN2_CTRL,
316 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
317 },
318 {
319 .name = "REGEN3",
320 .ctrl_addr = TPS65917_REGEN3_CTRL,
321 .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
322 },
323};
324
Keerthycac9e912014-06-18 15:28:59 +0530325#define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
326 [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
327 .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
328 .reg_offset = _offset, \
329 .bit_pos = _pos, \
330 }
331
Nishanth Menon4b09e172014-06-30 10:57:34 -0500332static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
Keerthycac9e912014-06-18 15:28:59 +0530333 EXTERNAL_REQUESTOR(REGEN1, 0, 0),
334 EXTERNAL_REQUESTOR(REGEN2, 0, 1),
335 EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
336 EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
337 EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
338 EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
339 EXTERNAL_REQUESTOR(REGEN3, 0, 6),
340 EXTERNAL_REQUESTOR(SMPS12, 1, 0),
341 EXTERNAL_REQUESTOR(SMPS3, 1, 1),
342 EXTERNAL_REQUESTOR(SMPS45, 1, 2),
343 EXTERNAL_REQUESTOR(SMPS6, 1, 3),
344 EXTERNAL_REQUESTOR(SMPS7, 1, 4),
345 EXTERNAL_REQUESTOR(SMPS8, 1, 5),
346 EXTERNAL_REQUESTOR(SMPS9, 1, 6),
347 EXTERNAL_REQUESTOR(SMPS10, 1, 7),
348 EXTERNAL_REQUESTOR(LDO1, 2, 0),
349 EXTERNAL_REQUESTOR(LDO2, 2, 1),
350 EXTERNAL_REQUESTOR(LDO3, 2, 2),
351 EXTERNAL_REQUESTOR(LDO4, 2, 3),
352 EXTERNAL_REQUESTOR(LDO5, 2, 4),
353 EXTERNAL_REQUESTOR(LDO6, 2, 5),
354 EXTERNAL_REQUESTOR(LDO7, 2, 6),
355 EXTERNAL_REQUESTOR(LDO8, 2, 7),
356 EXTERNAL_REQUESTOR(LDO9, 3, 0),
357 EXTERNAL_REQUESTOR(LDOLN, 3, 1),
358 EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
359};
360
Keerthyd6f83372014-06-18 15:29:00 +0530361#define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
362 [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
363 .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
364 .reg_offset = _offset, \
365 .bit_pos = _pos, \
366 }
367
368static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
369 EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
370 EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
371 EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
372 EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
373 EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
374 EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
375 EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
376 EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
Keerthybe035302017-05-23 17:46:56 +0530377 EXTERNAL_REQUESTOR_TPS65917(SMPS12, 1, 5),
Keerthyd6f83372014-06-18 15:29:00 +0530378 EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
379 EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
380 EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
381 EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
382 EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
383};
384
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530385static unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
386
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100387#define SMPS_CTRL_MODE_OFF 0x00
388#define SMPS_CTRL_MODE_ON 0x01
389#define SMPS_CTRL_MODE_ECO 0x02
390#define SMPS_CTRL_MODE_PWM 0x03
391
Laxman Dewangan0f45aa82013-09-04 15:20:06 +0530392#define PALMAS_SMPS_NUM_VOLTAGES 122
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100393#define PALMAS_SMPS10_NUM_VOLTAGES 2
394#define PALMAS_LDO_NUM_VOLTAGES 50
395
396#define SMPS10_VSEL (1<<3)
397#define SMPS10_BOOST_EN (1<<2)
398#define SMPS10_BYPASS_EN (1<<1)
399#define SMPS10_SWITCH_EN (1<<0)
400
401#define REGULATOR_SLAVE 0
402
403static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
404 unsigned int *dest)
405{
406 unsigned int addr;
407
408 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
409
410 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
411}
412
413static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
414 unsigned int value)
415{
416 unsigned int addr;
417
418 addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
419
420 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
421}
422
423static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
424 unsigned int *dest)
425{
426 unsigned int addr;
427
428 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
429
430 return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
431}
432
433static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
434 unsigned int value)
435{
436 unsigned int addr;
437
438 addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
439
440 return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
441}
442
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100443static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
444{
Nishanth Menoncf910b62014-06-30 10:57:36 -0500445 int id = rdev_get_id(dev);
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100446 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
Keerthycac9e912014-06-18 15:28:59 +0530447 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500448 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100449 unsigned int reg;
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +0530450 bool rail_enable = true;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100451
Nishanth Menoncf910b62014-06-30 10:57:36 -0500452 palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, &reg);
Keerthycac9e912014-06-18 15:28:59 +0530453
Axel Lin999f0c72012-06-07 17:08:21 +0800454 reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100455
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +0530456 if (reg == SMPS_CTRL_MODE_OFF)
457 rail_enable = false;
458
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100459 switch (mode) {
460 case REGULATOR_MODE_NORMAL:
461 reg |= SMPS_CTRL_MODE_ON;
462 break;
463 case REGULATOR_MODE_IDLE:
464 reg |= SMPS_CTRL_MODE_ECO;
465 break;
466 case REGULATOR_MODE_FAST:
467 reg |= SMPS_CTRL_MODE_PWM;
468 break;
469 default:
470 return -EINVAL;
471 }
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100472
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +0530473 pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
474 if (rail_enable)
Nishanth Menoncf910b62014-06-30 10:57:36 -0500475 palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
Nishanth Menon318dbb02014-06-20 12:26:23 -0500476
477 /* Switch the enable value to ensure this is used for enable */
478 pmic->desc[id].enable_val = pmic->current_reg_mode[id];
479
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100480 return 0;
481}
482
483static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
484{
485 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
486 int id = rdev_get_id(dev);
487 unsigned int reg;
488
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +0530489 reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100490
491 switch (reg) {
492 case SMPS_CTRL_MODE_ON:
493 return REGULATOR_MODE_NORMAL;
494 case SMPS_CTRL_MODE_ECO:
495 return REGULATOR_MODE_IDLE;
496 case SMPS_CTRL_MODE_PWM:
497 return REGULATOR_MODE_FAST;
498 }
499
500 return 0;
501}
502
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530503static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
504 int ramp_delay)
505{
Nishanth Menoncf910b62014-06-30 10:57:36 -0500506 int id = rdev_get_id(rdev);
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530507 struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
Keerthycac9e912014-06-18 15:28:59 +0530508 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500509 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530510 unsigned int reg = 0;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530511 int ret;
512
Axel Linf22c2ba2013-04-19 14:18:48 +0800513 /* SMPS3 and SMPS7 do not have tstep_addr setting */
514 switch (id) {
515 case PALMAS_REG_SMPS3:
516 case PALMAS_REG_SMPS7:
517 return 0;
518 }
519
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530520 if (ramp_delay <= 0)
521 reg = 0;
Axel Lin0ea34b52013-04-22 18:22:49 +0800522 else if (ramp_delay <= 2500)
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530523 reg = 3;
Axel Lin0ea34b52013-04-22 18:22:49 +0800524 else if (ramp_delay <= 5000)
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530525 reg = 2;
526 else
527 reg = 1;
528
Nishanth Menoncf910b62014-06-30 10:57:36 -0500529 ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530530 if (ret < 0) {
531 dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
532 return ret;
533 }
534
535 pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
536 return ret;
537}
538
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530539static const struct regulator_ops palmas_ops_smps = {
Keerthydbabd622014-05-22 14:48:29 +0530540 .is_enabled = regulator_is_enabled_regmap,
541 .enable = regulator_enable_regmap,
542 .disable = regulator_disable_regmap,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100543 .set_mode = palmas_set_mode_smps,
544 .get_mode = palmas_get_mode_smps,
Axel Linbdc4baa2012-11-29 10:01:44 +0800545 .get_voltage_sel = regulator_get_voltage_sel_regmap,
546 .set_voltage_sel = regulator_set_voltage_sel_regmap,
Keerthydbabd622014-05-22 14:48:29 +0530547 .list_voltage = regulator_list_voltage_linear_range,
548 .map_voltage = regulator_map_voltage_linear_range,
549 .set_voltage_time_sel = regulator_set_voltage_time_sel,
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +0530550 .set_ramp_delay = palmas_smps_set_ramp_delay,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100551};
552
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530553static const struct regulator_ops palmas_ops_ext_control_smps = {
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530554 .set_mode = palmas_set_mode_smps,
555 .get_mode = palmas_get_mode_smps,
556 .get_voltage_sel = regulator_get_voltage_sel_regmap,
557 .set_voltage_sel = regulator_set_voltage_sel_regmap,
Keerthydbabd622014-05-22 14:48:29 +0530558 .list_voltage = regulator_list_voltage_linear_range,
559 .map_voltage = regulator_map_voltage_linear_range,
560 .set_voltage_time_sel = regulator_set_voltage_time_sel,
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530561 .set_ramp_delay = palmas_smps_set_ramp_delay,
562};
563
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530564static const struct regulator_ops palmas_ops_smps10 = {
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100565 .is_enabled = regulator_is_enabled_regmap,
566 .enable = regulator_enable_regmap,
567 .disable = regulator_disable_regmap,
568 .get_voltage_sel = regulator_get_voltage_sel_regmap,
569 .set_voltage_sel = regulator_set_voltage_sel_regmap,
Axel Lin8029a002012-05-22 12:26:42 +0800570 .list_voltage = regulator_list_voltage_linear,
571 .map_voltage = regulator_map_voltage_linear,
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +0530572 .set_bypass = regulator_set_bypass_regmap,
573 .get_bypass = regulator_get_bypass_regmap,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100574};
575
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530576static const struct regulator_ops tps65917_ops_smps = {
Keerthyd6f83372014-06-18 15:29:00 +0530577 .is_enabled = regulator_is_enabled_regmap,
578 .enable = regulator_enable_regmap,
579 .disable = regulator_disable_regmap,
580 .set_mode = palmas_set_mode_smps,
581 .get_mode = palmas_get_mode_smps,
582 .get_voltage_sel = regulator_get_voltage_sel_regmap,
583 .set_voltage_sel = regulator_set_voltage_sel_regmap,
584 .list_voltage = regulator_list_voltage_linear_range,
585 .map_voltage = regulator_map_voltage_linear_range,
586 .set_voltage_time_sel = regulator_set_voltage_time_sel,
587};
588
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530589static const struct regulator_ops tps65917_ops_ext_control_smps = {
Keerthyd6f83372014-06-18 15:29:00 +0530590 .set_mode = palmas_set_mode_smps,
591 .get_mode = palmas_get_mode_smps,
592 .get_voltage_sel = regulator_get_voltage_sel_regmap,
593 .set_voltage_sel = regulator_set_voltage_sel_regmap,
594 .list_voltage = regulator_list_voltage_linear_range,
595 .map_voltage = regulator_map_voltage_linear_range,
596};
597
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100598static int palmas_is_enabled_ldo(struct regulator_dev *dev)
599{
Nishanth Menoncf910b62014-06-30 10:57:36 -0500600 int id = rdev_get_id(dev);
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100601 struct palmas_pmic *pmic = rdev_get_drvdata(dev);
Keerthycac9e912014-06-18 15:28:59 +0530602 struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500603 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100604 unsigned int reg;
605
Nishanth Menoncf910b62014-06-30 10:57:36 -0500606 palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, &reg);
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100607
608 reg &= PALMAS_LDO1_CTRL_STATUS;
609
610 return !!(reg);
611}
612
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530613static const struct regulator_ops palmas_ops_ldo = {
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100614 .is_enabled = palmas_is_enabled_ldo,
615 .enable = regulator_enable_regmap,
616 .disable = regulator_disable_regmap,
Axel Lin4a247a92012-07-18 12:34:08 +0800617 .get_voltage_sel = regulator_get_voltage_sel_regmap,
618 .set_voltage_sel = regulator_set_voltage_sel_regmap,
Axel Lin9119ff62012-11-27 10:27:34 +0800619 .list_voltage = regulator_list_voltage_linear,
620 .map_voltage = regulator_map_voltage_linear,
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100621};
622
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530623static const struct regulator_ops palmas_ops_ldo9 = {
Keerthyb554e142015-12-14 12:06:55 +0530624 .is_enabled = palmas_is_enabled_ldo,
625 .enable = regulator_enable_regmap,
626 .disable = regulator_disable_regmap,
627 .get_voltage_sel = regulator_get_voltage_sel_regmap,
628 .set_voltage_sel = regulator_set_voltage_sel_regmap,
629 .list_voltage = regulator_list_voltage_linear,
630 .map_voltage = regulator_map_voltage_linear,
631 .set_bypass = regulator_set_bypass_regmap,
632 .get_bypass = regulator_get_bypass_regmap,
633};
634
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530635static const struct regulator_ops palmas_ops_ext_control_ldo = {
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530636 .get_voltage_sel = regulator_get_voltage_sel_regmap,
637 .set_voltage_sel = regulator_set_voltage_sel_regmap,
638 .list_voltage = regulator_list_voltage_linear,
639 .map_voltage = regulator_map_voltage_linear,
640};
641
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530642static const struct regulator_ops palmas_ops_extreg = {
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530643 .is_enabled = regulator_is_enabled_regmap,
644 .enable = regulator_enable_regmap,
645 .disable = regulator_disable_regmap,
646};
647
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530648static const struct regulator_ops palmas_ops_ext_control_extreg = {
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530649};
650
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530651static const struct regulator_ops tps65917_ops_ldo = {
Keerthyd6f83372014-06-18 15:29:00 +0530652 .is_enabled = palmas_is_enabled_ldo,
653 .enable = regulator_enable_regmap,
654 .disable = regulator_disable_regmap,
655 .get_voltage_sel = regulator_get_voltage_sel_regmap,
656 .set_voltage_sel = regulator_set_voltage_sel_regmap,
657 .list_voltage = regulator_list_voltage_linear,
658 .map_voltage = regulator_map_voltage_linear,
659 .set_voltage_time_sel = regulator_set_voltage_time_sel,
660};
661
Bhumika Goyal0e5a768002017-01-28 20:23:55 +0530662static const struct regulator_ops tps65917_ops_ldo_1_2 = {
Keerthyb554e142015-12-14 12:06:55 +0530663 .is_enabled = palmas_is_enabled_ldo,
664 .enable = regulator_enable_regmap,
665 .disable = regulator_disable_regmap,
666 .get_voltage_sel = regulator_get_voltage_sel_regmap,
667 .set_voltage_sel = regulator_set_voltage_sel_regmap,
668 .list_voltage = regulator_list_voltage_linear,
669 .map_voltage = regulator_map_voltage_linear,
670 .set_voltage_time_sel = regulator_set_voltage_time_sel,
671 .set_bypass = regulator_set_bypass_regmap,
672 .get_bypass = regulator_get_bypass_regmap,
673};
674
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530675static int palmas_regulator_config_external(struct palmas *palmas, int id,
676 struct palmas_reg_init *reg_init)
677{
Nishanth Menoncf910b62014-06-30 10:57:36 -0500678 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
679 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530680 int ret;
681
Nishanth Menoncf910b62014-06-30 10:57:36 -0500682 ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
683 reg_init->roof_floor, true);
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530684 if (ret < 0)
685 dev_err(palmas->dev,
686 "Ext control config for regulator %d failed %d\n",
687 id, ret);
688 return ret;
689}
690
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100691/*
692 * setup the hardware based sleep configuration of the SMPS/LDO regulators
693 * from the platform data. This is different to the software based control
694 * supported by the regulator framework as it is controlled by toggling
695 * pins on the PMIC such as PREQ, SYSEN, ...
696 */
697static int palmas_smps_init(struct palmas *palmas, int id,
698 struct palmas_reg_init *reg_init)
699{
700 unsigned int reg;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100701 int ret;
Keerthycac9e912014-06-18 15:28:59 +0530702 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500703 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
704 unsigned int addr = rinfo->ctrl_addr;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100705
706 ret = palmas_smps_read(palmas, addr, &reg);
707 if (ret)
708 return ret;
709
Axel Linfedd89b2012-06-06 20:01:38 +0800710 switch (id) {
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +0530711 case PALMAS_REG_SMPS10_OUT1:
712 case PALMAS_REG_SMPS10_OUT2:
Laxman Dewangan30590d02013-04-17 15:13:11 +0530713 reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
714 if (reg_init->mode_sleep)
Axel Linfedd89b2012-06-06 20:01:38 +0800715 reg |= reg_init->mode_sleep <<
716 PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
Axel Linfedd89b2012-06-06 20:01:38 +0800717 break;
718 default:
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100719 if (reg_init->warm_reset)
720 reg |= PALMAS_SMPS12_CTRL_WR_S;
Laxman Dewangan30590d02013-04-17 15:13:11 +0530721 else
722 reg &= ~PALMAS_SMPS12_CTRL_WR_S;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100723
724 if (reg_init->roof_floor)
725 reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
Laxman Dewangan30590d02013-04-17 15:13:11 +0530726 else
727 reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100728
Laxman Dewangan30590d02013-04-17 15:13:11 +0530729 reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
730 if (reg_init->mode_sleep)
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100731 reg |= reg_init->mode_sleep <<
732 PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100733 }
Axel Linfedd89b2012-06-06 20:01:38 +0800734
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100735 ret = palmas_smps_write(palmas, addr, reg);
736 if (ret)
737 return ret;
738
Nishanth Menoncf910b62014-06-30 10:57:36 -0500739 if (rinfo->vsel_addr && reg_init->vsel) {
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100740
741 reg = reg_init->vsel;
742
Nishanth Menoncf910b62014-06-30 10:57:36 -0500743 ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100744 if (ret)
745 return ret;
746 }
747
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530748 if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
749 (id != PALMAS_REG_SMPS10_OUT2)) {
750 /* Enable externally controlled regulator */
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530751 ret = palmas_smps_read(palmas, addr, &reg);
752 if (ret < 0)
753 return ret;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100754
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530755 if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
756 reg |= SMPS_CTRL_MODE_ON;
757 ret = palmas_smps_write(palmas, addr, reg);
758 if (ret < 0)
759 return ret;
760 }
761 return palmas_regulator_config_external(palmas, id, reg_init);
762 }
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100763 return 0;
764}
765
766static int palmas_ldo_init(struct palmas *palmas, int id,
767 struct palmas_reg_init *reg_init)
768{
769 unsigned int reg;
770 unsigned int addr;
771 int ret;
Keerthycac9e912014-06-18 15:28:59 +0530772 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500773 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
Keerthycac9e912014-06-18 15:28:59 +0530774
Nishanth Menoncf910b62014-06-30 10:57:36 -0500775 addr = rinfo->ctrl_addr;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100776
Axel Lin2735dae2012-07-18 12:31:59 +0800777 ret = palmas_ldo_read(palmas, addr, &reg);
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100778 if (ret)
779 return ret;
780
781 if (reg_init->warm_reset)
782 reg |= PALMAS_LDO1_CTRL_WR_S;
Laxman Dewangan30590d02013-04-17 15:13:11 +0530783 else
784 reg &= ~PALMAS_LDO1_CTRL_WR_S;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100785
786 if (reg_init->mode_sleep)
787 reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
Laxman Dewangan30590d02013-04-17 15:13:11 +0530788 else
789 reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100790
Axel Lin2735dae2012-07-18 12:31:59 +0800791 ret = palmas_ldo_write(palmas, addr, reg);
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100792 if (ret)
793 return ret;
794
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530795 if (reg_init->roof_floor) {
796 /* Enable externally controlled regulator */
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530797 ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
798 addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
799 PALMAS_LDO1_CTRL_MODE_ACTIVE);
800 if (ret < 0) {
801 dev_err(palmas->dev,
802 "LDO Register 0x%02x update failed %d\n",
803 addr, ret);
804 return ret;
805 }
806 return palmas_regulator_config_external(palmas, id, reg_init);
807 }
Graeme Gregorye5ce4202012-05-18 16:53:57 +0100808 return 0;
809}
810
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530811static int palmas_extreg_init(struct palmas *palmas, int id,
812 struct palmas_reg_init *reg_init)
813{
814 unsigned int addr;
815 int ret;
816 unsigned int val = 0;
Keerthycac9e912014-06-18 15:28:59 +0530817 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500818 struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
Keerthycac9e912014-06-18 15:28:59 +0530819
Nishanth Menoncf910b62014-06-30 10:57:36 -0500820 addr = rinfo->ctrl_addr;
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530821
822 if (reg_init->mode_sleep)
823 val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
824
825 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
826 addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
827 if (ret < 0) {
828 dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
829 addr, ret);
830 return ret;
831 }
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530832
833 if (reg_init->roof_floor) {
834 /* Enable externally controlled regulator */
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530835 ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
836 addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
837 PALMAS_REGEN1_CTRL_MODE_ACTIVE);
838 if (ret < 0) {
839 dev_err(palmas->dev,
840 "Resource Register 0x%02x update failed %d\n",
841 addr, ret);
842 return ret;
843 }
844 return palmas_regulator_config_external(palmas, id, reg_init);
845 }
Laxman Dewanganaa07f022013-04-17 15:13:12 +0530846 return 0;
847}
848
Laxman Dewangan17c11a72013-04-17 15:13:13 +0530849static void palmas_enable_ldo8_track(struct palmas *palmas)
850{
851 unsigned int reg;
852 unsigned int addr;
853 int ret;
Keerthycac9e912014-06-18 15:28:59 +0530854 struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500855 struct palmas_regs_info *rinfo;
Keerthycac9e912014-06-18 15:28:59 +0530856
Nishanth Menoncf910b62014-06-30 10:57:36 -0500857 rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
858 addr = rinfo->ctrl_addr;
Laxman Dewangan17c11a72013-04-17 15:13:13 +0530859
860 ret = palmas_ldo_read(palmas, addr, &reg);
861 if (ret) {
862 dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
863 return;
864 }
865
866 reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
867 ret = palmas_ldo_write(palmas, addr, reg);
868 if (ret < 0) {
869 dev_err(palmas->dev, "Error in enabling tracking mode\n");
870 return;
871 }
872 /*
873 * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
874 * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
875 * and can be set from 0.45 to 1.65 V.
876 */
Nishanth Menoncf910b62014-06-30 10:57:36 -0500877 addr = rinfo->vsel_addr;
Laxman Dewangan17c11a72013-04-17 15:13:13 +0530878 ret = palmas_ldo_read(palmas, addr, &reg);
879 if (ret) {
880 dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
881 return;
882 }
883
884 reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
885 ret = palmas_ldo_write(palmas, addr, reg);
886 if (ret < 0)
887 dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
888
889 return;
890}
891
Keerthycac9e912014-06-18 15:28:59 +0530892static int palmas_ldo_registration(struct palmas_pmic *pmic,
893 struct palmas_pmic_driver_data *ddata,
894 struct palmas_pmic_platform_data *pdata,
895 const char *pdev_name,
896 struct regulator_config config)
Graeme Gregorya361cd92012-08-28 13:47:40 +0200897{
Keerthycac9e912014-06-18 15:28:59 +0530898 int id, ret;
899 struct regulator_dev *rdev;
900 struct palmas_reg_init *reg_init;
Nishanth Menoncf910b62014-06-30 10:57:36 -0500901 struct palmas_regs_info *rinfo;
Nishanth Menon429222d2014-06-30 10:57:38 -0500902 struct regulator_desc *desc;
Graeme Gregorya361cd92012-08-28 13:47:40 +0200903
Keerthycac9e912014-06-18 15:28:59 +0530904 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
905 if (pdata && pdata->reg_init[id])
906 reg_init = pdata->reg_init[id];
907 else
908 reg_init = NULL;
Graeme Gregorya361cd92012-08-28 13:47:40 +0200909
Nishanth Menoncf910b62014-06-30 10:57:36 -0500910 rinfo = &ddata->palmas_regs_info[id];
Keerthycac9e912014-06-18 15:28:59 +0530911 /* Miss out regulators which are not available due
912 * to alternate functions.
913 */
Graeme Gregorya361cd92012-08-28 13:47:40 +0200914
Keerthycac9e912014-06-18 15:28:59 +0530915 /* Register the regulators */
Nishanth Menon429222d2014-06-30 10:57:38 -0500916 desc = &pmic->desc[id];
917 desc->name = rinfo->name;
918 desc->id = id;
919 desc->type = REGULATOR_VOLTAGE;
920 desc->owner = THIS_MODULE;
Graeme Gregorya361cd92012-08-28 13:47:40 +0200921
Keerthycac9e912014-06-18 15:28:59 +0530922 if (id < PALMAS_REG_REGEN1) {
Nishanth Menon429222d2014-06-30 10:57:38 -0500923 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
Keerthycac9e912014-06-18 15:28:59 +0530924 if (reg_init && reg_init->roof_floor)
Nishanth Menon429222d2014-06-30 10:57:38 -0500925 desc->ops = &palmas_ops_ext_control_ldo;
Keerthycac9e912014-06-18 15:28:59 +0530926 else
Nishanth Menon429222d2014-06-30 10:57:38 -0500927 desc->ops = &palmas_ops_ldo;
928 desc->min_uV = 900000;
929 desc->uV_step = 50000;
930 desc->linear_min_sel = 1;
931 desc->enable_time = 500;
932 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
933 rinfo->vsel_addr);
934 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
935 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
936 rinfo->ctrl_addr);
937 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
Graeme Gregorya361cd92012-08-28 13:47:40 +0200938
Keerthycac9e912014-06-18 15:28:59 +0530939 /* Check if LDO8 is in tracking mode or not */
940 if (pdata && (id == PALMAS_REG_LDO8) &&
941 pdata->enable_ldo8_tracking) {
942 palmas_enable_ldo8_track(pmic->palmas);
Nishanth Menon429222d2014-06-30 10:57:38 -0500943 desc->min_uV = 450000;
944 desc->uV_step = 25000;
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530945 }
Keerthycac9e912014-06-18 15:28:59 +0530946
947 /* LOD6 in vibrator mode will have enable time 2000us */
948 if (pdata && pdata->ldo6_vibrator &&
949 (id == PALMAS_REG_LDO6))
Nishanth Menon429222d2014-06-30 10:57:38 -0500950 desc->enable_time = 2000;
Keerthyb554e142015-12-14 12:06:55 +0530951
952 if (id == PALMAS_REG_LDO9) {
953 desc->ops = &palmas_ops_ldo9;
954 desc->bypass_reg = desc->enable_reg;
Nishanth Menone0341f12016-04-26 11:36:42 -0500955 desc->bypass_val_on =
956 PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
Keerthyb554e142015-12-14 12:06:55 +0530957 desc->bypass_mask =
958 PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
959 }
Keerthycac9e912014-06-18 15:28:59 +0530960 } else {
Keerthye999c722015-03-17 15:56:05 +0530961 if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3)
962 continue;
963
Nishanth Menon429222d2014-06-30 10:57:38 -0500964 desc->n_voltages = 1;
Keerthycac9e912014-06-18 15:28:59 +0530965 if (reg_init && reg_init->roof_floor)
Nishanth Menon429222d2014-06-30 10:57:38 -0500966 desc->ops = &palmas_ops_ext_control_extreg;
Keerthycac9e912014-06-18 15:28:59 +0530967 else
Nishanth Menon429222d2014-06-30 10:57:38 -0500968 desc->ops = &palmas_ops_extreg;
969 desc->enable_reg =
Keerthycac9e912014-06-18 15:28:59 +0530970 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
Nishanth Menoncf910b62014-06-30 10:57:36 -0500971 rinfo->ctrl_addr);
Nishanth Menon429222d2014-06-30 10:57:38 -0500972 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +0530973 }
Graeme Gregorya361cd92012-08-28 13:47:40 +0200974
Keerthycac9e912014-06-18 15:28:59 +0530975 if (pdata)
976 config.init_data = pdata->reg_data[id];
977 else
978 config.init_data = NULL;
Graeme Gregorya361cd92012-08-28 13:47:40 +0200979
Nishanth Menon429222d2014-06-30 10:57:38 -0500980 desc->supply_name = rinfo->sname;
Keerthycac9e912014-06-18 15:28:59 +0530981 config.of_node = ddata->palmas_matches[id].of_node;
Graeme Gregorya361cd92012-08-28 13:47:40 +0200982
Nishanth Menon429222d2014-06-30 10:57:38 -0500983 rdev = devm_regulator_register(pmic->dev, desc, &config);
Keerthycac9e912014-06-18 15:28:59 +0530984 if (IS_ERR(rdev)) {
985 dev_err(pmic->dev,
986 "failed to register %s regulator\n",
987 pdev_name);
988 return PTR_ERR(rdev);
989 }
990
991 /* Save regulator for cleanup */
992 pmic->rdev[id] = rdev;
993
994 /* Initialise sleep/init values from platform data */
995 if (pdata) {
996 reg_init = pdata->reg_init[id];
997 if (reg_init) {
998 if (id <= ddata->ldo_end)
999 ret = palmas_ldo_init(pmic->palmas, id,
1000 reg_init);
1001 else
1002 ret = palmas_extreg_init(pmic->palmas,
1003 id, reg_init);
1004 if (ret)
1005 return ret;
1006 }
1007 }
Graeme Gregorya361cd92012-08-28 13:47:40 +02001008 }
1009
Keerthycac9e912014-06-18 15:28:59 +05301010 return 0;
Graeme Gregorya361cd92012-08-28 13:47:40 +02001011}
1012
Keerthyd6f83372014-06-18 15:29:00 +05301013static int tps65917_ldo_registration(struct palmas_pmic *pmic,
1014 struct palmas_pmic_driver_data *ddata,
1015 struct palmas_pmic_platform_data *pdata,
1016 const char *pdev_name,
1017 struct regulator_config config)
1018{
1019 int id, ret;
1020 struct regulator_dev *rdev;
1021 struct palmas_reg_init *reg_init;
Nishanth Menoncf910b62014-06-30 10:57:36 -05001022 struct palmas_regs_info *rinfo;
Nishanth Menon429222d2014-06-30 10:57:38 -05001023 struct regulator_desc *desc;
Keerthyd6f83372014-06-18 15:29:00 +05301024
1025 for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
1026 if (pdata && pdata->reg_init[id])
1027 reg_init = pdata->reg_init[id];
1028 else
1029 reg_init = NULL;
1030
1031 /* Miss out regulators which are not available due
1032 * to alternate functions.
1033 */
Nishanth Menoncf910b62014-06-30 10:57:36 -05001034 rinfo = &ddata->palmas_regs_info[id];
Keerthyd6f83372014-06-18 15:29:00 +05301035
1036 /* Register the regulators */
Nishanth Menon429222d2014-06-30 10:57:38 -05001037 desc = &pmic->desc[id];
1038 desc->name = rinfo->name;
1039 desc->id = id;
1040 desc->type = REGULATOR_VOLTAGE;
1041 desc->owner = THIS_MODULE;
Keerthyd6f83372014-06-18 15:29:00 +05301042
1043 if (id < TPS65917_REG_REGEN1) {
Nishanth Menon429222d2014-06-30 10:57:38 -05001044 desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
Keerthyd6f83372014-06-18 15:29:00 +05301045 if (reg_init && reg_init->roof_floor)
Nishanth Menon429222d2014-06-30 10:57:38 -05001046 desc->ops = &palmas_ops_ext_control_ldo;
Keerthyd6f83372014-06-18 15:29:00 +05301047 else
Nishanth Menon429222d2014-06-30 10:57:38 -05001048 desc->ops = &tps65917_ops_ldo;
1049 desc->min_uV = 900000;
1050 desc->uV_step = 50000;
1051 desc->linear_min_sel = 1;
1052 desc->enable_time = 500;
1053 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1054 rinfo->vsel_addr);
1055 desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
1056 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
1057 rinfo->ctrl_addr);
1058 desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
Keerthyd6f83372014-06-18 15:29:00 +05301059 /*
1060 * To be confirmed. Discussion on going with PMIC Team.
1061 * It is of the order of ~60mV/uS.
1062 */
Nishanth Menon429222d2014-06-30 10:57:38 -05001063 desc->ramp_delay = 2500;
Keerthyb554e142015-12-14 12:06:55 +05301064 if (id == TPS65917_REG_LDO1 ||
1065 id == TPS65917_REG_LDO2) {
1066 desc->ops = &tps65917_ops_ldo_1_2;
1067 desc->bypass_reg = desc->enable_reg;
Nishanth Menone0341f12016-04-26 11:36:42 -05001068 desc->bypass_val_on =
1069 TPS65917_LDO1_CTRL_BYPASS_EN;
Keerthyb554e142015-12-14 12:06:55 +05301070 desc->bypass_mask =
1071 TPS65917_LDO1_CTRL_BYPASS_EN;
1072 }
Keerthyd6f83372014-06-18 15:29:00 +05301073 } else {
Nishanth Menon429222d2014-06-30 10:57:38 -05001074 desc->n_voltages = 1;
Keerthyd6f83372014-06-18 15:29:00 +05301075 if (reg_init && reg_init->roof_floor)
Nishanth Menon429222d2014-06-30 10:57:38 -05001076 desc->ops = &palmas_ops_ext_control_extreg;
Keerthyd6f83372014-06-18 15:29:00 +05301077 else
Nishanth Menon429222d2014-06-30 10:57:38 -05001078 desc->ops = &palmas_ops_extreg;
1079 desc->enable_reg =
Keerthyd6f83372014-06-18 15:29:00 +05301080 PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
Nishanth Menoncf910b62014-06-30 10:57:36 -05001081 rinfo->ctrl_addr);
Nishanth Menon429222d2014-06-30 10:57:38 -05001082 desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
Keerthyd6f83372014-06-18 15:29:00 +05301083 }
1084
1085 if (pdata)
1086 config.init_data = pdata->reg_data[id];
1087 else
1088 config.init_data = NULL;
1089
Nishanth Menon429222d2014-06-30 10:57:38 -05001090 desc->supply_name = rinfo->sname;
Keerthyd6f83372014-06-18 15:29:00 +05301091 config.of_node = ddata->palmas_matches[id].of_node;
1092
Nishanth Menon429222d2014-06-30 10:57:38 -05001093 rdev = devm_regulator_register(pmic->dev, desc, &config);
Keerthyd6f83372014-06-18 15:29:00 +05301094 if (IS_ERR(rdev)) {
1095 dev_err(pmic->dev,
1096 "failed to register %s regulator\n",
1097 pdev_name);
1098 return PTR_ERR(rdev);
1099 }
1100
1101 /* Save regulator for cleanup */
1102 pmic->rdev[id] = rdev;
1103
1104 /* Initialise sleep/init values from platform data */
1105 if (pdata) {
1106 reg_init = pdata->reg_init[id];
1107 if (reg_init) {
1108 if (id < TPS65917_REG_REGEN1)
1109 ret = palmas_ldo_init(pmic->palmas,
1110 id, reg_init);
1111 else
1112 ret = palmas_extreg_init(pmic->palmas,
1113 id, reg_init);
1114 if (ret)
1115 return ret;
1116 }
1117 }
1118 }
1119
1120 return 0;
1121}
1122
Keerthycac9e912014-06-18 15:28:59 +05301123static int palmas_smps_registration(struct palmas_pmic *pmic,
1124 struct palmas_pmic_driver_data *ddata,
1125 struct palmas_pmic_platform_data *pdata,
1126 const char *pdev_name,
1127 struct regulator_config config)
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001128{
Keerthycac9e912014-06-18 15:28:59 +05301129 int id, ret;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001130 unsigned int addr, reg;
Keerthycac9e912014-06-18 15:28:59 +05301131 struct regulator_dev *rdev;
1132 struct palmas_reg_init *reg_init;
Nishanth Menoncf910b62014-06-30 10:57:36 -05001133 struct palmas_regs_info *rinfo;
Nishanth Menon429222d2014-06-30 10:57:38 -05001134 struct regulator_desc *desc;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001135
Keerthycac9e912014-06-18 15:28:59 +05301136 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301137 bool ramp_delay_support = false;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001138
1139 /*
1140 * Miss out regulators which are not available due
1141 * to slaving configurations.
1142 */
1143 switch (id) {
1144 case PALMAS_REG_SMPS12:
1145 case PALMAS_REG_SMPS3:
1146 if (pmic->smps123)
1147 continue;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301148 if (id == PALMAS_REG_SMPS12)
1149 ramp_delay_support = true;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001150 break;
1151 case PALMAS_REG_SMPS123:
1152 if (!pmic->smps123)
1153 continue;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301154 ramp_delay_support = true;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001155 break;
1156 case PALMAS_REG_SMPS45:
1157 case PALMAS_REG_SMPS7:
1158 if (pmic->smps457)
1159 continue;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301160 if (id == PALMAS_REG_SMPS45)
1161 ramp_delay_support = true;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001162 break;
1163 case PALMAS_REG_SMPS457:
1164 if (!pmic->smps457)
1165 continue;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301166 ramp_delay_support = true;
1167 break;
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +05301168 case PALMAS_REG_SMPS10_OUT1:
1169 case PALMAS_REG_SMPS10_OUT2:
Keerthycac9e912014-06-18 15:28:59 +05301170 if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
J Keerthy1ffb0be2013-06-19 11:27:48 +05301171 continue;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301172 }
Nishanth Menoncf910b62014-06-30 10:57:36 -05001173 rinfo = &ddata->palmas_regs_info[id];
Nishanth Menon429222d2014-06-30 10:57:38 -05001174 desc = &pmic->desc[id];
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301175
Sachin Kamat3f4d6362013-05-08 16:09:06 +05301176 if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301177 ramp_delay_support = true;
1178
1179 if (ramp_delay_support) {
Nishanth Menoncf910b62014-06-30 10:57:36 -05001180 addr = rinfo->tstep_addr;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301181 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1182 if (ret < 0) {
Keerthycac9e912014-06-18 15:28:59 +05301183 dev_err(pmic->dev,
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301184 "reading TSTEP reg failed: %d\n", ret);
Sachin Kamat51c86b32013-09-04 12:01:01 +05301185 return ret;
Laxman Dewangan28d1e8c2013-04-18 18:32:47 +05301186 }
Nishanth Menon429222d2014-06-30 10:57:38 -05001187 desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
1188 pmic->ramp_delay[id] = desc->ramp_delay;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001189 }
1190
Axel Linbdc4baa2012-11-29 10:01:44 +08001191 /* Initialise sleep/init values from platform data */
1192 if (pdata && pdata->reg_init[id]) {
1193 reg_init = pdata->reg_init[id];
Keerthycac9e912014-06-18 15:28:59 +05301194 ret = palmas_smps_init(pmic->palmas, id, reg_init);
Axel Linbdc4baa2012-11-29 10:01:44 +08001195 if (ret)
Sachin Kamat51c86b32013-09-04 12:01:01 +05301196 return ret;
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +05301197 } else {
1198 reg_init = NULL;
Axel Linbdc4baa2012-11-29 10:01:44 +08001199 }
1200
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001201 /* Register the regulators */
Nishanth Menon429222d2014-06-30 10:57:38 -05001202 desc->name = rinfo->name;
1203 desc->id = id;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001204
Axel Linfedd89b2012-06-06 20:01:38 +08001205 switch (id) {
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +05301206 case PALMAS_REG_SMPS10_OUT1:
1207 case PALMAS_REG_SMPS10_OUT2:
Nishanth Menon429222d2014-06-30 10:57:38 -05001208 desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
1209 desc->ops = &palmas_ops_smps10;
1210 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1211 PALMAS_SMPS10_CTRL);
1212 desc->vsel_mask = SMPS10_VSEL;
1213 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1214 PALMAS_SMPS10_CTRL);
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +05301215 if (id == PALMAS_REG_SMPS10_OUT1)
Nishanth Menon429222d2014-06-30 10:57:38 -05001216 desc->enable_mask = SMPS10_SWITCH_EN;
Kishon Vijay Abraham I77409d92013-08-12 14:21:14 +05301217 else
Nishanth Menon429222d2014-06-30 10:57:38 -05001218 desc->enable_mask = SMPS10_BOOST_EN;
1219 desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1220 PALMAS_SMPS10_CTRL);
Nishanth Menone0341f12016-04-26 11:36:42 -05001221 desc->bypass_val_on = SMPS10_BYPASS_EN;
Nishanth Menon429222d2014-06-30 10:57:38 -05001222 desc->bypass_mask = SMPS10_BYPASS_EN;
1223 desc->min_uV = 3750000;
1224 desc->uV_step = 1250000;
Axel Linfedd89b2012-06-06 20:01:38 +08001225 break;
1226 default:
Axel Linbdc4baa2012-11-29 10:01:44 +08001227 /*
1228 * Read and store the RANGE bit for later use
1229 * This must be done before regulator is probed,
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +05301230 * otherwise we error in probe with unsupportable
1231 * ranges. Read the current smps mode for later use.
Axel Linbdc4baa2012-11-29 10:01:44 +08001232 */
Nishanth Menoncf910b62014-06-30 10:57:36 -05001233 addr = rinfo->vsel_addr;
Nishanth Menon429222d2014-06-30 10:57:38 -05001234 desc->n_linear_ranges = 3;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001235
1236 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1237 if (ret)
Sachin Kamat51c86b32013-09-04 12:01:01 +05301238 return ret;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001239 if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
1240 pmic->range[id] = 1;
Keerthydbabd622014-05-22 14:48:29 +05301241 if (pmic->range[id])
Nishanth Menon429222d2014-06-30 10:57:38 -05001242 desc->linear_ranges = smps_high_ranges;
Keerthydbabd622014-05-22 14:48:29 +05301243 else
Nishanth Menon429222d2014-06-30 10:57:38 -05001244 desc->linear_ranges = smps_low_ranges;
Axel Linbdc4baa2012-11-29 10:01:44 +08001245
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +05301246 if (reg_init && reg_init->roof_floor)
Nishanth Menon429222d2014-06-30 10:57:38 -05001247 desc->ops = &palmas_ops_ext_control_smps;
Laxman Dewangan32b6d3f2013-08-21 16:18:16 +05301248 else
Nishanth Menon429222d2014-06-30 10:57:38 -05001249 desc->ops = &palmas_ops_smps;
1250 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1251 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1252 rinfo->vsel_addr);
1253 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +05301254
1255 /* Read the smps mode for later use. */
Nishanth Menoncf910b62014-06-30 10:57:36 -05001256 addr = rinfo->ctrl_addr;
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +05301257 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1258 if (ret)
Sachin Kamat51c86b32013-09-04 12:01:01 +05301259 return ret;
Laxman Dewangan51d3a0c2013-04-18 18:32:48 +05301260 pmic->current_reg_mode[id] = reg &
1261 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
Nishanth Menon318dbb02014-06-20 12:26:23 -05001262
Nishanth Menon429222d2014-06-30 10:57:38 -05001263 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1264 rinfo->ctrl_addr);
1265 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
Nishanth Menon318dbb02014-06-20 12:26:23 -05001266 /* set_mode overrides this value */
Nishanth Menon429222d2014-06-30 10:57:38 -05001267 desc->enable_val = SMPS_CTRL_MODE_ON;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001268 }
1269
Nishanth Menon429222d2014-06-30 10:57:38 -05001270 desc->type = REGULATOR_VOLTAGE;
1271 desc->owner = THIS_MODULE;
Axel Linbdc4baa2012-11-29 10:01:44 +08001272
Graeme Gregorya361cd92012-08-28 13:47:40 +02001273 if (pdata)
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001274 config.init_data = pdata->reg_data[id];
1275 else
1276 config.init_data = NULL;
1277
Nishanth Menon429222d2014-06-30 10:57:38 -05001278 desc->supply_name = rinfo->sname;
Keerthycac9e912014-06-18 15:28:59 +05301279 config.of_node = ddata->palmas_matches[id].of_node;
Graeme Gregorya361cd92012-08-28 13:47:40 +02001280
Nishanth Menon429222d2014-06-30 10:57:38 -05001281 rdev = devm_regulator_register(pmic->dev, desc, &config);
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001282 if (IS_ERR(rdev)) {
Keerthycac9e912014-06-18 15:28:59 +05301283 dev_err(pmic->dev,
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001284 "failed to register %s regulator\n",
Keerthycac9e912014-06-18 15:28:59 +05301285 pdev_name);
Sachin Kamat51c86b32013-09-04 12:01:01 +05301286 return PTR_ERR(rdev);
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001287 }
1288
1289 /* Save regulator for cleanup */
1290 pmic->rdev[id] = rdev;
1291 }
1292
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001293 return 0;
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001294}
1295
Keerthyd6f83372014-06-18 15:29:00 +05301296static int tps65917_smps_registration(struct palmas_pmic *pmic,
1297 struct palmas_pmic_driver_data *ddata,
1298 struct palmas_pmic_platform_data *pdata,
1299 const char *pdev_name,
1300 struct regulator_config config)
1301{
1302 int id, ret;
1303 unsigned int addr, reg;
1304 struct regulator_dev *rdev;
1305 struct palmas_reg_init *reg_init;
Nishanth Menoncf910b62014-06-30 10:57:36 -05001306 struct palmas_regs_info *rinfo;
Nishanth Menon429222d2014-06-30 10:57:38 -05001307 struct regulator_desc *desc;
Keerthyd6f83372014-06-18 15:29:00 +05301308
1309 for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
1310 /*
1311 * Miss out regulators which are not available due
1312 * to slaving configurations.
1313 */
Nishanth Menon429222d2014-06-30 10:57:38 -05001314 desc = &pmic->desc[id];
1315 desc->n_linear_ranges = 3;
Keerthybe035302017-05-23 17:46:56 +05301316 if ((id == TPS65917_REG_SMPS2 || id == TPS65917_REG_SMPS1) &&
1317 pmic->smps12)
Keerthyd6f83372014-06-18 15:29:00 +05301318 continue;
1319
1320 /* Initialise sleep/init values from platform data */
1321 if (pdata && pdata->reg_init[id]) {
1322 reg_init = pdata->reg_init[id];
1323 ret = palmas_smps_init(pmic->palmas, id, reg_init);
1324 if (ret)
1325 return ret;
1326 } else {
1327 reg_init = NULL;
1328 }
Nishanth Menoncf910b62014-06-30 10:57:36 -05001329 rinfo = &ddata->palmas_regs_info[id];
Keerthyd6f83372014-06-18 15:29:00 +05301330
1331 /* Register the regulators */
Nishanth Menon429222d2014-06-30 10:57:38 -05001332 desc->name = rinfo->name;
1333 desc->id = id;
Keerthyd6f83372014-06-18 15:29:00 +05301334
1335 /*
1336 * Read and store the RANGE bit for later use
1337 * This must be done before regulator is probed,
1338 * otherwise we error in probe with unsupportable
1339 * ranges. Read the current smps mode for later use.
1340 */
Nishanth Menoncf910b62014-06-30 10:57:36 -05001341 addr = rinfo->vsel_addr;
Keerthyd6f83372014-06-18 15:29:00 +05301342
1343 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1344 if (ret)
1345 return ret;
1346 if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
1347 pmic->range[id] = 1;
1348
1349 if (pmic->range[id])
Nishanth Menon429222d2014-06-30 10:57:38 -05001350 desc->linear_ranges = smps_high_ranges;
1351 else
1352 desc->linear_ranges = smps_low_ranges;
Keerthyd6f83372014-06-18 15:29:00 +05301353
1354 if (reg_init && reg_init->roof_floor)
Nishanth Menon429222d2014-06-30 10:57:38 -05001355 desc->ops = &tps65917_ops_ext_control_smps;
Keerthyd6f83372014-06-18 15:29:00 +05301356 else
Nishanth Menon429222d2014-06-30 10:57:38 -05001357 desc->ops = &tps65917_ops_smps;
1358 desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
1359 desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1360 rinfo->vsel_addr);
1361 desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
1362 desc->ramp_delay = 2500;
Keerthyd6f83372014-06-18 15:29:00 +05301363
1364 /* Read the smps mode for later use. */
Nishanth Menoncf910b62014-06-30 10:57:36 -05001365 addr = rinfo->ctrl_addr;
Keerthyd6f83372014-06-18 15:29:00 +05301366 ret = palmas_smps_read(pmic->palmas, addr, &reg);
1367 if (ret)
1368 return ret;
1369 pmic->current_reg_mode[id] = reg &
1370 PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
Nishanth Menonb6328152014-06-30 10:57:39 -05001371 desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
1372 rinfo->ctrl_addr);
1373 desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
1374 /* set_mode overrides this value */
1375 desc->enable_val = SMPS_CTRL_MODE_ON;
Keerthyd6f83372014-06-18 15:29:00 +05301376
Nishanth Menon429222d2014-06-30 10:57:38 -05001377 desc->type = REGULATOR_VOLTAGE;
1378 desc->owner = THIS_MODULE;
Keerthyd6f83372014-06-18 15:29:00 +05301379
1380 if (pdata)
1381 config.init_data = pdata->reg_data[id];
1382 else
1383 config.init_data = NULL;
1384
Nishanth Menon429222d2014-06-30 10:57:38 -05001385 desc->supply_name = rinfo->sname;
Keerthyd6f83372014-06-18 15:29:00 +05301386 config.of_node = ddata->palmas_matches[id].of_node;
1387
Nishanth Menon429222d2014-06-30 10:57:38 -05001388 rdev = devm_regulator_register(pmic->dev, desc, &config);
Keerthyd6f83372014-06-18 15:29:00 +05301389 if (IS_ERR(rdev)) {
1390 dev_err(pmic->dev,
1391 "failed to register %s regulator\n",
1392 pdev_name);
1393 return PTR_ERR(rdev);
1394 }
1395
1396 /* Save regulator for cleanup */
1397 pmic->rdev[id] = rdev;
1398 }
1399
1400 return 0;
1401}
1402
Keerthycac9e912014-06-18 15:28:59 +05301403static struct of_regulator_match palmas_matches[] = {
1404 { .name = "smps12", },
1405 { .name = "smps123", },
1406 { .name = "smps3", },
1407 { .name = "smps45", },
1408 { .name = "smps457", },
1409 { .name = "smps6", },
1410 { .name = "smps7", },
1411 { .name = "smps8", },
1412 { .name = "smps9", },
1413 { .name = "smps10_out2", },
1414 { .name = "smps10_out1", },
1415 { .name = "ldo1", },
1416 { .name = "ldo2", },
1417 { .name = "ldo3", },
1418 { .name = "ldo4", },
1419 { .name = "ldo5", },
1420 { .name = "ldo6", },
1421 { .name = "ldo7", },
1422 { .name = "ldo8", },
1423 { .name = "ldo9", },
1424 { .name = "ldoln", },
1425 { .name = "ldousb", },
1426 { .name = "regen1", },
1427 { .name = "regen2", },
1428 { .name = "regen3", },
1429 { .name = "sysen1", },
1430 { .name = "sysen2", },
1431};
1432
Keerthyd6f83372014-06-18 15:29:00 +05301433static struct of_regulator_match tps65917_matches[] = {
1434 { .name = "smps1", },
1435 { .name = "smps2", },
1436 { .name = "smps3", },
1437 { .name = "smps4", },
1438 { .name = "smps5", },
Keerthybe035302017-05-23 17:46:56 +05301439 { .name = "smps12",},
Keerthyd6f83372014-06-18 15:29:00 +05301440 { .name = "ldo1", },
1441 { .name = "ldo2", },
1442 { .name = "ldo3", },
1443 { .name = "ldo4", },
1444 { .name = "ldo5", },
1445 { .name = "regen1", },
1446 { .name = "regen2", },
1447 { .name = "regen3", },
1448 { .name = "sysen1", },
1449 { .name = "sysen2", },
1450};
1451
Nishanth Menon4b09e172014-06-30 10:57:34 -05001452static struct palmas_pmic_driver_data palmas_ddata = {
Keerthycac9e912014-06-18 15:28:59 +05301453 .smps_start = PALMAS_REG_SMPS12,
1454 .smps_end = PALMAS_REG_SMPS10_OUT1,
1455 .ldo_begin = PALMAS_REG_LDO1,
1456 .ldo_end = PALMAS_REG_LDOUSB,
1457 .max_reg = PALMAS_NUM_REGS,
Keerthye999c722015-03-17 15:56:05 +05301458 .has_regen3 = true,
Nishanth Menon6839cd62014-06-30 10:57:37 -05001459 .palmas_regs_info = palmas_generic_regs_info,
Keerthycac9e912014-06-18 15:28:59 +05301460 .palmas_matches = palmas_matches,
1461 .sleep_req_info = palma_sleep_req_info,
1462 .smps_register = palmas_smps_registration,
1463 .ldo_register = palmas_ldo_registration,
1464};
1465
Nishanth Menon4b09e172014-06-30 10:57:34 -05001466static struct palmas_pmic_driver_data tps65917_ddata = {
Keerthyd6f83372014-06-18 15:29:00 +05301467 .smps_start = TPS65917_REG_SMPS1,
Keerthybe035302017-05-23 17:46:56 +05301468 .smps_end = TPS65917_REG_SMPS12,
Keerthyd6f83372014-06-18 15:29:00 +05301469 .ldo_begin = TPS65917_REG_LDO1,
1470 .ldo_end = TPS65917_REG_LDO5,
1471 .max_reg = TPS65917_NUM_REGS,
Keerthye999c722015-03-17 15:56:05 +05301472 .has_regen3 = true,
Keerthyd6f83372014-06-18 15:29:00 +05301473 .palmas_regs_info = tps65917_regs_info,
1474 .palmas_matches = tps65917_matches,
1475 .sleep_req_info = tps65917_sleep_req_info,
1476 .smps_register = tps65917_smps_registration,
1477 .ldo_register = tps65917_ldo_registration,
1478};
1479
Nishanth Menon7f091e52016-05-05 19:29:51 -05001480static int palmas_dt_to_pdata(struct device *dev,
1481 struct device_node *node,
1482 struct palmas_pmic_platform_data *pdata,
1483 struct palmas_pmic_driver_data *ddata)
Keerthycac9e912014-06-18 15:28:59 +05301484{
1485 struct device_node *regulators;
1486 u32 prop;
1487 int idx, ret;
1488
Keerthycac9e912014-06-18 15:28:59 +05301489 regulators = of_get_child_by_name(node, "regulators");
1490 if (!regulators) {
1491 dev_info(dev, "regulator node not found\n");
Nishanth Menon7f091e52016-05-05 19:29:51 -05001492 return 0;
Keerthycac9e912014-06-18 15:28:59 +05301493 }
1494
1495 ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
1496 ddata->max_reg);
1497 of_node_put(regulators);
1498 if (ret < 0) {
1499 dev_err(dev, "Error parsing regulator init data: %d\n", ret);
Nishanth Menon7f091e52016-05-05 19:29:51 -05001500 return 0;
Keerthycac9e912014-06-18 15:28:59 +05301501 }
1502
1503 for (idx = 0; idx < ddata->max_reg; idx++) {
Julia Lawall96e4f522017-05-04 22:10:51 +02001504 struct of_regulator_match *match;
Nishanth Menon1b424432016-05-05 19:29:50 -05001505 struct palmas_reg_init *rinit;
Nishanth Menon6c7d6142016-05-05 19:29:52 -05001506 struct device_node *np;
Nishanth Menon036d1932016-05-05 19:29:49 -05001507
1508 match = &ddata->palmas_matches[idx];
Nishanth Menon6c7d6142016-05-05 19:29:52 -05001509 np = match->of_node;
Nishanth Menon036d1932016-05-05 19:29:49 -05001510
Nishanth Menon6c7d6142016-05-05 19:29:52 -05001511 if (!match->init_data || !np)
Keerthycac9e912014-06-18 15:28:59 +05301512 continue;
1513
Nishanth Menon1b424432016-05-05 19:29:50 -05001514 rinit = devm_kzalloc(dev, sizeof(*rinit), GFP_KERNEL);
Nishanth Menon7f091e52016-05-05 19:29:51 -05001515 if (!rinit)
1516 return -ENOMEM;
1517
Nishanth Menon036d1932016-05-05 19:29:49 -05001518 pdata->reg_data[idx] = match->init_data;
Nishanth Menon1b424432016-05-05 19:29:50 -05001519 pdata->reg_init[idx] = rinit;
Keerthycac9e912014-06-18 15:28:59 +05301520
Nishanth Menon6c7d6142016-05-05 19:29:52 -05001521 rinit->warm_reset = of_property_read_bool(np, "ti,warm-reset");
1522 ret = of_property_read_u32(np, "ti,roof-floor", &prop);
Keerthycac9e912014-06-18 15:28:59 +05301523 /* EINVAL: Property not found */
1524 if (ret != -EINVAL) {
1525 int econtrol;
1526
1527 /* use default value, when no value is specified */
1528 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1529 if (!ret) {
1530 switch (prop) {
1531 case 1:
1532 econtrol = PALMAS_EXT_CONTROL_ENABLE1;
1533 break;
1534 case 2:
1535 econtrol = PALMAS_EXT_CONTROL_ENABLE2;
1536 break;
1537 case 3:
1538 econtrol = PALMAS_EXT_CONTROL_NSLEEP;
1539 break;
1540 default:
1541 WARN_ON(1);
1542 dev_warn(dev,
1543 "%s: Invalid roof-floor option: %u\n",
Nishanth Menon036d1932016-05-05 19:29:49 -05001544 match->name, prop);
Keerthycac9e912014-06-18 15:28:59 +05301545 break;
1546 }
1547 }
Nishanth Menon1b424432016-05-05 19:29:50 -05001548 rinit->roof_floor = econtrol;
Keerthycac9e912014-06-18 15:28:59 +05301549 }
1550
Nishanth Menon6c7d6142016-05-05 19:29:52 -05001551 ret = of_property_read_u32(np, "ti,mode-sleep", &prop);
Keerthycac9e912014-06-18 15:28:59 +05301552 if (!ret)
Nishanth Menon1b424432016-05-05 19:29:50 -05001553 rinit->mode_sleep = prop;
Keerthycac9e912014-06-18 15:28:59 +05301554
Nishanth Menon6c7d6142016-05-05 19:29:52 -05001555 ret = of_property_read_bool(np, "ti,smps-range");
Keerthycac9e912014-06-18 15:28:59 +05301556 if (ret)
Nishanth Menon1b424432016-05-05 19:29:50 -05001557 rinit->vsel = PALMAS_SMPS12_VOLTAGE_RANGE;
Keerthycac9e912014-06-18 15:28:59 +05301558
1559 if (idx == PALMAS_REG_LDO8)
1560 pdata->enable_ldo8_tracking = of_property_read_bool(
Nishanth Menon6c7d6142016-05-05 19:29:52 -05001561 np, "ti,enable-ldo8-tracking");
Keerthycac9e912014-06-18 15:28:59 +05301562 }
1563
1564 pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
Nishanth Menon7f091e52016-05-05 19:29:51 -05001565
1566 return 0;
Keerthycac9e912014-06-18 15:28:59 +05301567}
1568
Fabian Frederickcdbf6f02015-03-16 20:17:08 +01001569static const struct of_device_id of_palmas_match_tbl[] = {
Keerthycac9e912014-06-18 15:28:59 +05301570 {
1571 .compatible = "ti,palmas-pmic",
1572 .data = &palmas_ddata,
1573 },
1574 {
1575 .compatible = "ti,twl6035-pmic",
1576 .data = &palmas_ddata,
1577 },
1578 {
1579 .compatible = "ti,twl6036-pmic",
1580 .data = &palmas_ddata,
1581 },
1582 {
1583 .compatible = "ti,twl6037-pmic",
1584 .data = &palmas_ddata,
1585 },
1586 {
1587 .compatible = "ti,tps65913-pmic",
1588 .data = &palmas_ddata,
1589 },
1590 {
1591 .compatible = "ti,tps65914-pmic",
1592 .data = &palmas_ddata,
1593 },
1594 {
1595 .compatible = "ti,tps80036-pmic",
1596 .data = &palmas_ddata,
1597 },
1598 {
1599 .compatible = "ti,tps659038-pmic",
1600 .data = &palmas_ddata,
1601 },
Keerthyd6f83372014-06-18 15:29:00 +05301602 {
1603 .compatible = "ti,tps65917-pmic",
1604 .data = &tps65917_ddata,
1605 },
Graeme Gregorya361cd92012-08-28 13:47:40 +02001606 { /* end */ }
1607};
1608
Keerthycac9e912014-06-18 15:28:59 +05301609static int palmas_regulators_probe(struct platform_device *pdev)
1610{
1611 struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
1612 struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
1613 struct device_node *node = pdev->dev.of_node;
1614 struct palmas_pmic_driver_data *driver_data;
1615 struct regulator_config config = { };
1616 struct palmas_pmic *pmic;
1617 const char *pdev_name;
1618 const struct of_device_id *match;
1619 int ret = 0;
1620 unsigned int reg;
1621
1622 match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
1623
1624 if (!match)
1625 return -ENODATA;
1626
1627 driver_data = (struct palmas_pmic_driver_data *)match->data;
1628 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1629 if (!pdata)
1630 return -ENOMEM;
1631
1632 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
1633 if (!pmic)
1634 return -ENOMEM;
1635
Keerthye999c722015-03-17 15:56:05 +05301636 if (of_device_is_compatible(node, "ti,tps659038-pmic")) {
Keerthye03826d2015-03-17 15:56:04 +05301637 palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr =
1638 TPS659038_REGEN2_CTRL;
Keerthye999c722015-03-17 15:56:05 +05301639 palmas_ddata.has_regen3 = false;
1640 }
Keerthye03826d2015-03-17 15:56:04 +05301641
Keerthycac9e912014-06-18 15:28:59 +05301642 pmic->dev = &pdev->dev;
1643 pmic->palmas = palmas;
1644 palmas->pmic = pmic;
1645 platform_set_drvdata(pdev, pmic);
1646 pmic->palmas->pmic_ddata = driver_data;
1647
Nishanth Menon7f091e52016-05-05 19:29:51 -05001648 ret = palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
1649 if (ret)
1650 return ret;
Keerthycac9e912014-06-18 15:28:59 +05301651
1652 ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, &reg);
1653 if (ret)
1654 return ret;
1655
Keerthybe035302017-05-23 17:46:56 +05301656 if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) {
Keerthycac9e912014-06-18 15:28:59 +05301657 pmic->smps123 = 1;
Keerthybe035302017-05-23 17:46:56 +05301658 pmic->smps12 = 1;
1659 }
Keerthycac9e912014-06-18 15:28:59 +05301660
1661 if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
1662 pmic->smps457 = 1;
1663
1664 config.regmap = palmas->regmap[REGULATOR_SLAVE];
1665 config.dev = &pdev->dev;
1666 config.driver_data = pmic;
1667 pdev_name = pdev->name;
1668
1669 ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
1670 config);
1671 if (ret)
1672 return ret;
1673
1674 ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
1675 config);
1676
1677 return ret;
1678}
1679
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001680static struct platform_driver palmas_driver = {
1681 .driver = {
1682 .name = "palmas-pmic",
Graeme Gregorya361cd92012-08-28 13:47:40 +02001683 .of_match_table = of_palmas_match_tbl,
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001684 },
Laxman Dewanganbbcf50b2013-03-18 14:59:49 +05301685 .probe = palmas_regulators_probe,
Graeme Gregorye5ce4202012-05-18 16:53:57 +01001686};
1687
1688static int __init palmas_init(void)
1689{
1690 return platform_driver_register(&palmas_driver);
1691}
1692subsys_initcall(palmas_init);
1693
1694static void __exit palmas_exit(void)
1695{
1696 platform_driver_unregister(&palmas_driver);
1697}
1698module_exit(palmas_exit);
1699
1700MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
1701MODULE_DESCRIPTION("Palmas voltage regulator driver");
1702MODULE_LICENSE("GPL");
1703MODULE_ALIAS("platform:palmas-pmic");
Graeme Gregorya361cd92012-08-28 13:47:40 +02001704MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);