Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 6d624eabcd4bd11f1304b12f7409a48d3a7743e6 / . / arch / arm / boot / dts / omap2.dtsi
blob: f39b237b9011871976c14b20b05dec157ced8162 [file] [log] [blame]
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]1/*
2 * Device Tree Source for OMAP2 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussard6d624ea2013-05-31 14:32:56 +0200[diff] [blame^]11#include <dt-bindings/gpio/gpio.h>
12
Florian Vaussard98ef79572013-05-31 14:32:55 +0200[diff] [blame]13#include "skeleton.dtsi"
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]14
15/ {
16 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]17 interrupt-parent = <&intc>;
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]18
19 aliases {
20 serial0 = &uart1;
21 serial1 = &uart2;
22 serial2 = &uart3;
23 };
24
25 cpus {
26 cpu@0 {
27 compatible = "arm,arm1136jf-s";
28 };
29 };
30
Jon Hunter9b07b472012-10-18 09:28:52 -0500[diff] [blame]31 pmu {
32 compatible = "arm,arm1136-pmu";
33 interrupts = <3>;
34 };
35
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]36 soc {
37 compatible = "ti,omap-infra";
38 mpu {
39 compatible = "ti,omap2-mpu";
40 ti,hwmods = "mpu";
41 };
42 };
43
44 ocp {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges;
49 ti,hwmods = "l3_main";
50
51 intc: interrupt-controller@1 {
52 compatible = "ti,omap2-intc";
53 interrupt-controller;
54 #interrupt-cells = <1>;
Jon Hunter95dca122012-06-12 19:40:46 -0500[diff] [blame]55 ti,intc-size = <96>;
56 reg = <0x480FE000 0x1000>;
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]57 };
58
Jon Hunter2c2dc542012-04-26 13:47:59 -0500[diff] [blame]59 sdma: dma-controller@48056000 {
60 compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
61 reg = <0x48056000 0x1000>;
62 interrupts = <12>,
63 <13>,
64 <14>,
65 <15>;
66 #dma-cells = <1>;
67 #dma-channels = <32>;
68 #dma-requests = <64>;
69 };
70
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]71 uart1: serial@4806a000 {
72 compatible = "ti,omap2-uart";
73 ti,hwmods = "uart1";
74 clock-frequency = <48000000>;
75 };
76
77 uart2: serial@4806c000 {
78 compatible = "ti,omap2-uart";
79 ti,hwmods = "uart2";
80 clock-frequency = <48000000>;
81 };
82
83 uart3: serial@4806e000 {
84 compatible = "ti,omap2-uart";
85 ti,hwmods = "uart3";
86 clock-frequency = <48000000>;
87 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]88
89 timer2: timer@4802a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]90 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]91 reg = <0x4802a000 0x400>;
92 interrupts = <38>;
93 ti,hwmods = "timer2";
94 };
95
96 timer3: timer@48078000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]97 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]98 reg = <0x48078000 0x400>;
99 interrupts = <39>;
100 ti,hwmods = "timer3";
101 };
102
103 timer4: timer@4807a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]104 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]105 reg = <0x4807a000 0x400>;
106 interrupts = <40>;
107 ti,hwmods = "timer4";
108 };
109
110 timer5: timer@4807c000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]111 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]112 reg = <0x4807c000 0x400>;
113 interrupts = <41>;
114 ti,hwmods = "timer5";
115 ti,timer-dsp;
116 };
117
118 timer6: timer@4807e000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]119 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]120 reg = <0x4807e000 0x400>;
121 interrupts = <42>;
122 ti,hwmods = "timer6";
123 ti,timer-dsp;
124 };
125
126 timer7: timer@48080000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]127 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]128 reg = <0x48080000 0x400>;
129 interrupts = <43>;
130 ti,hwmods = "timer7";
131 ti,timer-dsp;
132 };
133
134 timer8: timer@48082000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]135 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]136 reg = <0x48082000 0x400>;
137 interrupts = <44>;
138 ti,hwmods = "timer8";
139 ti,timer-dsp;
140 };
141
142 timer9: timer@48084000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]143 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]144 reg = <0x48084000 0x400>;
145 interrupts = <45>;
146 ti,hwmods = "timer9";
147 ti,timer-pwm;
148 };
149
150 timer10: timer@48086000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]151 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]152 reg = <0x48086000 0x400>;
153 interrupts = <46>;
154 ti,hwmods = "timer10";
155 ti,timer-pwm;
156 };
157
158 timer11: timer@48088000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]159 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]160 reg = <0x48088000 0x400>;
161 interrupts = <47>;
162 ti,hwmods = "timer11";
163 ti,timer-pwm;
164 };
165
166 timer12: timer@4808a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]167 compatible = "ti,omap2420-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]168 reg = <0x4808a000 0x400>;
169 interrupts = <48>;
170 ti,hwmods = "timer12";
171 ti,timer-pwm;
172 };
Tony Lindgrenf20b9332011-12-16 14:13:09 -0800[diff] [blame]173 };
174};